UNIT-3

Programmable Digital Signal Processors

3.1 Introduction:
Leading manufacturers of integrated circuits such as Texas Instruments (TI), Analog devices &
Motorola manufacture the digital signal processor (DSP) chips. These manufacturers have developed a
range of DSP chips with varied complexity.
The TMS320 family consists of two types of single chips DSPs: 16-bit fixed point &32-bit floating-
point. These DSPs possess the operational flexibility of high-speed controllers and the numerical
capability of array processors

3.2 Commercial Digital Signal-Processing Devices:

There are several families of commercial DSP devices. Right from the early eighties, when
these devices began to appear in the market, they have been used in numerous applications, such as
communication, control, computers, Instrumentation, and consumer electronics. The architectural
features and the processing power of these devices have been constantly upgraded based on the
advances in technology and the application needs. However, their basic versions, most of them have
Harvard architecture, a single-cycle hardware multiplier, an address generation unit with dedicated
address registers, special addressing modes, on-chip peripherals interfaces. Of the various families of
programmable DSP devices that are commercially available, the three most popular ones are those
from Texas Instruments, Motorola, and Analog Devices. Texas Instruments was one of the first to
come out with a commercial programmable DSP with the introduction of its TMS32010 in 1982.

Summary of the Architectural Features of three fixed-Points DSPs

3.3. The architecture of TMS320C54xx digital signal processors:

TMS320C54xx processors retain in the basic Harvard architecture of their predecessor,

TMS320C25, but have several additional features, which improve their performance over it. Figure 3.1
shows a functional block diagram of TMS320C54xx processors. They have one program and three
data memory spaces with separate buses, which provide simultaneous accesses to program instruction
and two data operands and enables writing of result at the same time. Part of the memory is
implemented on-chip and consists of combinations of ROM, dual-access RAM, and single-access
RAM. Transfers between the memory spaces are also possible.
The central processing unit (CPU) of TMS320C54xx processors consists of a 40- bit arithmetic
logic unit (ALU), two 40-bit accumulators, a barrel shifter, a 17x17 multiplier, a 40-bit adder, data
address generation logic (DAGEN) with its own arithmetic unit, and program address generation logic
(PAGEN). These major functional units are supported by a number of registers and logic in the
architecture. A powerful instruction set with a hardware-supported, single-instruction repeat and block
repeat operations, block memory move instructions, instructions that pack two or three simultaneous
reads, and arithmetic instructions with parallel store and load make these devices very efficient for
running high-speed DSP algorithms.
Several peripherals, such as a clock generator, a hardware timer, a wait state generator, parallel
I/O ports, and serial I/O ports, are also provided on-chip. These peripherals make it convenient to
interface the signal processors to the outside world. In these following sections, we examine in detail
the various architectural features of the TMS320C54xx family of processors.
 Figure 3.1.Functional architecture for TMS320C54xx processors.

3.3.1 Bus Structure:

The performance of a processor gets enhanced with the provision of multiple buses to provide
simultaneous access to various parts of memory or peripherals. The 54xx architecture is built around
four pairs of 16-bit buses with each pair consisting of an address bus and a data bus. As shown in
Figure
3.1, these are The program bus pair (PAB, PB); which carries the instruction code from the program
memory. Three data bus pairs (CAB, CB; DAB, DB; and EAB, EB); which interconnected the various
units within the CPU. In Addition the pair CAB, CB and DAB, DB are used to read from the data
memory, while The pair EAB, EB; carries the data to be written to the memory. The ‘54xxcan
generate up to two data-memory addresses per cycle using the two auxiliary register arithmeticunit
(ARAU0 and ARAU1) in the DAGEN block. This enables accessing two operands simultaneously.

3.3.2 Central Processing Unit (CPU):

The ‘54xx CPU is common to all the ‘54xx devices. The ’54xx CPU contains a 40-
bitarithmetic logic unit (ALU); two 40-bit accumulators (A and B); a barrel shifter; a
17 x 17-bit multiplier; a 40-bit adder; a compare, select and store unit (CSSU); an exponent
encoder(EXP); a data address generation unit (DAGEN); and a program address generation unit
(PAGEN).
The ALU performs 2’s complement arithmetic operations and bit-level Boolean operations on
16, 32, and 40-bit words. It can also function as two separate 16-bit ALUs
and perform two 16-bit operations simultaneously. Figure 3.2 show the functional diagram of the ALU
of the TMS320C54xx family of devices.

Accumulators A and B store the output from the ALU or the multiplier/adder block and provide a
second input to the ALU. Each accumulators is divided into three parts: guards bits (bits 39-32), high-
order word (bits-31-16), and low-order word (bits 15- 0), which can be stored and retrieved
individually. Each accumulator is memory-mapped and partitioned. It can be configured as the
destination registers. The guard bits are used as a head margin for computations.
Figure 3.2.Functional diagram of the central processing unit of the TMS320C54xxprocessors.
Barrel shifter: provides the capability to scale the data during an operand read or write.
No overhead is required to implement the shift needed for the scaling operations. The’54xx barrel
shifter can produce a left shift of 0 to 31 bits or a right shift of 0 to 16 bits on the input data. The shift
count field of status registers ST1, or in the temporary
register T. Figure 3.3 shows the functional diagram of the barrel shifter of TMS320C54xx processors.
The barrel shifter and the exponent encoder normalize the values in an accumulator in a single cycle.
The LSBs of the output are filled with0s, and the MSBs can be either zero filled or sign extended,
depending on the state of the sign-extension mode bit in the status register ST1. An additional shift
capability enables the processor to perform numerical scaling, bit extraction, extended arithmetic, and
overflow prevention operations.
 Figure 3.3.Functional diagram of the barrel shifter

Multiplier/adder unit: The kernel of the DSP device architecture is multiplier/adder unit. The
multiplier/adder unit of TMS320C54xx devices performs 17 x 17 2’s complement multiplication with
a 40-bit addition effectively in a single instruction cycle.
In addition to the multiplier and adder, the unit consists of control logic for integer and
fractional computations and a 16-bit temporary storage register, T. Figure 3.4 show the functional
diagram of the multiplier/adder unit of TMS320C54xx processors. The compare, select, and store unit
(CSSU) is a hardware unit specifically incorporated to accelerate the add/compare/select operation.
This operation is essential to implement the Viterbi algorithm used in many signal-processing
applications. The exponent encoder unit supports the EXP instructions, which stores in the T register
the number of leading redundant bits of the accumulator content. This information is useful while
shifting the accumulator content for the purpose of scaling.
 Figure 3.4. Functional diagram of the multiplier/adder unit of TMS320C54xx processors.
3.3.3 Internal Memory and Memory-Mapped Registers:
The amount and the types of memory of a processor have direct relevance to the efficiency and
performance obtainable in implementations with the processors. The ‘54xx memory is organized into
three individually selectable spaces: program, data, and I/O spaces. All ‘54xx devices contain both
RAM and ROM. RAM can be either dual-access type (DARAM) or single-access type (SARAM).
Theon-chip RAM for these processors is organized in pages having 128 word locations on each page.
The ‘54xx processors have a number of CPU registers to support operand addressing and
computations. The CPU registers and peripherals registers are all located on page 0 of the data
memory. Figure 3.5(a) and (b) shows the internal CPU registers and peripheral registers with their
addresses. The processors mode status (PMST) registers
that is used to configure the processor. It is a memory-mapped register located at address 1Dh on page
0 of the RAM. A part of on-chip ROM may contain a boot loader and look-up tables for function such
as sine, cosine, μ- law, and A- law.

Figure 3.5(a) Internal memory-mapped registers of TMS320C54xx processors

 Figure 3.5(b).peripheral registers for the TMS320C54xx processors

Status registers (ST0,ST1):

ST0: Contains the status of flags (OVA, OVB, C, TC) produced by arithmetic operations
& bit manipulations.
ST1: Contain the status of various conditions & modes. Bits of ST0&ST1registers can be set or clear
with the SSBX & RSBX instructions.
PMST: Contains memory-setup status & control information.
 Figure 3.6(a). ST0 diagram

ARP: Auxiliary register pointer.

TC: Test/control flag.
C: Carry bit.
OVA: Overflow flag for accumulator A.
OVB: Overflow flag for accumulator B.
DP: Data-memory page pointer.

Figure 3.6(b). ST1 diagram

BRAF: Block repeat active flag
BRAF=0, the block repeat is deactivated.
BRAF=1, the block repeat is activated.

CPL: Compiler mode

CPL=0, the relative direct addressing mode using data page pointer is selected.
CPL=1, the relative direct addressing mode using stack pointer is selected.

HM: Hold mode, indicates whether the processor continues internal execution or acknowledge for
external interface.

INTM: Interrupt mode, it globally masks or enables all interrupts.

INTM=0_all unmasked interrupts are enabled.
INTM=1_all masked interrupts are disabled.
0: Always read as 0

OVM: Overflow mode.

OVM=1_the destination accumulator is set either the most positive value or the most negative value.
OVM=0_the overflowed result is in destination accumulator.
SXM: Sign extension mode.
SXM=0 _Sign extension is suppressed.

SXM=1_Data is sign extended

C16: Dual 16 bit/double-Precision arithmetic mode.

C16=0_ALU operates in double-Precision arithmetic mode.
C16=1_ALU operates in dual 16-bit arithmetic mode.

FRCT: Fractional mode.

FRCT=1_the multiplier output is left-shifted by 1bit to compensate an extra sign bit.

CMPT: Compatibility mode.

CMPT=0_ ARP is not updated in the indirect addressing mode.
CMPT=1_ARP is updated in the indirect addressing mode.

ASM: Accumulator Shift Mode.

5 bit field, & specifies the Shift value within -16 to 15 range.

Processor Mode Status Register (PMST):

INTR: Interrupt vector pointer, point to the 128-word program page where the interrupt vectors
reside.
MP/MC: Microprocessor/Microcomputer mode,
MP/MC=0, the on chip ROM is enabled.
MP/MC=1, the on chip ROM is enabled.

OVLY: RAM OVERLAY, OVLY enables on chip dual access data RAM blocks to be mapped into
program space.

AVIS: It enables/disables the internal program address to be visible at the address pins.
DROM: Data ROM, DROM enables on-chip ROM to be mapped into data space.
CLKOFF: CLOCKOUT off.

SMUL: Saturation on Multiplication

SST: Saturation on Store.

3.4 Data Addressing Modes of TMS320C54X Processors:

Data addressing modes provide various ways to access operands to execute instructions and place
results in the memory or the registers. The 54XX devices offer seven basic addressing modes
1. Immediate addressing.
2. Absolute addressing.
3. Accumulator addressing.
4. Direct addressing.
5. Indirect addressing.
6. Memory mapped addressing
7. Stack addressing.

3.4.1 Immediate addressing:

The instruction contains the specific value of the operand. The operand can be short (3,5,8 or 9
bit in length) or long (16 bits in length). The instruction syntax for short operands occupies one
memory location,
Example: LD #20, DP.
RPT #0FFFFh.

3.4.2 Absolute Addressing:

The instruction contains a specified address in the operand.
1. Dmad addressing. MVDK Smem,dmad, MVDM dmad,MMR
2. Pmad addressing. MVDP Smem,pmad, MVPD pmem,Smad
3. PA addressing. PORTR PA, Smem,
4.*(lk) addressing .

3.4.3 Accumulator Addressing:

Accumulator content is used as address to transfer data between Program and Data memory.
Ex: READA *AR2

3.4.4 Direct Addressing:

Base address + 7 bits of value contained in instruction = 16 bit address. A page of 128
locations can be accessed without change in DP or SP.Compiler mode bit (CPL) in ST1 register is
used.

If CPL = 0 Selects DP
CPL = 1 selects SP,
It should be remembered that when SP is used instead of DP, the effective address iscomputed by adding the 7-bit offset to
SP
Figure 3.7 Block diagram of the direct addressing mode for TMS320C54xx Processors.
3.4.1Indirect Addressing:

TMS320C54xx have 8, 16 bit auxiliary register (AR0 – AR 7). Two auxiliary register arithmetic units
(ARAU0 & ARAU1)
Used to access memory location in fixed step size. AR0 register is used for indexed and bit reverse
addressing modes.
– operand addressing
MOD _ type of indirect addressing
ARF _ AR used for addressing
ARP depends on (CMPT) bit in ST1
CMPT = 0, Standard mode, ARP set to zero
CMPT = 1, Compatibility mode, Particularly AR selected by ARP
 Table 3.2 Indirect addressing options with a single data –memory operand.
Circular Addressing;
 Used in convolution, correlation and FIR filters.
 A circular buffer is a sliding window contains most recent data. Circular buffer of size R must
start on a N-bit boundary, where 2N > R .

 Effective base address (EFB): By zeroing the N LSBs of a user selected AR (ARx).

If 0 _ index + step < BK ; index = index +step;
else if index + step _ BK ; index = index + step - BK;
else if index + step < 0; index + step + BK
Bit-Reversed Addressing:
o Used for FFT algorithms.
o AR0 specifies one half of the size of the FFT.
o The value of AR0 = 2N-1: N = integer FFT size = 2N
o AR0 + AR (selected register) = bit reverse addressing.
o The carry bit propagating from left to right.

Dual-Operand Addressing:
Dual data-memory operand addressing is used for instruction that simultaneously
perform two reads (32-bit read) or a single read (16-bit read) and a parallel store (16-bit
store) indicated by two vertical bars, II. These instructions access operands using indirect addressing
mode.
If in an instruction with a parallel store the source operand the destination operand point to the
same location, the source is read before writing to the destination. Only 2 bits are available in the
instruction code for selecting each auxiliary register in this mode. Thus, just four of the auxiliary
registers, AR2-AR5, can be used, The ARAUs together with these registers, provide capability to
access two operands in a single cycle. Figure 3.11 shows how an address is generated using dual data-
memory operand addressing.
 3.4.6. Memory-Mapped Register Addressing:
 Used to modify the memory-mapped registers without affecting the current data page
 pointer (DP) or stack-pointer (SP)
o Overhead for writing to a register is minimal
o Works for direct and indirect addressing
o Scratch –pad RAM located on data PAGE0 can be modified
 STM #x, DIRECT
 STM #tbl, AR1

3.4.7 Stack Addressing:

• Used to automatically store the program counter during interrupts and subroutines.
• Can be used to store additional items of context or to pass data values.
• Uses a 16-bit memory-mapped register, the stack pointer (SP).
• PSHD X2
3.5. Memory Space of TMS320C54xx Processors
 A total of 128k words extendable up to 8192k words.
 Total memory includes RAM, ROM, EPROM, EEPROM or Memory mapped peripherals.
 mapped
registers.
Figure 3.14 Memory map for the TMS320C5416 Processor.
3.6. Program Control
 It contains program counter (PC), the program counter related H/W, hard stack, repeat
counters &status registers.
 PC addresses memory in several ways namely:
 Branch: The PC is loaded with the immediate value following the branch instruction
 Subroutine call: The PC is loaded with the immediate value following the call instruction
 Interrupt: The PC is loaded with the address of the appropriate interrupt vector.
 Instructions such as BACC, CALA, etc ;The PC is loaded with the contents of the accumulator
low word
 End of a block repeat loop: The PC is loaded with the contents of the block repeat
programaddress start register.
 Return: The PC is loaded from the top of the stack.
Problems:
1. Assuming the current content of AR3 to be 200h, what will be its contents
aftereach of the following TMS320C54xx addressing modes is used? Assume that the
contents of AR0 are 20h.
a. *AR3+0
b. *AR3-0
c. *AR3+
d. *AR3
e. *AR3
f. *+AR3 (40h)
g. *+AR3 (-40h)
Solution:
a. AR3 ← AR3 + AR0; AR3
= 200h + 20h = 220h
b. AR3← AR3 - AR0;
AR3 = 200h - 20h = 1E0h
c. AR3 ← AR3 + 1; AR3
= 200h + 1 = 201h
d. AR3 ← AR3 - 1; AR3
= 200h - 1 = 1FFh
e. AR3 is not modified.
AR3 = 200h
f. AR3 ← AR3 + 40h; AR3
= 200 + 40h = 240h
g. AR3 ← AR3 - 40h; AR3
= 200 - 40h = 1C0h
 2. Assuming the current contents of AR3 to be 200h, what will be its contents after
each of the following TMS320C54xx addressing modes is used? Assume that
the contents of AR0 are20h
a. *AR3 + 0B
b. *AR3 – 0B
Solution:
a. AR3 ← AR3 + AR0 with reverse
carry propagation; AR3 = 200h + 20h
(with reverse carry propagation) =
220h.
b. AR3 ← AR3 - AR0 with reverse
carry propagation; AR3 = 200h - 20h
(with reverse carry propagation) =
23Fh.

3.7 On chip peripherals:

It facilitates interfacing with external devices. The peripherals are:
 General purpose I/O pins
 A software programmable wait state generator.
 Hardware timer
 Host port interface (HPI)
 Clock generator
 Serial port

3.7.1 It has two general purpose I/O pins:

 BIO-input pin used to monitor the status of external devices.

 XF- output pin, software controlled used to signal external devices

3.7.2 Software programmable wait state generator:

 Extends external bus cycles up to seven machine cycles.

3.7.3 Hardware Timer




of 3 memory mapped registers:

 The timer register (TIM)
 Timer period register (PRD)
 Timer controls register (TCR)
• Pre scaler block (PSC).
• TDDR (Time Divide Down ratio)
• TIN &TOUT

The timer register (TIM) is a 16-bit memory-mapped register that decrements at

every pulse from the prescaler block (PSC).
The timer period register (PRD) is a 16-bit memory-mapped register whose
contents are loaded onto the TIM whenever the TIM decrements to zero or the
device is reset (SRESET).
The timer can also be independently reset using the TRB signal. The
timer control register (TCR) is a 16-bit memory-mapped register that contains
status and control bits. Table shows the functions of the various bits in the TCR.
The prescaler block is also an on-chip counter. Whenever the prescaler
bits count down to 0, a clock pulse is given to the TIM register that decrements
the TIM register by 1. The TDDR bits contain the divide-down ratio, which is
loaded onto the prescaler block after each time the prescaler bits count down to 0.
That is to say that the 4-bit value of TDDR determines the divide-by ratio
of the timer clock with respect to the system clock. In other words, the TIM
decrements either at the rate of the system clock or at a rate slower than that as
decided by the value of the TDDR bits. TOUT and TINT are the output signal
generated as the TIM register decrements to 0. TOUT can trigger the start of the
conversion signal in an ADC interfaced to the DSP.
The sampling frequency of the ADC determines how frequently it
receives the TOUT signal. TINT is used to generate interrupts, which are
required to service a peripheral such as a DRAM controller periodically. The
timer can also be stopped, restarted, reset, or disabled by specific status bits.
3.8 Interrupts of TMS320C54xx Processors:
Many times, when CPU is in the midst of executing a program, a
peripheral device may requirea service from the CPU. In such a situation, the
main program may be interrupted by a signal generated by the peripheral devices.
This results in the processor suspending the main program in order to execute
another program, called interrupt service routine, to service the peripheral device.
On completion of the interrupt service routine, the processor returns to the main
program to continue fromwhere it left.
Interrupt may be generated either by an internal or an external device. It may also
be generated by software. Not all interrupts are serviced when they occur. Only
those interrupts that are called nonmaskable are serviced whenever they occur.
Other interrupts, which are called maskable interrupts,are serviced only if they
are enabled. There is also a priority to determine which interrupt gets
servicedfirst if more than one interrupts occur simultaneously.
Almost all the devices of TMS320C54xx family have 32 interrupts. However,
the types and the number under each type vary from device to device. Some of these
interrupts are reserved for use by the CPU.

3.9 Pipeline operation of TMS320C54xx Processors:

The CPU of ‘54xx devices have a six-level-deep instruction pipeline. The
six stages of the pipeline are independent of each other. This allows overlapping
execution of instructions. During any given cycle, up to six different instructions
can be active, each at a different stage of processing. The six levels of the
pipeline structure are program prefetch, program fetch, decode, access, read and
execute. 1 During program prefetch, the program address bus, PAB, is loaded
with the address of the next instruction to be fetched.
2 In the fetch phase, an instruction word is fetched from the program bus, PB,
and loaded into the instruction register, IR. These two phases from the
instruction
fetch sequence.
3 During the decode stage, the contents of the instruction register, IR are
decoded to determine thetype of memory access operation and the control
signals required for the data-address generation unit and the CPU.
4 The access phase outputs the read operand’s on the data address bus, DAB. If
a second operand is required, the other data address bus, CAB, also loaded with
an appropriate address. Auxiliary registers in indirect addressing mode and the
stack pointer (SP) are also updated.
5 In the read phase the data operand(s), if any, are read from the data buses,
DB and CB. This phase completes the two-phase read process and starts the two
phase write processes. The data address of thewrite operand, if any, is loaded
into the data write address bus, EAB.
6 The execute phase writes the data using the data write bus, EB, and
completes the operand write sequence. The instruction is executed in this
phase.
 UNIT-IV
Analog Devices Family of DSP Devices:
ALU Block Diagram:

MAC (Multiplier and Accumulate):

Shifter Instructions:
Base Architecture of ADSP 2100:
The ASDP-2100 is a programmable single-Chip microprocessor optimized for digital signal
processing (DSP) and other high-speed numeric processing applications. The ADSP-2100 chip
contains an ALU, a multiplier/accumulator, a barrel shifter, two data address generators and a
program sequencer; data and program memories are external. The ADSP- 2100 A is a pin-and code-
compatible version of the original ADSP-2100 fabricated, in 1.0- µm CMOS. It can operate at a faster
clock rate than the ADSP-2100
This section gives a broad overview of the ADSP-2100 internal architecture,
using Figure 1.1 to show the architecture of the ADSP-2100processor.
The ADSP-2100 processor contains three full-function and independent
computational units: an arithmetic/logic unit, a multiplier/accumulatorand a barrel shifter.
The computational units process 16-bit data directly and provide for multiprecision
computation.
Two dedicated data address generators and a complete program sequencer supply
addresses. The sequencer supports single-cycle conditional branching and executes
program loops with zero overhead. Dual address generators allow the processor to output
simultaneous addresses for dual operand fetches. Together the sequencer and data address
generators allow computational operations to execute with maximum efficiency. The
ADSP- 2100 family uses a modified Harvard architecture in which data memory stores
data, and program memory stores both instructions and data. Able to store data in both
program and data memory, ADSP-2100 processors are capable of fetching two operandson
the same instruction cycle.

The internal components are supported by five internal buses.

• Program Memory Address (PMA) bus
• Program Memory Data (PMD) bus
• Data Memory Address (DMA) bus
• Data Memory Data (DMD) bus
• Result (R) bus (which interconnects the computational units)

MEMORY

INSTRUCTION

GENERATOR GENERATOR
SEQUENCER

PMA

DMA
DMA BUS

PMD

EXCHANGE
DMD

DMD BUS

INPUT REGS INPUT REGS INPUT REGS

ALU MAC SHIFTER

OUTPUT REGS
Figure 1.1 ADSP-2100 Internal Architecture
OUTPUT REGS OUTPUT REGS
 On the ADSP-2100, the four memory buses are extended off-chip for directconnection to
external memories. The program memory data (PMD) bus serves primarily to transfer instructions
from off-chip memory to the internal instruction register. Instructions are fetched and loaded into
the instruction register duringone processor cycle; they execute during the following cycle while the
next instruction is being fetched. The instruction register introduces a single level of pipelining in the
program flow. Instructions loaded into theinstruction register are also written into the cache
memory, to be described below

The next instruction address i s generated by the program sequencer depending on the
current instruction and internal processor status. This address is placed on the program memory
address (PMA) bus. The program sequencer uses features such as conditional branching, loop
counters and zero-overhead looping to minimize program flow overhead.The program memory
address (PMA) bus is 14 bits wide, allowing direct access to up to 16K words of instruction code
and 16K words of data. Thestate of the PMDA pin distinguishes between code and data access of
program memory. The program memory data (PMD) bus, like the processor’s instruction words, is
24 bits wide.
.
The data memory address (DMA) bus is 14 bits wide allowing direct access of up to 16K
words of data. The data memory data (DMD) bus is 16bits wide. The data memory data (DMD) bus
provides a path for the contents of any register in the processor to be transferred to any other
register, or to any external data memory location, in a single cycle. The datamemory address can
come from two sources: an absolute value specified in the instruction code (direct addressing) or
the output of a data address generator (indirect addressing). Only indirect addressing is supported
for data fetches via the program memory bus.

The program memory data (PMD) bus can also be used to transfer data toand from the
computational units through direct paths or via the PMD- DMD bus exchange unit. The PMD-
DMD bus exchange unit permits datato be passed from one bus to the other. It contains
hardware to overcome the 8-bit width discrepancy between the two buses when necessary.

Each computational unit contains a set of dedicated input and output registers.
Computational operations generally take their operands from input registers and load the result
into an output register. The registers actas a stopover point for data between the external
memory and the computational circuitry, effectively introducing one pipeline level on input and
one level on output. The computational units are arranged side by side rather than in cascade. To
avoid excessive pipeline delays when a series of different operations are performed, the internal
result (R) bus allows any of the output registers to be used directly (without delay) as the input to
another computation.
For a wide variety of calculations, it is desirable to fetch two operands at the same time—
one from data memory and one from program memory. Fetching data from program memory,
however, makes it impossible to fetch the next instruction from program memory on the same
cycle; an additional cycle would be required. To avoid this overhead, the ADSP- 2100 incorporates
an instruction cache which holds sixteen words. The benefit of the cache architecture is most
apparent when executing a program loop that can be totally contained in the cache memory. In
this situation, the ADSP-2100 works like a three-bus system with an instruction fetch and two
operand fetches taking place at the same time. Many algorithms are readily coded in loops of
sixteen instructions or lessbecause of the parallelism and high-level syntax of the ADSP-2100
assembly language.
Here’s how the cache functions: Every instruction loaded into the instruction register is
also written into cache memory. As additional instructions are fetched, they overwrite the current
contents of cache in acircular fashion. When the current instruction does a program memory data
access, the cache automatically sources the instruction register if its contents are valid. Operation
of the cache is completely transparent to user.
There are two independent data address generators (DAGs). As a pair, they allow the
simultaneous fetch of data stored in program and in data memory for executing dual-operand
instructions in a single cycle. One data address generator (DAG1) can supply addresses to the data
memoryonly; the other (DAG2) can supply addresses to either the data memory orthe program
memory. Each DAG can handle linear addressing as well as modulo addressing for circular buffers.
With its multiple bus structure, the ADSP-2100 supports a high degree of operational
parallelism. In a single cycle, the ADSP-2100 can fetch an instruction, compute the next instruction
address, perform one or two data transfers, update one or two data address pointers and perform
a computation. Every instruction executes in a single cycle.
 Figure 1.2, on the next page, is a simplified representation of the ADSP-2100 in a system
context. The figure shows the two external memories used by the processor. Program memory
stores instructions and is also used to store data. Data memory stores only data. The data memory
address space may be shared with memory-mapped peripherals, if desired. Both memories may
be accessed by external devices, such as a system host, if desired. Figure 1.2 also shows the
processor control interface signals, (RESET, HALT and TRAP) the four interrupt request lines, the bus
request and bus grant lines (BR and BG) and the clock input(CLKIN) and output (CLKOUT).

CLOCK

CLKIN CLKOUT
ADDR
MEMORY
ADSP-2100

Program Memory DATA

PROGRAM

Program Memory

ADDR
BG
RESETHALT TRAPIRQ

DATA

Figure 1.2 ADSP-2100 System

ADSP-2181 high performance Processor:

The ADSP-2181 is a single-chip microcomputer optimized fordigital signal processing ( DSP) and
other high speed numeric processing applications.
The ADSP-2181 combines the ADSP-2100 family base archi- tecture (three computational units,
data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, Flag I/O,extensive interrupt capabilities, and on-
chip program and data memory.
The ADSP-2181 integrates 80K bytes of on-chip memory con- figured as 16K words (24-bit) of
program RAM, and 16K words(16-bit) of data RAM. Power-down circuitry is also provided to meet
the low power needs of battery operated portable equip- ment. The ADSP-2181 is available in
128- lead TQFP and 128- lead PQFP packages.
In addition, the ADSP-2181 supports new instructions, which include bit manipulations—bit set,
bit clear, bit toggle, bit test—new ALU constants, new multiplication instruction (x squared), biased
rounding, result free ALU operations, I/O memory trans- fers and global interrupt masking for
increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2181 operates
with a 25 ns instruction cycletime. Every instruction can execute in a single processor cycle.
The ADSP-2181’s flexible architecture and comprehensive instruction set allow the processor to
perform multiple opera-tions in parallel. In one processor cycle the ADSP-2181 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
 • Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer

21xx CORE ADSP-2181 INTEGRATION

POWER- DOWN CONTROL LOGIC
2

INSTRUCTION REGISTER

PROGRAM SRAM 16K × 24 SRAM 16K × 16

DATA PROGRAMMABLE 8
I/O
DATA ADDRESS GENERATOR
DATA ADDRESS
#1 GENERATOR #2 BYTE DMA
PROGRAM SEQUENCER 3
CONTROLLER FLAGS

PMA BUS 14 PMA BUS

14

DMA BUS DMA BUS MUX

14
EXTERNAL ADDRESS BUS

PMD BUS 24 PMD BUS

EXTERNAL DATA BUS
INPUT INPUT
REGS REGS
BUS EXCHANGE
MUX
DMD BUS
ALU MAC
DMD BUS 24

16

INPUT REGS INPUT REGS INPUT REGS COMPANDING CIRCUITRY

16

TIMER INTERNAL DMA PORT

ALU MAC SHIFTER
OUTPUT REGS OUTPUT REGS OUTPUT REGS TRANSMIT REG TRANSMIT REG

Figure 1. ADSP-2181 RECEIVE REG RECEIVE REG

SERIAL 4
16 Block Diagram SERIAL
PORT 0 PORT 0
INTERRUPTS

R BUS
5 5
The ADSP-2181 instruction set provides flexible data moves and multifunction (one
or two data moves with a computation)instructions. Every instruction can be executed
in a single processor cycle. The ADSP-2181 assembly language uses an algebraic syntax
for ease of coding and readability. A comprehensive set of development tools
supports program development.
Figure 1 is an overall block diagram of the ADSP-2181. The processor
contains three independent computational units: the ALU, the multiplier/accumulator
( MAC) and the shifter. The computational units process 16-bit data directly and have
provi-sions to support multiprecision computations. The ALU per- forms a standard
set of arithmetic and logic operations; division primitives are also supported. The MAC
performs single-cycle multiply, multiply/add and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arithmetic shifts, normalization,
denormalization and derive exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and block floating- point
representations.
The internal result (R) bus connects the computational units sothat the output of
any unit may be the input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address generators ensure
efficient delivery of operands to these computational units. The sequencer supports
conditional jumps, subroutinecalls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2181 executes looped code with zero over- head;
no explicit jump instructions are required to maintain loops.
Two data address generators ( DAGs) provide addresses for simultaneous dual
operand fetches (from data memory and program memory). Each DAG maintains and
updates four address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of four possible modify
registers. A length value may be associatedwith each pointer to implement
automatic modulo addressing for circular buffers.
Efficient data transfer is achieved with the use of five internalbuses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address ( DMA) Bus
• Data Memory Data ( DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external address bus, allowing
memory to be expanded off-chip, and the two data buses (PMD and DMD) share a
single external data
bus. Byte memory space and I/O memory space also share the external buses.
Program memory can store both instructions and data, permit- ting the ADSP-2181
to fetch two operands in a single cycle, one from program memory and one from
data memory. The ADSP-2181 can fetch an operand from program memory and the
next instruction in the same cycle. In addition to the address and data bus for external
memory connection, the ADSP-2181 has a 16-bit Internal DMA port (IDMA port) for
connection to external systems. The IDMA port is made up of 16 data/address pins
and five control pins. The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM. An interface to low cost byte-wide memory is
provided by the Byte DMA port (BDMA port). The BDMA port is bidirectionaland can
directly address up to four megabytes of external RAMor ROM for off-chip storage
of program overlays or data tables. The byte memory and I/O memory space interface
supports slow memories and I/O memory-mapped peripherals with program- mable
wait state generation. External devices can gain control of external buses with bus
request/grant signals ( BǍ, BŠǏ and BŠ).One execution mode (Go Mode) allows the
ADSP-2181 to con- tinue running from on-chip memory. Normal execution mode
requires the processor to halt while buses are granted. The ADSP-2181 can respond
to 13 possible interrupts, eleven of which are accessible at any given time. There
can be up to sixexternal interrupts (one edge-sensitive, two level-sensitive and three
configurable) and seven internal interrupts generated bythe timer, the serial ports
(SPORTs), the Byte DMA port and the power-down circuitry. There is also a master
ǍESET signal. The two serial ports provide a complete synchronous serial inter- face
with optional companding in hardware and a wide variety of framed or frameless data
transmit and receive modes of operation. Each port can generate an internal
programmable serial clock or accept an external serial clock.
The ADSP-2181 provides up to 13 general-purpose flag pins. The data input and output
pins on SPORT 1 can be alternatively configured as an input flag and an output flag. In
addition, there are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A 16-bit count register ( T
COUN T) is decremented every n pro- cessor cycles, where n is a scaling value stored in an 8-
bit regis- ter ( TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded from a 16-bit period
register ( TPERIOD).
Serial Ports
The ADSP-2181 incorporates two complete synchronous serial ports (SPORT 0 and SPORT
1) for serial communications and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2181 SPORTs. Refer to the ADSP-2100
Family User’s Manual, Third Edition for further details.
• SPORTs are bidirectional and have a separate, double-buffered transmit and
receive section.
• SPORTs can use an external serial clock or generate their own serial clock
internally.
• SPORTs have independent framing for the receive and trans- mit sections. Sections run
in a frameless mode or with frame synchronization signals internally or externally
generated.
Frame sync signals are active high or inverted, with either of two pulse widths and
timings.
• SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law
and -law companding accordingto CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique interrupts on completing a
data word transfer.
• SPORTs can receive and transmit an entire circular buffer ofdata with only one overhead
cycle per data word. An interruptis generated after a data buffer transfer.
• SPORT 0 has a multichannel interface to selectively receive and transmit a 24- or 32-word,
time-division multiplexed, serial bitstream.
• SPORT 1 can be configured to have two external interrupts (IǍQ0 and IǍQ1) and the Flag
In and Flag Out signals. The internally generated serial clock may still be used in this
configuration.