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Approximate Computing Survey, Part II: Application-Specific

& Architectural Approximation Techniques and Applications
VASILEIOS LEON, National Technical University of Athens, Greece
MUHAMMAD ABDULLAH HANIF, New York University Abu Dhabi, UAE
arXiv:2307.11128v1 [cs.AR] 20 Jul 2023

GIORGOS ARMENIAKOS, National Technical University of Athens, Greece

XUN JIAO, Villanova University, USA
MUHAMMAD SHAFIQUE, New York University Abu Dhabi, UAE
KIAMAL PEKMESTZI, National Technical University of Athens, Greece
DIMITRIOS SOUDRIS, National Technical University of Athens, Greece
The challenging deployment of compute-intensive applications from domains such Artificial Intelligence
(AI) and Digital Signal Processing (DSP), forces the community of computing systems to explore new design
approaches. Approximate Computing appears as an emerging solution, allowing to tune the quality of results
in the design of a system in order to improve the energy efficiency and/or performance. This radical paradigm
shift has attracted interest from both academia and industry, resulting in significant research on approximation
techniques and methodologies at different design layers (from system down to integrated circuits). Motivated
by the wide appeal of Approximate Computing over the last 10 years, we conduct a two-part survey to cover
key aspects (e.g., terminology and applications) and review the state-of-the art approximation techniques from
all layers of the traditional computing stack. In Part II of our survey, we classify and present the technical
details of application-specific and architectural approximation techniques, which both target the design
of resource-efficient processors/accelerators & systems. Moreover, we present a detailed analysis of the
application spectrum of Approximate Computing and discuss open challenges and future directions.

CCS Concepts: • General and reference → Surveys and overviews; • Software and its engineering →
Software notations and tools; • Hardware → Integrated circuits; • Computer systems organization
→ Architectures.

Additional Key Words and Phrases: Inexact Computing, Approximation Method, Approximate Programming,
Approximation Framework, Approximate Processor, Approximate Memory, Approximate Circuit, Approximate
Arithmetic, Error Resilience, Accuracy, Review, Classification

ACM Reference Format:

Vasileios Leon, Muhammad Abdullah Hanif, Giorgos Armeniakos, Xun Jiao, Muhammad Shafique, Kiamal
Pekmestzi, and Dimitrios Soudris. 2023. Approximate Computing Survey, Part II: Application-Specific &
Architectural Approximation Techniques and Applications. ACM Computing Surveys.

Authors’ addresses: Vasileios Leon, National Technical University of Athens, Athens 15780, Greece; Muhammad Abdullah
Hanif, New York University Abu Dhabi, Abu Dhabi 129188, UAE; Giorgos Armeniakos, National Technical University of
Athens, Athens 15780, Greece; Xun Jiao, Villanova University, Villanova, Pennsylvania 19085, USA; Muhammad Shafique,
New York University Abu Dhabi, Abu Dhabi 129188, UAE; Kiamal Pekmestzi, National Technical University of Athens,
Athens 15780, Greece; Dimitrios Soudris, National Technical University of Athens, Athens 15780, Greece.

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2 Vasileios Leon et al.

1 INTRODUCTION
The recent technological advancements in processing, storage, communication and sensing have
transformed the landscape of computing systems. With the emergence of Internet of Things (IoT),
a huge amount of data is generated, imposing technical challenges in the resource-constrained
embedded systems that are placed at the edge of the network. The ever-growing number of global
IoT connections, which grew by 18% in 2022 and is expected to be 29.7 billion in 2027 [91], is only
deteriorating this situation. At the same time, the already-stressed cloud data centers are drawing
worldwide concerns due to their enormous electricity demands. Indicatively, it is estimated that
the energy consumption of data centers in Europe was increased by 43% from 2010 to 2020 [22],
while according to [30], data centers may generate up to 8% of the global carbon emissions in 2030.
The above issues become even more critical when considering the massive growth of demanding
applications from domains such as Digital Signal Processing (DSP), Artificial Intelligence (AI), and
Machine Learning (ML). More specifically, the emergence of compute- and memory-intensive DSP
and AI/ML applications marks a new era for computing, where traditional design approaches and
conventional processors are unable to meet the performance requirements [64, 166]. Therefore, it is
obvious that the proliferation of data and workloads, the increase in the complexity of applications,
and the urgent need for power efficiency and fast processing, all together, force the industry of
computing systems to examine alternative design solutions and computing schemes.
In this transition, Approximate Computing (AxC) is already considered a novel design par-
adigm that improves the energy efficiency and performance of computing systems [260]. Over
the past decade, AxC has been established as a vigorous approach to leverage the inherent ability
of numerous applications to produce results of acceptable quality, despite some inaccuracies in
computations [16]. The motivation behind AxC is further analyzed in our work in [129]. Driven
by its potential to address the energy and performance demands in a favorable manner, AxC is
increasingly gaining significant attention over the last years. A representative example of this trend
is depicted in Figure 1. This figure illustrates the growing number of works that apply any kind of
approximation (e.g., software, hardware, architectural), published in four major design automation
conferences. Furthermore, AxC has attracted significant interest from the industry. Companies
such as Google [101], IBM [5], and Samsung [188] exploit the AI/ML error resilience and design
accelerators for compressed networks with reduced precision and less computations, improving
the energy efficiency and performance in exchange for negligible or zero accuracy loss.
Considering the need to go beyond single optimizations or efficient processor design, which
solely do not suffice [49], prior research has focused on approximation techniques at different design
abstraction layers [260], involving algorithmic- or compiler-level approximations (software) [9, 10],
circuit-level approximations (hardware) [36, 96] and systematic design of approximate processors
(architectural) [47, 55]. Despite their share objective of achieving energy/area gains and latency
reduction, these fundamental techniques are orthogonal and can complement each other. As com-
bining AxC techniques is expected to be highly beneficial (several works report energy gains over
90% [49]), a further adoption and understanding of cross-layer development (i.e., hardware/software
co-design), including tools & frameworks tailored to specific applications, are highly required to
maximize these benefits. In this context, motivated by the attractive outcomes, novel methods, and
future potential of AxC, we conduct a two-part survey that covers all its key aspects.

2 APPROXIMATE COMPUTING SURVEY

Scope and Contribution: As also discussed in Part I [129] of our survey, we examine the entire
AxC computing stack, reviewing software, hardware, and architectural approximation techniques,
contrary to other AxC surveys that focus on a single area (either design layer, technique or

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 3

DATE DAC ICCAD MICRO

60

Number of Papers
40
20
0
2015/16 2017/18 2019/20 2021/22

Fig. 1. Number of publications that apply any type of approximation. Four design automation conferences
over the past eight years have been considered.

Table 1. Qualitative comparison of Approximate Computing surveys on the entire computing stack.
e

pprox.
overag

gy
ces #

& Tools ks

arks

GP U/A GA/

ges
SIC

olo
or
ch.

ies
ey

h.

Benchm
Framew

P
rv

n
Arch. A

Termin
SW Tec
Pages #

Memor
HW Te

CP U/F
Refere

Challe
Metric
Su

Year C

AI/ML
xC
A

[73] 2013 6 65 ✓ ✓ ≈ ≈ ✗ ✗ ✓ ✗ ≈ ✗ ✗
[165] 2015 331 84 ✓ ≈ ✓ ≈ ✓ ✓ ✓ ✓ ✓ ✗ ✓
[276] 2015 15 59 ✓ ✓ ✓ ✗ ≈ ✗ ✗ ✗ ≈ ✗ ✗
[262] 2015 6 54 ✓ ✓ ✓ ✗ ✗ ✓ ✗ ✗ ≈ ✗ ✗
[227] 2016 6 47 ✓ ✓ ✓ ✗ ✗ ≈ ✗ ✗ ≈ ✗ ✗
[169] 2017 4 40 ✓ ✓ ✗ ≈ ≈ ✗ ✗ ✗ ≈ ✗ ✗
[15] 2017 6 72 ✓ ✓ ✓ ≈ ≈ ≈ ✗ ✓ ≈ ✗ ✓
[238] 2020 391 235 ≈ ✓ ✓ ✗ ✓ ≈ ✗ ✗ ≈ ✗ ✓
Pt. 1 2023 341 221 ✓ ✓ ✓ ✓ ✓
Our work
Pt. 2 2023 351 296 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
1 Single-column pages

application). Table 1 compares surveys studying multiple areas of AxC, like our work. As shown,
our two-part survey includes all the areas examined in the previous works, while it reviews all of
them in depth (e.g., AI/ML has not received significant attention) and it is up-to-date.
Regarding the contribution of our survey, it provides to the readers a complete view on AxC,
while it allows them to emphasize on specific areas (e.g., architectural techniques or application
domains), as they are all presented in detail. Furthermore, this survey can be considered as a tutorial
on the state-of-the-art approximation techniques, as we do not only classify them, but we report
in brief their technical details. Overall, the key contributions of our two-part survey are: 1) the
introduction of the AxC paradigm by discussing its background and application domains, 2) the
review of a plethora of state-of-the-art approximation techniques, their coarse- and fine-grained
classification, and the presentation of their technical details, 3) the study of application domains
where approximations are tolerated and the analysis of representative techniques and results per
domain, and 4) the discussion of open challenges in the design of approximate systems, as they
emerge from the comprehensive literature review.
Organization: Figure 2 presents the content of each part of our survey:

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4 Vasileios Leon et al.

Selective Task Skipping

Approximate Memoization
Relaxed Synchronization Circuit Functional Approximation

Precision Scaling Voltage Over-Scaling

Data Sampling AxC Over-Clocking

Approximate Progr. Languages

Paradigm Motivation

Terminology Principles
Part I

Part II Challenges
Future Directions
Software Approximations
Hardware Approximations Approximate Processors
Cross-Layer Approximations Approximate Data Storage
End-to-End Approximations AxC
Applications
Application Spectrum Application-Driven Analysis
Benchmark Suites Error/Quality Metrics

Fig. 2. Organization of our two-part survey on Approximate Computing.

Part I: It is presented in [129], and it introduces the AxC paradigm (terminology and principles)
and reviews software & hardware approximation techniques.
Part II: It is presented in the current paper, and it reviews application-specific & architectural
approximation techniques and introduces the AxC applications (domains, quality metrics,
benchmarks).
The remainder of the article (Part II of survey) is organized as follows. Section 3 reports software-,
hardware- and cross-layer application-specific approximation techniques. Section 4 focuses on
the architecture level and classifies approximate processors and storage. Section 5 studies the
applications of AxC, while Section 6 discusses challenges and future directions. Finally, Section 7
draws the conclusions.

3 APPLICATION-SPECIFIC APPROXIMATION TECHNIQUES

In this section, we classify and introduce application-specific approximation techniques. We mainly
discuss techniques that are proposed for improving the performance and efficiency of Deep Learning
(DL) and AI applications. The techniques presented in the literature can be broadly categorized into
software-level, hardware-level and cross-layer approximation techniques (see Figure 3 and Table 2).

3.1 Software-Level Approximations

Various types of software-level approximation techniques have been proposed in the literature
to reduce the computational complexity and memory footprint of AI and DL workloads. These
techniques can broadly be divided into four groups: (i) computation skipping / pruning [42, 75, 76, 84,
85, 88, 125, 136, 241, 244, 267, 273, 283–285], (ii) precision scaling [75, 89, 94, 206, 269, 295], (iii) input-
adaptive approximation [63, 120, 148, 181, 183, 192, 246, 261, 263], and (iv) input scaling [65, 245].

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 5

APPLICATION-SPECIFIC
APPROXIMATION TECHNIQUES

Software-Level Hardware-Level Cross-Layer & End-to-End

Approximations Approximations Approximations

Fig. 3. Classification of application-specific approximation techniques for DL and AI applications in three

main classes: Software-Level, Hardware-Level, and Cross-Layer & End-to-End.

Table 2. Classification of application-specific approximation techniques.

Application-Specific
Technique/Approach
Approximation Class
Computation Skipping / Pruning [42, 75, 76, 84, 85, 88, 125, 136, 241, 244, 267, 273, 283–285]
Software-Level Precision Scaling [75, 89, 94, 206, 269, 295]
Approximation Input-Adaptive Approximation [63, 148, 181, 183, 192, 246, 261, 263]
Input Scaling [65, 245]
Functional Approximation & Approx. Datapaths [77, 110, 128, 130, 172–174, 213, 233, 236, 264]
Hardware-Level Approximation-based Novel Data Representation Formats [69, 78, 93, 94]
Approximation Voltage Scaling [95, 111, 115, 184, 231, 292]
Data Approximation [111, 115]
Cross-Layer & Approximation at Various Layers of Computing Stack [18, 19, 57, 65, 68, 79, 82, 198, 199, 260]
End-to-End Full-System Perspective [65, 82, 198, 199]
Approximation Approximation of Multiple Subsystems in a Synergistic Manner [65, 82, 198, 199]

3.1.1 Pruning. Computation skipping is one of the most effective software-level techniques for
approximating DNNs. Various techniques have been proposed under the umbrella of DNN pruning
that exploits computation skipping for optimizing the DNN inference process. In general, DNN
pruning refers to the process of removing non-essential (or less important) weights from a DNN to
reduce its computational complexity, memory footprint as well as energy consumption during the
inference process. These techniques are generally divided into two main categories: (1) unstructured
pruning and (2) structured pruning.
Unstructured pruning (a.k.a. fine-grained pruning) refers to techniques that analyze the impor-
tance/saliency of each individual weight and remove it if its importance is below a predefined
threshold. These techniques are usually designed to be iterative, where in each iteration only a
small percentage of less significant weights are removed and then the network is retrained for a few
epochs to regain close to the baseline accuracy. For example, Han et al. [76] propose a three-step
method to prune DNNs. First, they train a DNN to learn the importance of connections. Then,
they remove non-essential (less important) connections from the DNN. Finally, they fine-tune
the remaining weights to regain the lost accuracy. The authors further propose that learning the
right connections is an iterative process. Therefore, the process of pruning followed by fine tuning
should be repeated multiple times (with a small pruning ratio) to achieve higher compression ratios.
Deep Compression [75] combines a similar method with weight sharing and Huffman coding to
achieve ultra-high compression ratios.
Although unstructured pruning significantly reduces the number of parameters and the memory
footprint of DNNs, it does not guarantee energy or latency benefits in all cases. This is mainly

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6 Vasileios Leon et al.

because; (1) the weights of a pruned network are usually stored in a compressed format, such as the
Compressed Sparse Row (CSR) format, to achieve high compression ratios and, therefore, have to
be uncompressed before corresponding computations, which results in significant overheads, and
(2) the underlying hardware (in most use cases) is not designed to take advantage of unstructured
sparsity in DNNs, which results in under utilization of the hardware. Therefore, specialized hardware
accelerators, such as EIE [74] and SCNN [185], are required to efficiently process data using
unstructured sparse DNNs. Similarly, Yu et al. [283] highlight that it is essential to align the
pruning method to the underlying hardware architecture to achieve efficiency gains. A mismatch
between the type of sparsity in the network and the sparsity the hardware can support efficiently
usually leads to significant overheads. Based on this observation, the authors propose two novel
pruning methods, i.e., SIMD-aware weight pruning and node pruning. SIMD-aware weight pruning
maintains weights in aligned fixed-size groups to fully utilize the available SIMD units in the
underlying hardware, while node pruning removes less significant nodes from the network without
affecting the dense format of weight matrices.
Various other techniques have also been proposed in the literature to achieve structured sparsity
in DNNs. These methods generally include weight-dependent pruning techniques [136, 284, 285],
activation-based techniques [84, 85, 88, 241, 244], and regularization-based techniques [42, 125,
267, 273]. The weight-dependent techniques evaluate the importance of filters solely based on the
weights of the filters, while activation-based techniques use activation maps to identify critical
filters in the network. Similarly, regularization-based techniques encourage sparsity during training
by adding regularization terms in the loss function or by exploiting batch normalization parameters.

3.1.2 Precision Scaling. It refers to the techniques of mapping values from a high-precision range
to a lower-precision range with lesser number of quantization levels. The number of quantization
levels in a range defines the number of bits required to represent each data value. Hence, by
using a lower-precision format, such as 4-bit or 8-bit fixed-point or floating-point format instead
of the standard 32-bit floating-point format, the memory footprint as well as the computational
requirements of DNNs can be significantly reduced.
Various techniques have been proposed to achieve precision scaling of DNNs without affecting
their application-level accuracy. The most commonly used technique is 8-bit range linear post-
training quantization, where floating-point weights and activations are converted to 8-bit fixed-
point format. The range linear quantization is further divided into two types: (1) asymmetric
quantization [92] and (2) symmetric quantization [116]. In asymmetric quantization, the minimum
and maximum observed values in the input range are mapped to the minimum and maximum
values in the output (integer/fixed-point) range, respectively. However, in symmetric quantization,
the maximum absolute observed value in the input range is used to define both minimum and
maximum values of the input range. Significant efforts have been made to push the limits of
DNN precision scaling to ultra-low precision levels. Works like XNOR-Net [206], Binarized Neural
Network (BNN) [89] and DoReFa-Net [295] explore the potential of aggressive quantization, up
to 1-bit precision. However, as aggressive quantization leads to significant accuracy loss, these
techniques usually employ quantization-aware training to achieve reasonable accuracy, as in such
cases training also acts as an error-healing process.
Non-linear (or non-uniform) quantization techniques have also been explored in the litera-
ture [75, 94]. These techniques are inspired by the non-uniform probability distribution of DNN
data structures and propose to distribute the quantization levels accordingly. Apart from the
above-mentioned techniques, mixed-precision techniques are also commonly used, where different
precision formats can be used for different layers and filters/channels of a DNN [269]. We note

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 7

that mixed-precision quantization is only effective when the underlying hardware is capable of
supporting different precision formats.
3.1.3 Input-Adaptive Approximation. Besides pruning and precision scaling, input-adaptive ap-
proximations are also commonly used to approximate DNN workloads. In general, input-adaptive
approximations refer to the techniques that dynamically adapt the level of approximation based
on the characteristics of the input data. Various methods have been proposed in the literature to
realize input-adaptive approximations. These methods mainly include (1) early-exit classifiers, (2)
dynamic network architectures, and (3) selective attention mechanisms. Works such as [181, 263]
that fall under early-exit classifiers argue that most of the inputs can be classified with very low
effort. Towards this, the authors in [181] propose Conditional Deep Learning (CDL), where the
outputs of convolutional layers are used to estimate the difficulty of input samples (with the
help of linear classifiers) and conditionally activate the deeper layers of the DNN. Similarly, [183]
propose a hierarchical classification framework by exploiting semantic decomposition. Towards
dynamic network architectures, [63] presents an approach that adapts the structure of a DNN based
on the difficulty of the input sample. Along similar lines, [246] presents a method for building
runtime configurable DNNs and a score margin-based mechanism for dynamically adjusting the
DNN capability. Unlike the above techniques that involve network structure or size modification,
selective attention mechanisms focus on reducing computational requirements by processing only
the important/relevant regions of the input while ignoring all less relevant parts. A prominent work
in this direction includes selective tile processing [192], where a low cost attention mechanism is
used to identify the tiles that require processing.
3.1.4 Input Scaling. Given that neighboring pixels in images are not always statistically indepen-
dent and contain a significant amount of redundant information, input scaling can be exploited to
reduce the computational requirements of DNN inference. Towards this, Tan et al. in [245] propose
a compound scaling method that uniformly scales network width, depth, and input resolution to
design a complete class of EfficientNets. Moreover, techniques like AxIS [65] employ input scaling
as an approximation knob in their cross-layer approximations to achieve ultra-high efficiency gains.

3.2 Hardware-Level Approximations

Venkataramani et al. in [264] highlight that DNNs are mostly used for error-resilient applications,
and hence, hardware approximations can be used to effectively trade quality for efficiency of
the DNN inference process. Towards this, they propose a method to transform a given Neural
Network (NN) to an Approximate Neural Network (AxNN) [264]. The method mainly employs
backpropagation to estimate the importance of each neuron and then selectively approximates
less significant neurons through precision scaling of weights and activations to achieve better
energy-accuracy trade-offs. The method also employs approximation-aware retraining to regain a
significant portion of the accuracy lost due to approximations.
As a single DNN inference can take from some million to billions of MAC operations, the use
of approximate MAC units in DNN accelerators (instead of accurate ones) can have a significant
impact on the overall energy consumption of DNN inference systems. In general, approximate
MAC units refer to the simplified variants of the accurate counterparts that offer approximately the
same functionality but at a lower energy or performance cost. Various significant efforts have been
made toward designing approximate MAC units. Most of these works focus on approximating the
multiplication part in the MAC operations, as multipliers are in general more complex and resource
hungry than adders. Marazek et al. in [172] employ the Cartesian Genetic Programming (CGP)
approach to approximate accurate multiplier designs. The methodology employs approximation-
aware retraining of the given NN in the methodology to reach the best possible approximate

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8 Vasileios Leon et al.

multiplier design for the given application. However, approximation-aware retraining is not possi-
ble in all scenarios, e.g., due to limited computational resources or due to the lack of availability
of training data. Therefore, to address this limitation, ALWANN [174] proposes a layer-wise ap-
proximation technique to select an appropriate approximate multiplier from a given library (e.g.,
EvoApprox [171]) for each individual layer of the given DNN without involving any training. The
authors also present a computationally inexpensive method to fine-tune the DNN weights after
the approximate module selection process to reduce the accuracy loss due to approximations. In
the same context, the Max-DNN framework [130] relies on ALWANN’s functionalities to provide
fine-grained approximation of the multiplications at different DNN layers. In [173], the authors
present a methodology to generate libraries of more specific approximate circuits and show that
such techniques can produce better results than techniques like ALWANN [174]. Other promi-
nent approximate multiplier designs for DNN acceleration include Digital Approximate In-SRAM
Multiplier (DAISM) [233], positive/negative approximate multipliers [236] and approximate log-
multipliers [110, 213]. Moreover, towards mitigating the impact of approximation errors, CANN [77]
presents the concept of curable approximations for DNN accelerators, where approximation errors
can be internally compensated with some additional functionality. To facilitate the design and
exploration of approximate modules for efficient DNN inference, fast simulation techniques and
frameworks are also being developed and studied [52, 67, 242]. Finally, the use of approximate
multipliers provides resource saving and increased throughput in FPGA-based DNN accelerators
[128], while the same benefits are also delivered in classic DSP kernels [132].
Another set of techniques that include works such as BiScaled-DNNs [94], CoNLoCNN [78],
Compensated-DNNs [93] and ANT [69] targets novel data representation formats to significantly
reduce the hardware complexity and energy requirements of DNN inference systems. BiScaled-
DNNs [94] argues that DNN data structures are long-tailed and, therefore, can effectively be
quantized using two different scale factors (namely, scale-fine and scale-wide). Scale-fine enables
the system to precisely capture small numbers using more fractional bits, while scale-wide allows
the system to cover the entire range of large numbers but at a coarser granularity. CoNLoCNN [78]
employs a modified version of power-of-two quantization to replace multiplication with shift
operations. Compensated-DNNs [93] propose the concept of dynamic compensation to mitigate
the impact of quantization errors caused due to aggressive quantization. On the other hand,
ANT [69] argues that most of the existing quantization techniques use fixed-point or floating-point
data representation formats, which offer limited benefits, as both are effective for specific data
distributions, and thus, require reasonably large number of bits to maintain the DNN accuracy.
Therefore, [69] proposes a novel adaptive numerical data type that combines the benefits of float
and integer data formats and, thereby, it allows the system to adapt based on the importance of
each value in a tensor.
Apart from functional approximation of arithmetic modules in DNN accelerators, voltage-scaling
can also be employed to improve the energy efficiency of DNNs. ThunderVolt [292] presents
TE-Drop, a timing error recovery technique for DNN accelerators. It employs Razor flip-flops to
detect timing errors in the MAC units and then avoids re-execution penalty by dropping the MAC
operation subsequent to the erroneous MAC. [231] presents a similar approach but employs Razor
flip-flops in between the multiplier and the adder of each MAC unit. As dropping MAC operations
can result in significant performance degradation, the authors in [95] present a Compensation MAC
(CMAC) unit that compensates for the dropped multiplication using an additional adder in the
MAC subsequent to the erroneous MAC. Along similar lines, GreenTPU [184] presents a Timing
Error Control Unit (TECU) to keep track of the timing error causing input patterns and boost the
operating voltage of the subsequent MACs in the processing array. Apart from exploiting voltage
scaling for improving energy efficiency of computational units, works such as MATIC [111] explore

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 9

the potential of aggressive voltage scaling of on-chip weight memories to improve the energy
efficiency of DNN accelerators. Similarly, EDEN [115] presents a framework for using approximate
DRAM with reduced voltage and reduced latency to improve the energy and performance efficiency
of DNN inference systems. These techniques mainly employ memory adaptive training to achieve
ultra-high efficiency gains and without any significant loss in the DNN accuracy.

3.3 Cross-Layer and End-to-End Approximations

The adoption of approximations in real-world systems has been mostly limited to either the software
or hardware level and to only one subsystem (usually the computational one). To uncover the true
potential of Approximate Computing, a full-system approach is essential where approximations
are applied at multiple abstraction levels and to multiple subsystems (e.g., the memory, sensor,
and communication subsystems) together with the computational subsystem. Various studies
have shown the potential of systematic joint approximation of subsystems to achieve ultra-high
efficiency gains. Earlier works highlight the potential of combining software- and hardware-level
approximations. For example, in [182], the authors highlight different algorithmic and circuit-level
approximation techniques for significantly reducing the energy consumption of DNN inference
systems. For algorithmic approximations, they mainly discuss scalable effort computing tech-
niques [181, 263], in which less complex inputs are processed using smaller networks, and more
complex inputs are passed through a larger number of processing layers to generate an accurate
output. For circuit/hardware-level approximations, they mainly highlight voltage scaling of on-chip
SRAM and functional approximation of multipliers to reduce the energy consumption of DNNs.
In [198], Raha et al. present a full-system perspective for approximating smart camera sys-
tems designed for computer vision and image processing applications. They present a systematic
methodology for judiciously approximating sensor, memory, and computation subsystems. For
sensor approximation, they consider pixel subsampling (or downscaling image resolution), as
it not only reduces the energy consumption of the sensor but also reduces the entire system’s
energy consumption by reducing the input size (or data) and the number of computations required
for processing the input. For approximating memory, they focus on increasing the refresh inter-
val of DRAM, as sub-optimal refresh intervals result in a significant reduction in refresh energy
consumption while still offering space to store critical data in non-erroneous DRAM pages. For
computation approximation, they consider loop perforation and early loop termination techniques.
To systematically tune all the subsystem approximation knobs, they first find the optimal image
resolution for the given quality constraint and then using gradient descent over the individual
quality vs. energy curves find the optimal operating points for DRAM and computation skipping.
In [199], the methodology is extended to cover the communication subsystem as well. The work
shows that for compute-intensive systems the methodology offers 3.5×–5.5× energy benefits, while
for communication-intensive systems, e.g., where the input is sent to a server for processing,
the methodology offers 1.8×–3.7× energy benefits at the cost of less than 1% application-level
quality loss. In [65], Ghosh et al. design a similar methodology for DNN-based inference system
and demonstrate that their methodology can lead to 1.6×–1.7× energy benefits for the on-device
inference scenario and 1.4×–3.4× energy benefits for the on-cloud inference scenario at the cost of
less than 1% accuracy loss.
A similar end-to-end approach is presented in [82] for approximating an iris scanning system. The
authors employ approximations both at the software and hardware levels to build an accurate system
using approximate pipeline. They identify eight different approximation knobs and then employ
a reinforcement learning-based methodology for design space exploration on the approximate
pipeline to achieve optimal trade-off between accuracy and runtime/energy consumption. Their
method can lead to 48× improvement in runtime while maintaining 100% accuracy.

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10 Vasileios Leon et al.

Apart from the above methods, various other techniques have also been proposed that combine
DNN compression/approximation algorithms with hardware-level approximations to achieve
significant efficiency gains. Gong et al. [68] present a framework that combines dynamic layered
CNN structure, kernel shrinking and layer-by-layer quantization at the algorithm level and uses
an approximate computing-based reconfigurable architecture at the hardware level. Similarly,
[79] presents a cross-layer framework that combines network pruning and quantization with
hardware-level functional approximations of arithmetic units. Along similar lines, [57] integrates
activation pruning and voltage scaling with hardware-level functional approximation. To overcome
the accuracy loss incurred due to hardware approximations, the authors propose to incorporate
approximations in the training process, which results in an increase of about 5.32% in accuracy.
The authors report around 52.5% improvement in the energy efficiency of the system on average.
As the spectrum of AI-based products and services is expanding at a rapid pace, there is an in-
creased demand for computing systems that can efficiently handle various types of DNN workloads.
Towards this, [260] presents an AI system design, RaPID, that integrates different approximation
techniques developed at different layers of the computing stack. At the algorithm level, it employs
precision scaling and gradient compression to reduce the compute, memory, and data-transfer costs.
At the hardware level, it employs a reconfigurable approximate AI core that supports different levels
of approximations. Finally, it incorporates an approximation-aware compiler to map approximate
algorithms on approximate hardware. The system is designed to support various types of DNNs
and both DNN inference and training workloads.
Of particular relevance, the need for further hardware efficiency across multiple abstraction
levels also exists in resource-limited scenarios, suited to low-power ML, such as flexible and printed
applications [17, 175]. Printed classifiers are significantly less costly than conventional CMOS
technologies, paving the way for high circuit customizations, also known as Bespoke implementa-
tions [43]. Recent examples introduced Approximate Computing in printed ML classifiers tailored
to Bespoke architectures [18, 19]. [19] proposes an automated framework that applies a model-
to-circuit cross approximation and generates close-to-accuracy-optimal approximate ML circuits,
allowing the deployment of complex classifiers on battery-powered devices (< 30mW). On the other
hand, through a hardware-friendly retraining (at algorithmic level), [18] replaces coefficients with
more area-efficient ones, while an approximate neuron (at hardware-level) boosts the area/power
efficiency by discarding the least significant information among the least significant summands.

4 ARCHITECTURAL APPROXIMATION TECHNIQUES

Architectures that offer the flexibility to willingly trade-off among resource usage, storage and
correctness in processor designs have the potential to achieve both higher performance and
improved energy efficiency compared to error-free baselines. This section elaborates how these
gains can be accomplished through the adoption of approximate processors and approximate data
storage, where certain computational and/or storage tasks can be loaded to specialized/approximate
computing units, resulting in faster processing at the expense of reduced accuracy [11, 55, 151, 170,
280]. Such approximations are typically implemented at a higher level of abstraction and involve
reorganizing the system’s functional blocks or optimizing the use of memory, rather than making
modifications to the system’s physical components (like in hardware approximation techniques).

4.1 Approximate Processors

Early research in the design of approximate processors includes a complete system and toolchain,
proposed in [11]. The design spans from circuits to a compiler, which integrates an area- and energy-
efficient analog neural accelerator tailored to approximate general-purpose code. This solution
includes a compiler workflow that configures both the topology and weights of the neural network,

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 11

while a customized training algorithm reduces errors derived from analog range limitations. In
a similar approach [55], digital Neural Processing Units (NPUs) are tightly integrated with the
processor pipeline, resulting in low-power approximations for specific sections of general-purpose
code. Finally, approximate neural network processing along with high data-level parallelism has
been explored for GPUs [280] and FPGAs [170], as well.
Relax [51] is an architectural framework that comprises three key components - ISA extension,
hardware support and software support. The ISA extension allows the registration of a fault handler
for a code region, enabling software applications to incorporate try/catch behavior. The hardware
support for Relax simplifies hardware design and enhances energy efficiency by relaxing reliability
constraints and providing fault detection mechanisms, while the software support offers a language-
level recovery construct in C/C++, with relax blocks marking regions susceptible to hardware faults.
Similarly, ERSA [47] is a system architecture that targets applications with inherent error resilience,
and ensures high degrees of resilience at low cost. It achieves high error resilience to high-order
bit errors and control flow errors using asymmetric reliability (and the concept of “configurable
reliability” for general-purpose applications) in many-core architectures, error-resilient algorithms,
and intelligent software optimizations.
Prior research studies on the design of approximate processors also include the voltage over-
scaling paradigm as a potential energy-saving method with adjustable approximation level [3]. The
authors in [54] propose an ISA extension provided with approximate operations and storage, as
well as a microarchitecture design, called Truffle, which effectively supports these extensions. This
work utilizes dual-voltage operation to save power and allows the programmers to specify which
parts of a program can be computed approximately at a lower energy cost. Similar manipulations
in operational (timing) errors to decrease power consumption of processor architectures from
voltage/reliability trade-offs, have been studied and can be found in [104, 224].
Among previous architectures, RISC-V has been established as an increasingly growing com-
petitor and alternative of CPUs with funded projects and support from star companies (e.g., Intel,
Microsoft, ST Microelectronics [235]). The availability of open-source RISC-V tools and libraries
provides developers with greater flexibility in designing and optimizing approximate computing sys-
tems. More specifically, the authors in [177] extend prior works in variable bit-width approximate
arithmetic operators with configurable data memory units as well, while [112] leverages the inher-
ent “value similarity” characteristic of ML workloads and by using lightweight micro-architectural
ISA extensions skips entire instruction sequences. Accordingly, it substitutes the results with previ-
ously executed computations, improving both performance and energy efficiency. Furthermore,
[59] utilizes multiple hardware-level approximations and minimizes quality degradation of several
applications by adopting a hardware controller, which adjusts the degree of approximation by
selecting various approximate units. Lastly, RISC-V processors targeting DNN applications have
also been explored in [48, 180]. In [180], the authors exploit the efficacy of SIMD instructions and
propose mixed-precision Quantized Neural Network (QNN) execution that enables functional units
down to 2 bits, opposed to commercial cores (e.g., ARM Cortex M55) that cannot natively support
smaller than 8-bit SIMD instructions. On the other hand, [48] extends the base RISC-V ISA to enable
low bit-width operations tailored to DNN tasks, but this time by adopting a posit processing unit
that can be integrated in a full RISC-V core with minimal overheads.

4.2 Approximate Data Storage

In this survey, we consider the two main types of memories: the non-volatile and the volatile
memories. In our review, the works on approximate non-volatile data storage target Phase-Change
Memories (PCMs) [58, 223, 247], flash memories [141, 217, 250], and Spin Transfer Torque (SST)
RAMs [205, 220, 247, 286]. Regarding the volatile memories, we review static RAMs (SRAMs)

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[34, 61, 118, 208], dynamic RAMs (DRAMs) [102, 142, 208], and caches [135, 156, 157]. We note that
the literature also includes approximation techniques that are applied and evaluated in different
types of memory [203].
4.2.1 Approximate Non-Volatile Memories. Sampson et al. [223] introduce two mechanisms to
approximate PCMs, which can be used for persistent storage (e.g., for databases or filesystems)
or as main memory. The first mechanism reduces the number of programming pulses for writing
the multi-level cells (i.e., cells storing multiple bits of information), while the second one stores
approximate data in blocks with exhausted error correction resources. SoftPCM [58] integrates a
method to reduce the write traffic towards improved energy efficiency and lifetime. More specifically,
a circuit compares the new data with stored data, and the writing operation is not performed if the
difference is below a threshold.
The authors of [217] provide approximate storage in embedded flash memories by lowering the
voltage below its nominal value. To deal with unpredictable behaviors and large error rates, they
employ three software-based methods, i.e., “in-place writes”, “multiple-place writes”, and “RS-Berger
codes”. The first method repeatedly writes the data to the same memory address, while the second
one writes the data in more than one addresses. The last method is an error detection & correction
code that recovers the originally stored data. In the same context, Tseng et al. [250] characterize
various multi-level cell flash memories when the supply voltage drops during read, program and
erase operations. Based on the characterization results, they propose a dynamic scaling mechanism
that adjusts the voltage supply of flash according to the executed operation. Retention relaxation
[141] is another interesting technique applied in multi-level cell flash memories. In particular, the
write operation for data with short lifetime (e.g., data from proxy and MapReduce workloads) is
accelerated based on modeling the relationship between raw bit error rates and retention time.
The literature also includes works on approximate SST RAMs, which are non-volatile alternative
of SRAMs for on-chip scratchpad or cache memory. Sampaio et al. [220] propose an approximate
STT-RAM cache architecture that reduces the reliability overhead under a given error bound. The
application’s critical data are protected using a latency-aware double error correction module,
while approximation-aware read and write policies provide approximate storage. Moreover, the
architecture is equipped with a unit for monitoring the quality of the application’s output. To
provide an approximate scratchpad memory, Ranjan et al. [205] design a quality configurable
SST-RAM, in which read and write operations are executed at varying accuracy levels. Approximate
reads are performed by either lowering the current used to sense the stored value or lowering
the sensing duration and increasing the current. Similarly, approximate writes are performed by
lowering the current and/or sensing duration. Furthermore, the authors of [286] propose a scheme
for progressively scaling the cells of STT-RAM arrays based on a scaling factor. In this approach,
the most significant bits of the data words are implemented to provide lower bit error rates from the
least-significant ones. In [247], the authors propose AdAM, which provides adaptive approximation
management across the entire non-volatile memory hierarchy. In more detail, they model a system
with STT-RAM scratchpad and PCM main memory and apply various approximation knobs (e.g.,
read/write pulse magnitude/duration) to exchange data accuracy for improved STT-RAM access
delay and PCM lifetime.
4.2.2 Approximate Volatile Memories. Regarding SRAM memories, significant research efforts have
focused on lowering the supply voltage. In this context, Kumar et al. [118] apply system-level design
techniques to reduce the SRAM leakage power. Their framework is constrained by a data-reliability
factor, while they use a statistical/probabilistic setup to model soft errors and process variations. In
[34], the authors propose a hybrid memory array for video processors. Their policy is to store the
high-order bits of luminance pixels, i.e., those that are more sensitive to human vision, in robust

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 13

8T SRAM bit-cells, while the low-order bits are stored in 6T bit-cells. This approach allows to
lower the supply voltage without significantly affecting the high-order bits. Frustaci et al. [61]
evaluate a wide range of approximation techniques (bit dropping, selective write assist, selective
error correcting code, voltage scaling) for dynamic management of the energy–quality trade-off in
SRAMs. Their analysis is based on measurements on a 28-nm SRAM testchip, and it also includes
combinations of the examined techniques and different array/word sizes.
The authors of [208] use approximate SRAM and DRAM memories to implement sketches for
similarity estimation. In more detail, based on theoretical analysis and simulation, they examine the
error rates in unprotected and parity-protected memories and tune their voltage supply. Moreover,
the work in [142] applies lower refresh rates in the DRAM portions storing the non-critical data.
Similarly, Jung et al. [102] define reliable and unreliable memory regions, however, in their strategy
they completely disable the DRAM’s auto-refresh feature.
Besides SRAMs and DRAMs, the literature also includes research works on approximate caches.
In [157], the authors propose the Doppelganger cache based on the approximate similarity among
the cache values. In particular, they associate the tags of multiple similar blocks with a single data
array entry, and hence, they reduce the cache memory footprint. In the same context, the authors of
[156] propose the Bunker cache based on the spatio-value similarity, where approximately similar
data exhibit spatial regularity in memory. Their approach is to map similar data to the same cache
location with respect only to their memory address. Finally, ASCache [135] is an approximate SSD
cache that allows bit errors within a tolerable threshold, while avoiding unnecessary cache misses
and guaranteeing end-to-end data integrity.

5 APPLICATION DOMAINS OF APPROXIMATE COMPUTING

In this section, we introduce the error-tolerant application domains that have been systematically
examined for Approximate Computing. At first, we classify per domain the works presented in
Part I [129] and Part II of our survey (Table 3), and discuss approximation opportunities and
representative techniques for each domain. Next, we analyze the case studies of each domain, and
we report benchmark suites and error / Quality-of-Service (QoS) metrics that are widely used.

5.1 The Application Spectrum of Approximate Computing

Image Processing: This vital process is useful in various emerging applications from fields such
as multimedia, bio-informatics and robotics, which often require processing of tremendous amount
of data with diverse standards and formats [10]. Fortunately, image processing workloads exhibit
tolerance against errors, as most systems can accept minor perturbations or distortion within a
quality degradation limit. Thus, Approximate Computing has received increasing attention here
to mitigate the high computation cost and to enhance the efficiency of the deployed systems by
reasonable trade-offs based on constraints of the specific application.
A noticeable amount of Approximate Computing schemes and methodologies have focused
on the filters inside the image processing function, which are applied to the input image to per-
form specific processing tasks, such as edge detection or morphological processing [56]. Most of
them require intensive matrix computations and convolutions. Therefore, a several works propose
novel approximate functional units to replace the exact ones. For example, RAP-CLA proposes
approximate carry look ahead adders to achieve higher Peak Signal-to-Noise Ratio (PSNR) in
smoothing and sharpening applications compared with baselines [8]. Designs of inexact multipliers
with truncation are proposed to achieve graceful quality degradation in video compression [62].
Additionally, image processing often involves floating-point DSP computations, with particularly
resource-demanding mantissa bit operations, which can be approximated with negligible quality
loss [131]. Programming-level approximation techniques also show promising results in image

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Table 3. Classification of state-of-the-art Approximate Computing works per application domain.

Application Domain References

[2, 7, 8, 10, 25, 32, 34, 37–41, 51, 53–56, 58–60, 62, 71, 80, 81, 86, 90, 97–100, 103, 119,
127, 131, 133–135, 137, 142–145, 147, 149, 150, 156–159, 161, 163, 164, 168, 170, 177, 186,
Image Processing
187, 190, 191, 200, 201, 204, 214–216, 218–221, 226, 228, 229, 232, 240, 243, 251–254, 256–
259, 271, 272, 279–281, 287, 288, 290, 296]
[10, 20, 21, 25, 36, 45, 54–56, 70, 71, 83, 96, 104, 107, 108, 127, 132–134, 139, 140, 146, 147,
Signal Processing 152, 170, 178, 179, 186, 190, 197, 201, 202, 204, 211, 212, 218, 222, 223, 228, 239, 259, 265,
266, 279, 279, 282, 289, 290]
Computer Vision [1, 21, 51, 86, 108, 137, 158, 161, 163, 164, 167, 179, 225, 232, 234, 243]
Computer Graphics [20, 21, 29, 51, 54, 109, 142, 147, 160, 186, 187, 222, 223]
Big Data Analysis [4, 12, 66, 87, 100, 105, 117, 124, 141, 189, 195, 196, 250, 274, 294]
Databases [4, 20, 28, 105, 232, 250, 294]
[1, 11, 14, 21, 26, 28, 33, 46, 47, 51, 55, 86, 114, 131, 137, 145, 147, 153, 154, 156, 157, 167,
Data Mining
170, 200, 203–205, 207, 208, 219, 221, 224, 230, 232, 237, 243, 248, 279]
[11, 18–20, 24, 46, 47, 55, 80, 106, 112–114, 156, 157, 163, 167, 170, 178, 179, 189, 200, 203–
Machine Learning
205, 218, 219, 224, 249, 279, 293]
[3, 9, 13, 29, 42, 47, 48, 57, 63, 65, 65, 68, 69, 75, 75–79, 82, 84, 85, 88, 89, 93, 94, 94, 95, 110,
111, 111, 115, 115, 125, 128, 130, 131, 136, 138, 148, 172–174, 180, 181, 183, 184, 191, 192,
Artificial Neural Networks
198, 199, 203, 205, 206, 213, 215, 224, 231, 233, 236, 241, 244–246, 253, 255, 260, 261, 263,
264, 267–270, 273, 279, 283–285, 292, 293, 295]
[14, 25, 26, 31, 44, 45, 50, 54, 60, 70, 97, 100, 107, 108, 121–123, 131, 155, 157, 159, 160, 186,
Scientific Computing
187, 201, 209, 211, 212, 222–225, 280, 282]
[1, 20, 21, 26, 60, 86, 100, 137, 139, 147, 157–159, 170, 218, 221, 230, 232, 251, 258, 280, 282,
Financial Analysis
291]
Physics Simulations [1, 14, 27, 29, 51, 137, 147, 155, 157, 158, 160, 162, 164, 209, 210, 218, 221, 224, 258, 282, 291]

processing applications. Chisel provides system-level support of optimizing approximate configura-

tions and shows higher energy savings as to image processing benchmarks such as scale, DCT and
IDCT [159]. Furthermore, there are language-specific frameworks designed for Java applications
such as 3D tracers and edge detection [186].
Signal Processing: In edge computing and IoT systems, various signal processing methodologies
and algorithms are applied to process raw signal from sensors, which are often associated to
noise [223]. Recently, signal processing algorithms are migrating from cloud-based platforms with
high computation capabilities, such as servers and desktops, to the edge and low power-devices (i.e.,
embedded systems) that are often resource-constrained and cost-sensitive. Real-time requirements
are common in signal processing systems, thus Approximate Computing schemes are proposed to
suffice critical performance requirements [21]. Memory storage can also benefit from Approximate
Computing. For example, the work in [223] uses reduced precision operations (e.g., memory write)
to extend the storage lifetime.
Filters in signal processing systems usually consumes considerable amount of energy. Finite
Impulse Response (FIR) filters with voltage scaling strategies and reduced precision redundancy can
achieve considerable energy saving with negligible degradation of Signal-to-Noise Ratio (SNR) [36].
Hardware-level approximate designs such as reverse carry propagate adders are also implemented
in FIRS filters to replace exact functional units [190]. Moreover, FIR filters are optimized at the
architecture level, for example, the PANDORA framework eliminates loop-carried dependencies,
achieving up to 81× speed-up with acceptable errors [239]. In addition to filters, signal trans-
formations (e.g., the discrete Fourier transform) are also target of approximation, as their main

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computations come from trigonometric functions, which require massive amount of floating-point
computations, while at the same time they can tolerate errors [20].
Computer Vision: Computer vision is critical in many emerging applications such as aug-
mented/virtual reality, autonomous driving and robotics. These applications often require intensive
computation efforts on large volume of data. One core component of a computer vision system is
the computation kernel known as meta-functions, which are dedicated to execute one specific algo-
rithm. As those meta-functions are typically inherently error resilient, voltage scaling techniques
are applied to obtain attractive quality–energy trade-offs [167]. Another application, ray tracing,
which is also a common computer vision task, requires intensive arithmetic with floating-point
numbers, whose precision can be formulated as a stochastic optimization problem for accelera-
tion [225]. Some computer vision applications are deployed onto perpetual systems, i.e., embedded
systems that are not connected to power but rely on harvesting energy from the environment. Such
systems often have strict power constraints when executing demanding machine vision algorithms.
Therefore, specialized languages and runtimes are proposed to maximize QoS on such platforms
for tasks such as tracking and remote sensing [234].
From the software aspect, various computer vision applications including motion estimation and
body tracing also exhibit tolerance against code perforations, inspiring opportunities of slightly com-
promising accuracy for increasing the performance by two to three times [86]. However, although
the accuracy and quality degradation from approximation are negligible at most times, computer
vision systems may still output critically inaccurate or erroneous results. The language Topaz
enables outlier task detection and re-execution, which can collaborate with existing approximate
solutions to ensure that tasks such as subject pose tracking produce acceptable results [1].
Computer Graphics: Modern digital photography and filming as well as 3D modelling, ren-
dering and simulation depend on extensive support from computer graphics algorithms. These
workloads demand a significant amount of computations due to the visual contents that are in-
creasingly complex. Although computationally intensive, computer graphics show opportunities
for Approximate Computing by having a strong data locality, which indicates that there are high
redundancies that can be harvested to mitigate the computation costs [109]. By using cache to
memorize outcomes of instructions, computer graphics applications such as OpenGL games can
have reduced number of instructions and witness acceleration [109]. Additionally, by leveraging the
tolerance against potentially non-deterministic parallel execution of sequential computer graphics
programs (e.g., volume rendering), notable speed-ups can be delivered [160]. Another direction of
enhancing the parallel computing performance of OpenGL application via Approximate Computing
is to relax the program semantics, where code can briefly bypass strict semantic adherence to
achieve energy saving with acceptable output quality loss [29].
Big Data Analysis: The data query is the first and foremost task in the big data analysis domain.
Targeting improved performance, an approximate query engine BlinkDB is proposed in [4]. BlinkDB
uses a set of stratified samples for the aim of optimization and deploys a dynamic sampling strategy
to select an appropriately sized sample, which permits users to trade accuracy for response time.
Other works are mainly based on Big data frameworks such as Hadoop and Spark. The authors
in [66] propose ApproxHadoop, which is a framework to run approximation-enabled MapReduce
programs. ApproxHadoop leverages statistical theories to optimize the MapReduce programs when
approximating with data sampling and task dropping. On the other hand, the authors in [87]
present a data sampling framework to enable approximate computing with estimated error bounds
in Spark, called ApproxSpark. In ApproxSpark a tree-based framework is proposed to compute the
approximate aggregate values and corresponding error bounds, which can dynamically balance the
trade-off among the sampling rates, execution time, and accuracy loss.

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16 Vasileios Leon et al.

Databases: Considering the Approximate Computing in database access, [105] introduces a

novel data query system that injects samplers in the run-time and without requiring former existing
samples. This system allows multiple join inputs and approximates the answer according to complex
outputs. In the meantime, inspired by parallel computing, [232] utilizes the nature of approximation
to improve the performance and decrease the error according to the accuracy demands.
Data Mining: During the data mining process, redundant computations, e.g., calling functions
with the same parameters or using iterative input and output data, increase the execution time
and lead to low performance. [26] targets this redundant computing and proposes an approximate
approach named ATM. ATM employs both dynamic redundancy and approximation for a task-
level computing that utilizes the previous task for the future. In practice, ATM also introduces an
adaptive algorithm in the run-time that dynamically balances the trade-off between accuracy and
performance. Moreover, [21] uses the core-level redundancy, which is a combination of accurate
and approximate versions of a task on different cores to increase the reliability. On the other hand,
[114] presents a skipping strategy aiming to improve the memory performance in data mining,
especially the recursive partitioning method such as decision tree and random forest. [147] employs
different approximate logarithmic multipliers and unique operators to reduce power consumption
and improve the performance during the data mining process.
Machine Learning: With the development of cloud computing, an increasing number of machine
learning systems have become dominant in many sophisticated and crucial software architectures.
The machine learning models can be either supervised or unsupervised, learn features from the
training data and deploy inference on unseen query data. Nowadays, most machine learning models
are data-driven, meaning that the key to their success is the input data. However, in the cloud
computing environment, the large scale data will make the machine learning process tardiness and
energy-consuming. To reduce resource consumption, recent work propose approaches in different
domains. [20] presents an energy-efficient Approximate Computing framework that dynamically
makes approximation decisions based on a predefined accuracy level. In the meantime, [80] exploits
the error resilience in the machine learning system to trade off accuracy for computational re-
sources. Moreover, [106] employs a run-time resource management approach based on functionally
approximate kernels that exploit accuracy-performance trade-offs within error resilient applications.
This approach makes performance-aware decisions on power management under varied situations.
Artificial Neural Networks: Considering the number of arithmetic operations in Artificial
Neural Networks (ANNs), the conventional architectures perform over millions of computations on
each input data, leading to a high rate of timing and energy consumption. Therefore, as explained in
Section 3, approximation techniques at different design layers aim to provide sufficient performance
and power efficiency. The approximation of ANNs imposes several challenges. One of the them
is to avoid retraining for reducing the accuracy loss [174], while the approximation localization
[130] is also a key factor towards improved resources gains. Finally, cross-layer and end-to-end
approaches [182] further increase the resource savings by exploiting the error resilience of each
layer/sub-system.
Scientific Computing: Due to the rapid development of the computing industry in recent
decades, scientific computing has become much more powerful and precise. Natural science research
has been greatly enhanced by the availability of new materials and methodologies as well as the
development of new hardware. A wide variety of scientific computing applications are employed
in various areas, such as meteorology, astrophysics, and molecular biology. Though the specific
tasks in scientific computing may vary, the underlying mathematical functions used are similar. As
an example, most mathematical simulation models include linear equations, nonlinear equations,
eigenvalue problems, FFT analysis, and ODEs. Nevertheless, the growth in computational power
cannot completely meet the computing demands of scientific computing. Therefore, the scientific

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computing community aims to develop more efficient, robust, and fast frameworks for scientific
computations to meet these demands.
As the mathematical models for scientific computing become increasingly complex and the
advanced sensors collect vast amounts of data, the computing resources become the bottleneck.
Scientific computing entails a considerable amount of continuous computation, while typically, its
targeted result is always approximate. Generally, increased computation precision will provide a
more accurate result, but it will also consume more resources. Scientists usually employ double-
precision computations to achieve a precise result, which is expensive. Many studies have examined
the trade-off between precision and performance. One of the ideas is to get a balance between
them by tuning the floating-point precision into mixed precision. The implementation in [123] uses
binary instrumentation and modification to build mixed-precision configurations, whereas [27]
uses dynamic program information and temporal locality to customize floating-point precision for
scientific computing. Two of these approaches use the system’s floating-point variables as search
space and assume the system to be a black box in order to find the best configuration with some
loss in accuracy. By analyzing the dependence between floating-point variables, the authors in
[70] design a community structure of floating-point variables and devise a scalable hierarchy for
optimization. Furthermore, the tools presented in [45] focus on determining the input settings for
a floating-point routine to understand how they affect the result’s error.
Even though cluster computers are relatively reliable, minor software and hardware faults may
still occur, particularly during the execution of lengthy tasks, like those of scientific computing.
This makes reliability and robustness an important consideration when carrying out scientific
computing. [209] presents a methodology that estimates an acceptable accuracy bound based on
the impacts of different computation errors and faults on the entire task. The technique is not
only useful in helping to create robust scientific computing frameworks, but it can also be used to
discard computations to save execution time in a reasonable manner. The work in [31] presents
a programming language that can determine the quantitative reliability of a specific computing
application running on unreliable hardware. The skipping of data accesses is not only for precision
tuning and robustness analysis but also for boosting the computations. Similarly, special hardware
designs can be viewed as an approximation technique. [97] devise a special divider and square root
circuit that uses an adaptive approximation to increase the computation rate and save energy.
Financial Analysis: Financial analysis is another area in which approximate computations
can be useful. The internet and the digitalization of the financial industry have led to increased
importance of computation in financial analysis, especially when analyzing large amounts of data
and incorporating machine learning. With the advent of these technologies, quantitative finance
models continue to develop. The use of approximate computations increases the efficiency of data
analysis, as well as enables real-time processes. For example, [251] demonstrate a compiler-directed
output-based approximate memoization function that provides speedup in two different financial
analysis applications to pricing a portfolio of stock options and swaptions. In the meanwhile,
[100] presents a framework for algorithmic profiling known as AXPROF for analyzing randomized
approximate programs, which are important to the analysis of big financial data.
Physics Simulations: Apart from being a part of scientific computing, simulation of physical
phenomena involves some more specific areas, such as hydrodynamics simulation, thermodynamics
simulation, and optical simulation. Many of these tasks are very compute-intensive. Approximate
Computing can be applied to the physics simulation to accelerate this process. [164] presents a
novel system called OPPROX for the application’s execution-phase-aware approximation. OPPROX
is demonstrated to be an efficient method for reducing dozens of workloads in a simulation of
the Sedov blast wave problem. Additionally, the authors in [29] seek to combine Approximate

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18 Vasileios Leon et al.

Computing with automatic parallelization by allowing the user to select tuning knobs that can be
used to trade performance gains and/or energy savings for output distortion.

5.2 Application-Driven Analysis of Case Studies

Table 4 presents the respective analysis of the aforementioned application domains, including also
some statistical results about the dominant sub-categories for each layer of the computing stack.
Regarding the distribution of the main techniques in the various research areas, Table 4 reveals a
considerable heterogeneity that is contingent upon the particular use case. As shown, works in
image processing are almost evenly distributed through the entire computing stack (i.e., 24 software-
, 25 hardware-, and 25 architecture-level works). However, within the specific domain, notably,
multiplier approximations dominate over the other hardware techniques, accounting for almost
80% of the total works. Similar observations arise for big data analysis, where software-oriented
approximations this time, and specifically data sampling sub-category, constitute the vast majority
and the most prominent solutions. On the other hand, it is noteworthy that in five application
domains (computer graphics, big data analysis, databases, financial analysis and physics simulations)
there are no works focusing on hardware-level approximations. This might be explained by the fact
that research and development efforts in these domains are traditionally revolved around software
algorithms, optimizations and data management techniques, rather than the lower level of the
design abstraction hierarchy. The latter highlights, thus, the space for further exploration and
development of hardware-oriented approximate designs.
Table 4 also reports some significant experimental results, most of them concerning speedup,
area and power/energy gains over conventional designs, with their respective overheads and/or
quality losses. Out of all the techniques reported, it is observed that software-based approximations
realize the highest speedups compared to hardware and architectural approximations. For example,
the memoization approach of [26] achieves 16× speedup for only 5% memory overhead and 3%
accuracy loss, while [294] manages up to 20× speedup for accurate execution. Finally, the table
underscores the potential of Approximate Computing in machine learning applications, at each layer
of the computing stack, that can attain remarkable energy reduction (22%–54%), while maintaining
unaffected the level of quality with zero accuracy loss.

5.3 Benchmark Suites and Error Metrics

Various open source benchmark suites for approximate computing have been proposed and released.
In Table 5, we report some of the most well-established suites, which have been employed in
the state-of-the-art works examined in this survey. Parallel programming benchmarks including
PARSEC (Princeton Application Repository for Shared-Memory Computers) [23] and SPLASH-2
(Stanford Parallel Applications for Shared Memory) [275] are cross-domain benchmark suites
with different emerging applications for evaluating and studying parallel chip-multiprocessors.
There are also benchmarks focusing on multimedia and communication applications such as
MediaBench [126]. SciMark is a benchmark suite primarily focusing on Java language applications
of scientific computing, including kernels like FFT, sparse matrix multiplication, Monte Carlo
simulation and successive over-relaxation [194]. With the development of multi-platform parallel
or acceleration libraries such as OpenMP, OpenCL and CUDA, more recent benchmarks focus
on those libraries and frameworks. Rodinia is a benchmark set for heterogenous computing with
diverse applications targeting at platforms from multi-core CPU systems to GPUs [35]. Regarding
hardware, AxBench provides Verilog and C benchmark implementations [277].
Various error/QoS metrics have been proposed to describe and evaluate the capability of Approx-
imate Computing techniques and methodologies, as shown in Table 6. At the bottom level, different
error rates are used, such as Error Rate (ER), which calculates the number of erroneous results

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 19

Table 4. Remarkable improvements among all examined works with respect to the application domain and
the different layers of computing stack.

Application Domain Stack #Works Main Techniques Remarkable Gains Ref.

34% energy gains &
SW 24 Approx. Progr. Language [187]
113× less programming effort
Image Processing 95% energy gains & 85% area
HW 25 Multiplier Approx. [253]
reduction for 1% accuracy loss
Arch 25 Approx. Data Storage 1.7× speedup for <10% quality loss [223]
SW 13 Precision Scaling 1.33× speedup for no accuracy loss [107]
HW 11 Approx. Synthesis 60% power gains for <2% avg. error [265]
Signal Processing
2.3× speedup & 3× energy gains
Arch 4 Approx. Processor [55]
for <10% accuracy loss
SW 12 Loop Perforation 35% energy gains & 40% area reduction [21]
Computer Vision HW 3 Approx. Synthesis 23% power gains & 19% area savings [179]
Arch 1 Approx. Processors 40% energy gains for negligible quality loss [51]
SW 10 Approx. Progr. Language 2×–17× energy gains [186]
Computer Graphics HW 0 – – –
Arch 3 Approx. Processor up to 43% energy gains [54]
SW 13 Data Sampling up to 8× speedup & 38% wait time reduction [12]
HW 0 – – –
Big Data Analysis
1.8×–5.7× speedup for <1%
Arch 2 Approx. Data Storage [141]
memory overhead
SW 5 Data Sampling up to 20× speedup for precise execution [294]
HW 0 – –
Databases
22%–45% energy gains for
Arch 2 Approx. Data Storage [250]
0.1% performance loss
SW 19 Loop Perforation 6.4×/7.1× for 5%/10% error budget [137]
up to 86% power, 46% delay & 63% area
HW 5 Multiplier Approx. [145]
Data Mining gains for NMED <0.0081
1.2× speedup, 1.4× energy gains
Arch 14 Approx. Processor [55]
for 6% quality loss
SW 12 Computation Skipping 2.18× energy gains for <0.5% accuracy loss [200]
Machine Learning HW 10 Voltage Over-Scaling 22% power reduction for no accuracy loss [19]
Arch 10 Approx. Processor 24% energy reduction for no accuracy loss [177]
2× speedup, 1.9× energy gains
SW 40 Computation Skipping [9]
for 3% accuracy loss
Artificial Neural Networks HW 40 Multiplier Approx. 2.8× power gains for 5% accuracy loss [131]
up to 2× energy gains for
Arch 7 Approx. Data Storage [203]
negligible accuracy loss
up to 1.25× energy gains for
SW 26 Approx. Progr. Language [159]
negligible quality loss
3.9× speedup, 4.8× power gains
Scientific Computing HW 2 Divider Approx. [97]
for <5% NMED
up to 2.55× energy gains, 1.55× cache
Arch 6 Approx. Data Storage [157]
area reduction for <10% quality error
16× speedup for 5% memory overhead &
SW 19 Approx. Memoization [26]
<3% accuracy loss
Financial Analysis
HW 0 – –
Arch 4 Approx. Processor 2.1× energy gains for 4% quality loss [209]
SW 16 Approx. Memoization 3× speedup for 10% quality loss [218]
Physics Simulations HW 0 – –
Arch 5 Approx. Processor 1.25× energy gains for negligible quality loss [51]

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20 Vasileios Leon et al.

Table 5. Open-source benchmark suites used in state-of-the-art works of Approximate Computing.

Benchmark Suite Source Code Application Domain

Image Processing, Computer Vision, Data Mining, Financial
PARSEC [23] C/C++
Analysis, Physics Simulations
SPLASH-2 [275] C Scientific Computing, Computer Graphics, Physics Simulations
MediaBench [126] C Image Processing, Signal Processing
MiBench [72] C Image Processing, Signal Processing
MiniBench [176] C/C++ Data Mining
Data Mining, Scientific Computing, Physics Simulation, Ma-
Rodinia [35] OpenMP, OpenCL, CUDA
chine Learning
PolyBench [193] C, CUDA Scientific Computing
SciMark 2.0 [194] Java Scientific Computing
Image Processing, Signal Processing, Computer Graphics, Data
AxBench [277] C++, CUDA, Verilog
Mining, Financial Analysis

Table 6. Error/QoS metrics of Approximate Computing.

Metric Description Application Domain

ER Error Rate – Erroneous results per total results
EP Error Probability – Probability of error occurrence
MED/MRED Mean (Relative) Error Distance
NMED/NMRED Normalized Mean (Relative) Error Distance
Max ED/RED Maximum (Relative) Error Distance General Computing
PED/PRED Probability of (Relative) Error Distance > 𝑋
MSE Mean Squared Error
RMSE Root Mean Squared Error
HD Hamming Distance
BER Bit Error Ratio – Bit errors per total received bits Digital Systems,
PER Packet Error Ratio – Incorrect packets per total received packets Telecommunications
PSNR Peak Signal-to-Noise Ratio – Quality measurement between images
Image Processing, Video
SSIM Structural Similarity – Quality measurement between images
Processing, Computer Vision
MPD Mean Pixel Difference
Classif. Accuracy Correct classifications per total classifications Pattern Recognition,
Precision Relevant instances per total retrieved instances Information Retrieval,
Recall Relevant instances per total relevant instances Machine Learning

over the total number of results, and correspondingly, Bit Error Ratio (BER), which calculates the
number of erroneous bits over the total bits. Another family of error metrics is the Error Distance
(ED), including Hamming Distance (HD), Mean (Relative) ED (MED/MRED), Normalized MED
(NMED), and other numerical-based metrics. Another metric that is employed in the evaluation
of approximate designs is the Probability of (Relative) ED higher than 𝑋 (PRED/PRED), where 𝑋
is a numerical value, Finally, Mean Squared Error (MSE) and Root MSE (RMSE) are also common
metrics to evaluate the output quality.
There are also application-specific error metrics to describe the efficiency of the approximations at
a higher level. For example, in telecommunications, Packet Error Ratio (PER) is usually considered to
evaluate the communication quality. In ML applications, such as pattern recognition and information
retrieval, classification accuracy is usually considered, as well as other metrics such as precision

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Approximate Computing Survey, Part II: Application-Specific & Architectural Techniques and Applications 21

(relevant instances of retrieved instances) and recall (relevant instances of total instances). These
metrics provide a systematic view on the assessment of the approximate application.

6 CHALLENGES AND FUTURE DIRECTIONS

This section highlights several key challenges that need to be addressed to accelerate progress in
Approximate Computing and enable its use in real-world systems.
Cross-Layer and End-to-End System-Level Approximations: Most of the research in Ap-
proximate Computing have focused on individual abstraction layers of the computing stack. How-
ever, the true potential of Approximate Computing lies in cross-layer and end-to-end system-level
approximations, where multiple complementary approximation techniques are combined to achieve
a better quality–efficiency trade-off. Therefore, a system-level view is necessary for trading quality
for efficiency, as approximation can be deployed at different abstraction layers and in different
components. Only the right set of approximations deployed at the right layers and in the right
components can offer optimal returns. Some existing works in this direction include [6, 65, 82].
However, still a significant amount of research is required to develop sophisticated automated
methodologies that can efficiently identify the appropriate set of approximations for all the compo-
nents in a system to offer the best quality–efficiency trade-off while satisfying the user-defined
constraints. One of the key limitations towards enabling such methodologies is the lack of tools
and methods that can efficiently and accurately quantify the impact of approximations, specifically
multiple types of approximations, on the application-level accuracy of the systems.
Hardware Models: The field of Approximate Computing lacks validated hardware models that
are essential for performing efficient-yet-accurate design space exploration to select appropriate
level of approximation for each hardware module in the system. For example, the models used
for voltage overscaling are based on assumptions about the distribution of errors in computing
and memory structures. Similarly, most of the ReRAM-based in-memory computing works are
based on assumptions about the precision with which values can be written to or read from the
memory arrays. Moreover, different works use different models and assumptions, which makes it
difficult to compare techniques based on the reported results. Therefore, there is a dire need for
building hardware models that have been validated by the hardware community through extensive
simulations. The models need to be validated for a wide variety of scenarios to enable their reliable
deployment in cross-layer approximation methodologies.
Benchmarks: The Approximate Computing community lacks representative sets of applications
as well as datasets from different application domains that can be used for benchmarking approxima-
tion techniques. Having a carefully selected set of applications and datasets is crucial, as the impact
of approximations can vary drastically from application to application and even from data sample
to data sample. Some efforts have been made towards defining benchmarks, e.g., AxBench [278];
however, these efforts cover only a small set of applications and scenarios. Therefore, there is a need
for a much broader set of applications and datasets from a wider spectrum of application domains.
Moreover, as it is difficult to cover all the application domains and applications, specifically when
new applications are emerging on a daily basis due to the rapid pace of technology growth, there
is a need for standards and rules for defining evaluation strategies and selecting datasets for an
unbiased and thorough evaluation of approximation techniques.
Evaluation Metrics: Design space exploration methodologies are guided through quality and
performance evaluation metrics to find the optimal configurations that offer the best quality–
efficiency trade-offs and meet all the user-defined constraints. As a result, it is crucial to have
reliable quality and performance evaluation metrics in place. Metrics that do not capture suitable
characteristics can lead to sub-optimal configurations, eventually affecting the user experience.
Therefore, it is essential to define the right set of quality evaluation metrics for each application.

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22 Vasileios Leon et al.

Post-Fabrication Testing: Process variations, which lead to permanent faults and variations
in the hardware characteristics of transistors, are a major concern in nano-scale devices. All the
fabricated devices are passed through post-fabrication testing to detect manufacturing-induced
defects and variations. However, approximations make this already challenging process further
challenging. Only a limited amount of work has been carried out towards testing of Approximate
Computing devices. Therefore, there is a dire need for specialized approximation-aware testing
methodologies that can enable efficient-yet-accurate testing of these devices and reduce the yield
loss, wherever possible, through binning.
Reproducibility for Fair Comparison and Future Developments: In most cases, it is chal-
lenging to replicate the exact evaluation methodology and setup reported in research works, making
it difficult (if not impossible) to reproduce the results. Therefore, it is essential to promote open-
source contributions to ensure the reproducibility of the results. The open-source contributions will
also facilitate further research and development in the area of Approximate Computing, resulting
in rapid progress towards uncovering the true potential of Approximate Computing for improving
the efficiency of computing systems.

7 CONCLUSION
In this article, we presented Part II of our survey on Approximate Computing, which reviews the
state-of-the-art application-specific and architectural approximation techniques. Regarding the
application-specific techniques, we focused on the emerging AI/ML applications and discussed
about software, hardware, cross-layer and end-to-end approximations. Regarding the architectural
techniques, we focused on approximate processors & accelerators and different memory types
for approximate data storage. Moreover, we performed an extensive analysis of the application
spectrum of Approximate Computing, i.e., we classified per domain all the works reviewed in our
two-part survey, we presented representative techniques and remarkable results, as well as we
reported well-established error metrics and benchmark suites for evaluating the quality-of-service
of approximate designs. Despite the notable progress demonstrated by Approximate Computing,
there remains a pressing need for ongoing and significant innovation to fully realize the potential of
approximations in the design of complex computing systems. These open challenges are discussed
along with future directions at the end of our survey.

ACKNOWLEDGEMENT
This research is supported in parts by ASPIRE, the technology program management pillar of Abu
Dhabi’s Advanced Technology Research Council (ATRC), via the ASPIRE Awards for Research
Excellence.

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Received 18 July 2023

ACM Computing Surveys, Under Review. July 2023.