Scribd Logo
Upload

Welcome to Scribd!

  • 6 views

    Exp 3. Encoders & Decoders

    Uploaded by

    221225

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Exp 3. Encoders & Decoders

    Uploaded by

    221225
    6 views17 pages

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    6 views17 pages

    Exp 3. Encoders & Decoders

    Uploaded by

    221225

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 17

    EX.NO.

    : 3
    Encoders and Decoders
    DATE:

    Aim: To simulate Encoders and decoders in behavioral, structural and data flow model of Verilog HDL.

    Software used: ModelSim – Advanced Simulation and debugging Tool

    Program:

    4 to 2 line Encoder:

    Behavioral Model

    module encoder_4x2_b(
    input [3:0] in,
    output reg [1:0] out
    );

    always @(in) begin


    case (in)
    4'b1000: out = 2'b11;
    4'b0100: out = 2'b10;
    4'b0010: out = 2'b01;
    4'b0001: out = 2'b00;
    default: out = 2'bxx;
    endcase
    end

    endmodule

    structural Model

    module encoder_4x2_s(
    input [3:0] in,
    output [1:0] out);

    or G1(out[1],in[3],in[2]);
    or G2(out[0],in[3],in[1]);

    endmodule

    data flow model


    module encoder_4x2_df(
    input [3:0] in,
    output [1:0] out);

    assign out[1] = ~in[0] & ~in[1] & (in[2] ^ in[3]);


    assign out[0] = ~in[0] & ~in[3] & (in[2] ^ in[1]);

    endmodule
    Testbench:

    module encoder_4x2_tb();
    reg [3:0] in;
    wire [1:0] out;

    encoder_4x2_df UUT (in, out);

    initial begin
    $monitor("in = %b, out = %b", in, out);

    in = 4'b1000; #10;
    in = 4'b0100; #10;
    in = 4'b0010; #10;
    in = 4'b0001; #10;
    in = 4'b0000; #10;

    $finish;
    end
    endmodule

    8 to 3 line Encoder:

    module encoder_8x3_b(

    input [7:0] in,

    output reg [2:0] out

    );

    always @(in) begin

    case (in)

    8'b10000000: out = 3'b111;

    8'b01000000: out = 3'b110;

    8'b00100000: out = 3'b101;

    8'b00010000: out = 3'b100;

    8'b00001000: out = 3'b011;

    8'b00000100: out = 3'b010;

    8'b00000010: out = 3'b001;


    8'b00000001:out = 3'b000;

    default: out = 3'bxxx;

    endcase

    end

    endmodule

    module priority_encoder_8x3_b(

    input [7:0] in,

    output reg [2:0] out

    );

    always @(in) begin

    casex (in)

    8'b1xxxxxxx: out = 3'b111;

    8'b01xxxxxx: out = 3'b110;

    8'b001xxxxx: out = 3'b101;

    8'b0001xxxx: out = 3'b100;

    8'b00001xxx: out = 3'b011;

    8'b000001xx: out = 3'b010;

    8'b0000001x: out = 3'b001;

    8'b00000001: out = 3'b000;

    default: out = 3'bxxx;

    endcase

    end

    endmodule

    Testbench:
    module encoder_8x3_tb();
    reg [7:0] in;
    wire [2:0] out;

    encoder_8x3_b UUT (in, out);

    initial begin
    $monitor("in = %b, out = %b", in, out);

    in = 8'b10000000; #10;
    in = 8'b01000000; #10;
    in = 8'b00100000; #10;
    in = 8'b00010000; #10;
    in = 8'b00001000; #10;
    in = 8'b00000100; #10;
    in = 8'b00000010; #10;
    in = 8'b00000001; #10;
    in = 8'b00000000; #10;

    $finish;
    end
    endmodule

    8 to 3 Priority Encoder:

    module priority_encoder_8x3_b(
    input [7:0] in,
    output reg [2:0] out
    );

    always @(in) begin


    casex (in)
    8'b1xxxxxxx: out = 3'b111;
    8'b01xxxxxx: out = 3'b110;
    8'b001xxxxx: out = 3'b101;
    8'b0001xxxx: out = 3'b100;
    8'b00001xxx: out = 3'b011;
    8'b000001xx: out = 3'b010;
    8'b0000001x: out = 3'b001;
    8'b00000001: out = 3'b000;
    default: out = 3'bxxx;
    endcase
    end

    endmodule

    Testbench:

    module prio_encoder_8x3_tb();
    reg [7:0] in;
    wire [2:0] out;

    priority_encoder_8x3_b UUT (in, out);

    initial begin
    $monitor("in = %b, out = %b", in, out);

    in = 8'b10000000; #10;
    in = 8'b01000000; #10;
    in = 8'b00100000; #10;
    in = 8'b00010000; #10;
    in = 8'b00001000; #10;
    in = 8'b00000111; #10;
    in = 8'b00000011; #10;
    in = 8'b00000001; #10;
    in = 8'b00000000; #10;

    $finish;
    end
    endmodule

    Decoders:

    2 to 4 Decoder

    Behavioral Model

    module decoder_2x4_b(input [1:0] in, output reg [3:0] out);

    always @(in) begin


    case (in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = 4'b1000;
    default: out = 4'b1111;
    endcase
    end
    endmodule

    structural Model

    module decoder_2x4_s(input [1:0] in, output [3:0] out);


    wire n0,n1;
    not g1(n0,in[0]);
    not g2(n1,in[1]);
    and g3(out[0],n0,n1);
    and g4(out[1],n1,in[0]);
    and g5(out[2],in[1],n0);
    and g6(out[3],in[1],in[0]);

    endmodule
    data flow model

    module decoder_2x4_df(input [1:0] in, output [3:0] out);

    assign out[0] = (~in[0] & ~in[1]);


    assign out[1] = (in[0] & ~in[1]);
    assign out[2] = (~in[0] & in[1]);
    assign out[3] = (in[0] & in[1]);

    endmodule

    Testbench:

    module decoder_2x4_tb();
    wire [3:0] out;
    reg [1:0] in;
    decoder_2x4_df M1(in, out);

    initial begin
    $monitor("in = %b, out = %b", in, out);

    in = 2'b00; #10;
    in = 2'b01; #10;
    in = 2'b10; #10;
    in = 2'b11; #10;
    $finish;
    end

    endmodule

    3 to 8 Decoder

    module decoder_3x8_b(input [3:0] in, output reg [7:0] out);

    always @(in) begin

    case (in)
    4'b0001: out = 8'b00000001;
    4'b0011: out = 8'b00000010;
    4'b0101: out = 8'b00000100;
    4'b0111: out = 8'b00001000;
    4'b1001: out = 8'b00010000;
    4'b1011: out = 8'b00100000;
    4'b1101: out = 8'b01000000;
    4'b1111: out = 8'b10000000; //last bit is enable
    default: out = 8'b11111111;
    endcase
    end

    endmodule

    Testbench:
    module decoder_3x8_tb;

    wire [7:0] out;


    reg [3:0] in;
    decoder_3x8_b M1(in,out);

    initial begin
    $monitor("in = %b out = %b", in, out);

    in = 4'b0001; #10;
    in = 4'b0011; #10;
    in = 4'b0101; #10;
    in = 4'b0111; #10;
    in = 4'b1001; #10;
    in = 4'b1011; #10;
    in = 4'b1101; #10;
    in = 4'b1111; #10;
    $finish;
    end

    endmodule

    5 to 32 line decoder using 2 to 4 line and 3 to 8 line decoders:

    module decoder2to4(input [1:0] A, input E, output [3:0] Y);


    assign Y = E ? (1 << A) : 4'b0000;
    endmodule

    module decoder3to8(input [2:0] A, input E, output [7:0] Y);


    assign Y = E ? (1 << A) : 8'b00000000;
    endmodule

    module decoder5to32(input [4:0] A, output [31:0] Y);


    wire [3:0] E;
    decoder2to4 dec1(A[4:3], 1'b1, E);
    decoder3to8 dec2(A[2:0], E[0], Y[7:0]);
    decoder3to8 dec3(A[2:0], E[1], Y[15:8]);
    decoder3to8 dec4(A[2:0], E[2], Y[23:16]);
    decoder3to8 dec5(A[2:0], E[3], Y[31:24]);
    endmodule

    Testbench:

    module t_decoder5to32;
    reg [4:0] A;
    wire [31:0] Y;
    decoder5to32 uut(A, Y);
    initial begin
    $monitor("A = %b, Y = %b", A, Y);
    A = 5'b00000; #10;
    A = 5'b00001; #10;
    A = 5'b00010; #10;
    A = 5'b00011; #10;
    A = 5'b00100; #10;
    A = 5'b00101; #10;
    A = 5'b00110; #10;
    A = 5'b00111; #10;
    A = 5'b01000; #10;
    A = 5'b01001; #10;
    A = 5'b01010; #10;
    A = 5'b01011; #10;
    A = 5'b01100; #10;
    A = 5'b01101; #10;
    A = 5'b01110; #10;
    A = 5'b01111; #10;
    A = 5'b10000; #10;
    A = 5'b10001; #10;
    A = 5'b10010; #10;
    A = 5'b10011; #10;
    A = 5'b10100; #10;
    A = 5'b10101; #10;
    A = 5'b10110; #10;
    A = 5'b10111; #10;
    A = 5'b11000; #10;
    A = 5'b11001; #10;
    A = 5'b11010; #10;
    A = 5'b11011; #10;
    A = 5'b11100; #10;
    A = 5'b11101; #10;
    A = 5'b11110; #10;
    A = 5'b11111; #10;
    $finish;
    end
    endmodule

    Circuit diagram:
    Encoder:
    4 to 2 line Encoder:

    Q1 = ~D0 & ~D1 & (D2 ^ D3)

    Q0 = ~D0 & ~D3 & (D2 ^ D1)


    Q1 = D2 | D3

    Q0 = D1 | D3

    8 to 3 line Encoder:
    8 to 3 Priority Encoder:

    Decoders:
    2 to 4 Decoder
    3 to 8 Decoder
    5 to 32 line decoder using 2 to 4 line and 3 to 8 line decoder
    Simulation Waveform:

    4 to 2 line Encoder:

    8 to 3 line Encoder:
    8 to 3 Priority Encoder:

    Decoders:

    2 to 4 Decoder

    3 to 8 Decoder

    5 to 32 line decoder using 2 to 4 line and 3 to 8 line decoder4 to 2 line Encoder:


    Result:

    Thus the logic circuits for the adders and subtractors are designed in Verilog HDL and the output
    combinations are verified in Modelsim.

    You might also like