Carnegie Mellon

Machine-Level Programming IV:

Data

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Today
 Arrays
▪ One-dimensional
▪ Multi-dimensional (nested)
▪ Multi-level
 Structures
▪ Allocation
▪ Access

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Today
 Procedures (x86-64)
 Arrays
▪ One-dimensional
▪ Multi-dimensional (nested)
▪ Multi-level
 Structures

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Basic Data Types

 Integral
▪ Stored & operated on in general (integer) registers
▪ Signed vs. unsigned depends on instructions used
Intel ASM Bytes C
byte b 1 [unsigned] char
word w 2 [unsigned] short
double word l 4 [unsigned] int
quad word q 8 [unsigned] long int (x86-64)

 Floating Point
▪ Stored & operated on in floating point registers
Intel ASM Bytes C
Single s 4 float
Double l 8 double
Extended t 10/12/16 long double
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Array Allocation
 Basic Principle
T A[L];
▪ Array of data type T and length L
▪ Contiguously allocated region of L * sizeof(T) bytes

char string[12];

x x + 12
int val[5];

x x+4 x+8 x + 12 x + 16 x + 20
double a[3];

x x+8 x + 16 x + 24
char *p[3]; IA32
x x+4 x+8 x + 12

x86-64
x x+8 x + 16 x + 24
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Array Access
 Basic Principle
T A[L];
▪ Array of data type T and length L
▪ Identifier A can be used as a pointer to array element 0: Type T*

int val[5]; 1 5 2 1 3
x x+4 x+8 x + 12 x + 16 x + 20

 Reference Type Value

val[4] int 3
val int * x
val+1 int * x+4
&val[2] int * x+8
val[5] int ??
*(val+1) int 5
val + i int * x+4i
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Array Example
#define ZLEN 5
typedef int zip_dig[ZLEN];

zip_dig cmu = { 1, 5, 2, 1, 3 };
zip_dig mit = { 0, 2, 1, 3, 9 };
zip_dig ucb = { 9, 4, 7, 2, 0 };

zip_dig cmu; 1 5 2 1 3
16 20 24 28 32 36
zip_dig mit; 0 2 1 3 9
36 40 44 48 52 56
zip_dig ucb; 9 4 7 2 0
56 60 64 68 72 76

 Declaration “zip_dig cmu” equivalent to “int cmu[5]”

 Example arrays were allocated in successive 20 byte blocks
▪ Not guaranteed to happen in general
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Array Accessing Example

zip_dig cmu; 1 5 2 1 3
16 20 24 28 32 36

int get_digit
(zip_dig z, int dig)
{
return z[dig];
} ◼ Register %edx contains
starting address of array
IA32 ◼ Register %eax contains
# %edx = z array index
# %eax = dig ◼ Desired digit at
movl (%edx,%eax,4),%eax # z[dig] 4*%eax + %edx
◼ Use memory reference
(%edx,%eax,4)
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Multidimensional (Nested) Arrays

 Declaration A[0][0] • • • A[0][C-1]
T A[R][C];
• •
▪ 2D array of data type T • •
▪ R rows, C columns • •
▪ Type T element requires K bytes
A[R-1][0] • • • A[R-1][C-1]
 Array Size
▪ R * C * K bytes
 Arrangement
▪ Row-Major Ordering

int A[R][C];
A A A A A A
[0] • • • [0] [1] • • • [1] • • • [R-1] • • • [R-1]
[0] [C-1] [0] [C-1] [0] [C-1]

4*R*C Bytes
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Today
 Structures
▪ Allocation
▪ Access

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Structure Allocation
struct rec {
int a[3]; Memory Layout
int i; a i n
struct rec *n;
}; 0 12 16 20

 Concept
▪ Contiguously-allocated region of memory
▪ Refer to members within structure by names
▪ Members may be of different types

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Structure Access
r r+12
struct rec {
int a[3];
int i; a in
struct rec *n;
}; 0 12 16 20

 Accessing Structure Member

▪ Pointer indicates first byte of structure
▪ Access elements with offsets

void IA32 Assembly

set_i(struct rec *r,
# %edx = val
int val)
# %eax = r
{
movl %edx, 12(%eax) # Mem[r+12] = val
r->i = val;
}

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Generating Pointer to Structure Member

r r+idx*4
struct rec {
int a[3];
a i n
int i;
struct rec *n; 0 12 16 20
};

 Generating Pointer to int *get_ap

(struct rec *r, int idx)
Array Element {
▪ Offset of each structure return &r->a[idx];
member determined at }
compile time
▪ Arguments movl 12(%ebp), %eax # Get idx
sall $2, %eax # idx*4
▪ Mem[%ebp+8]: r
addl 8(%ebp), %eax # r+idx*4
▪ Mem[%ebp+12]: idx

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struct rec {
int a[3];
Following Linked List int i;
struct rec *n;
 C Code };

void set_val
(struct rec *r, int val) a i n
{ 0 12 16 20
while (r) {
int i = r->i; Element i
r->a[i] = val;
r = r->n; Register Value
} %edx r
}
%ecx val
.L17: # loop:
movl 12(%edx), %eax # r->i
movl %ecx, (%edx,%eax,4) # r->a[i] = val
movl 16(%edx), %edx # r = r->n
testl %edx, %edx # Test r
jne .L17 # If != 0 goto loop
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Summary
 Arrays
▪ One-dimensional
▪ Multi-dimensional (nested)
 Structures
▪ Allocation
▪ Access

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The Memory Hierarchy

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Today
 Storage technologies and trends
 Locality of reference
 Caching in the memory hierarchy

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Random-Access Memory (RAM)

 Key features
▪ RAM is traditionally packaged as a chip.
▪ Basic storage unit is normally a cell (one bit per cell).
▪ Multiple RAM chips form a memory.
 Static RAM (SRAM)
▪ Each cell stores a bit with a four or six-transistor circuit.
▪ Retains value indefinitely, as long as it is kept powered.
▪ Relatively insensitive to electrical noise (EMI), radiation, etc.
▪ Faster and more expensive than DRAM.
 Dynamic RAM (DRAM)
▪ Each cell stores bit with a capacitor. One transistor is used for access
▪ Value must be refreshed every 10-100 ms.
▪ More sensitive to disturbances (EMI, radiation,…) than SRAM.
▪ Slower and cheaper than SRAM.
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SRAM vs DRAM Summary

Trans. Access Needs Needs

per bit time refresh? EDC? Cost Applications

SRAM 4 or 6 1X No Maybe 100x Cache memories

DRAM 1 10X Yes Yes 1X Main memories,

frame buffers

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Conventional DRAM Organization

 d x w DRAM:
▪ dw total bits organized as d supercells of size w bits
16 x 8 DRAM chip
cols
0 1 2 3
2 bits 0
/
addr
1
rows
Memory supercell
2
controller (2,1)
(to/from CPU)
3
8 bits
/
data

Internal row buffer

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Reading DRAM Supercell (2,1)

Step 1(a): Row access strobe (RAS) selects row 2.
Step 1(b): Row 2 copied from DRAM array to row buffer.

16 x 8 DRAM chip
Cols
0 1 2 3
RAS = 2
2
/ 0
addr
1
Rows
Memory
controller 2

8 3
/
data

Internal row buffer

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Reading DRAM Supercell (2,1)

Step 2(a): Column access strobe (CAS) selects column 1.
Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually
back to the CPU.
16 x 8 DRAM chip
Cols
0 1 2 3
CAS = 1
2
/ 0
addr
To CPU 1
Rows
Memory
controller 2

supercell 3
8
(2,1) /
data

supercell
Internal row buffer
(2,1)
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Memory Modules
addr (row = i, col = j)
: supercell (i,j)
DRAM 0

64 MB
memory module
DRAM 7
consisting of
eight 8Mx8 DRAMs

bits bits bits bits bits bits bits bits

56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Memory
controller
64-bit doubleword at main memory address A

64-bit doubleword

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Enhanced DRAMs
 Basic DRAM cell has not changed since its invention in 1966.
▪ Commercialized by Intel in 1970.
 DRAM cores with better interface logic and faster I/O :
▪ Synchronous DRAM (SDRAM)
▪ Uses a conventional clock signal instead of asynchronous control
▪ Allows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS)

▪ Double data-rate synchronous DRAM (DDR SDRAM)

▪ Double edge clocking sends two bits per cycle per pin
▪ Different types distinguished by size of small prefetch buffer:
– DDR (2 bits), DDR2 (4 bits), DDR4 (8 bits)
▪ By 2010, standard for most server and desktop systems
▪ Intel Core i7 supports only DDR3 SDRAM

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Nonvolatile Memories
 DRAM and SRAM are volatile memories
▪ Lose information if powered off.
 Nonvolatile memories retain value even if powered off
▪ Read-only memory (ROM): programmed during production
▪ Programmable ROM (PROM): can be programmed once
▪ Eraseable PROM (EPROM): can be bulk erased (UV, X-Ray)
▪ Electrically eraseable PROM (EEPROM): electronic erase capability
▪ Flash memory: EEPROMs with partial (sector) erase capability
▪ Wears out after about 100,000 erasings.
 Uses for Nonvolatile Memories
▪ Firmware programs stored in a ROM (BIOS, controllers for disks,
network cards, graphics accelerators, security subsystems,…)
▪ Solid state disks (replace rotating disks in thumb drives, smart
phones, mp3 players, tablets, laptops,…)
▪ Disk caches
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Traditional Bus Structure Connecting

CPU and Memory
 A bus is a collection of parallel wires that carry address,
data, and control signals.
 Buses are typically shared by multiple devices.

CPU chip

Register file

ALU

System bus Memory bus

I/O Main
Bus interface
bridge memory

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Memory Read Transaction (1)

 CPU places address A on the memory bus.

Register file Load operation: movl A, %eax

ALU
%eax

Main memory
I/O bridge 0
A
Bus interface x A

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Memory Read Transaction (2)

 Main memory reads A from the memory bus, retrieves
word x, and places it on the bus.
Register file
Load operation: movl A, %eax

ALU
%eax

Main memory
I/O bridge x 0

Bus interface x A

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Memory Read Transaction (3)

 CPU read word x from the bus and copies it into register
%eax.
Register file Load operation: movl A, %eax

ALU
%eax x

Main memory
I/O bridge 0

Bus interface x A

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Memory Write Transaction (1)

 CPU places address A on bus. Main memory reads it and
waits for the corresponding data word to arrive.
Register file Store operation: movl %eax, A

ALU
%eax y

Main memory
I/O bridge 0
A
Bus interface A

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Memory Write Transaction (2)

 CPU places data word y on the bus.

Register file Store operation: movl %eax, A

ALU
%eax y

Main memory
I/O bridge 0
y
Bus interface A

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Memory Write Transaction (3)

 Main memory reads data word y from the bus and stores
it at address A.
register file
Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0

bus interface y A

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What’s Inside A Disk Drive?

Arm Spindle
Platters

Actuator

Electronics
(including a
processor
SCSI and memory!)
connector
Image courtesy of Seagate Technology
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Disk Geometry
 Disks consist of platters, each with two surfaces.
 Each surface consists of concentric rings called tracks.
 Each track consists of sectors separated by gaps.

Tracks
Surface
Track k Gaps

Spindle

Sectors
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Disk Geometry (Muliple-Platter View)

 Aligned tracks form a cylinder.
Cylinder k

Surface 0
Platter 0
Surface 1
Surface 2
Platter 1
Surface 3
Surface 4
Platter 2
Surface 5

Spindle

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Disk Capacity
 Capacity: maximum number of bits that can be stored.
▪ Vendors express capacity in units of gigabytes (GB), where
1 GB = 109 Bytes (Lawsuit pending! Claims deceptive advertising).
 Capacity is determined by these technology factors:
▪ Recording density (bits/in): number of bits that can be squeezed
into a 1 inch segment of a track.
▪ Track density (tracks/in): number of tracks that can be squeezed
into a 1 inch radial segment.
▪ Areal density (bits/in2): product of recording and track density.
 Modern disks partition tracks into disjoint subsets called
recording zones
▪ Each track in a zone has the same number of sectors, determined
by the circumference of innermost track.
▪ Each zone has a different number of sectors/track
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Computing Disk Capacity

Capacity = (# bytes/sector) x (avg. # sectors/track) x
(# tracks/surface) x (# surfaces/platter) x
(# platters/disk)
Example:
▪ 512 bytes/sector
▪ 300 sectors/track (on average)
▪ 20,000 tracks/surface
▪ 2 surfaces/platter
▪ 5 platters/disk

Capacity = 512 x 300 x 20000 x 2 x 5

= 30,720,000,000
= 30.72 GB

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Disk Operation (Single-Platter View)

The disk surface

The read/write head
spins at a fixed
is attached to the end
rotational rate
of the arm and flies over
the disk surface on
a thin cushion of air.

spindle
spindle
spindle
spindle

By moving radially, the arm can

position the read/write head over
any track.

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Disk Operation (Multi-Platter View)

Read/write heads
move in unison
from cylinder to cylinder

Arm

Spindle

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Disk Structure - top view of single platter

Surface organized into tracks

Tracks divided into sectors

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Disk Access

Head in position above a track

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Disk Access

Rotation is counter-clockwise

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Disk Access – Read

About to read blue sector

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Disk Access – Read

After BLUE read

After reading blue sector

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Disk Access – Read

After BLUE read

Red request scheduled next

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Disk Access – Seek

After BLUE read Seek for RED

Seek to red’s track

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Disk Access – Rotational Latency

After BLUE read Seek for RED Rotational latency

Wait for red sector to rotate around

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Disk Access – Read

After BLUE read Seek for RED Rotational latency After RED read

Complete read of red

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Disk Access – Service Time Components

After BLUE read Seek for RED Rotational latency After RED read

Data transfer Seek Rotational Data transfer

latency

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Disk Access Time

 Average time to access some target sector approximated by :
▪ Taccess = Tavg seek + Tavg rotation + Tavg transfer
 Seek time (Tavg seek)
▪ Time to position heads over cylinder containing target sector.
▪ Typical Tavg seek is 3—9 ms
 Rotational latency (Tavg rotation)
▪ Time waiting for first bit of target sector to pass under r/w head.
▪ Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min
▪ Typical Tavg rotation = 7200 RPMs
 Transfer time (Tavg transfer)
▪ Time to read the bits in the target sector.
▪ Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

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Disk Access Time Example

 Given:
▪ Rotational rate = 7,200 RPM
▪ Average seek time = 9 ms.
▪ Avg # sectors/track = 400.
 Derived:
▪ Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms.
▪ Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms
▪ Taccess = 9 ms + 4 ms + 0.02 ms
 Important points:
▪ Access time dominated by seek time and rotational latency.
▪ First bit in a sector is the most expensive, the rest are free.
▪ SRAM access time is about 4 ns/doubleword, DRAM about 60 ns
▪ Disk is about 40,000 times slower than SRAM,
▪ 2,500 times slower then DRAM.
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Logical Disk Blocks

 Modern disks present a simpler abstract view of the
complex sector geometry:
▪ The set of available sectors is modeled as a sequence of b-sized
logical blocks (0, 1, 2, ...)
 Mapping between logical blocks and actual (physical)
sectors
▪ Maintained by hardware/firmware device called disk controller.
▪ Converts requests for logical blocks into (surface,track,sector)
triples.
 Allows controller to set aside spare cylinders for each
zone.
▪ Accounts for the difference in “formatted capacity” and “maximum
capacity”.

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I/O Bus
CPU chip
Register file

ALU
System bus Memory bus

I/O Main
Bus interface
bridge memory

I/O bus Expansion slots for

other devices such
USB Graphics Disk as network adapters.
controller adapter controller

Mouse Keyboard Monitor

Disk
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Reading a Disk Sector (1)

CPU chip
Register file
CPU initiates a disk read by writing a
command, logical block number, and
ALU destination memory address to a port
(address) associated with disk controller.

Main
Bus interface
memory

I/O bus

USB Graphics Disk

controller adapter controller

mouse keyboard Monitor

Disk
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Reading a Disk Sector (2)

CPU chip
Register file Disk controller reads the sector and
performs a direct memory access
ALU
(DMA) transfer into main memory.

Main
Bus interface
memory

I/O bus

USB Graphics Disk

controller adapter controller

Mouse Keyboard Monitor

Disk
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Reading a Disk Sector (3)

CPU chip
When the DMA transfer completes,
Register file
the disk controller notifies the CPU
ALU with an interrupt (i.e., asserts a
special “interrupt” pin on the CPU)

Main
Bus interface
memory

I/O bus

USB Graphics Disk

controller adapter controller

Mouse Keyboard Monitor

Disk
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Solid State Disks (SSDs)

I/O bus

Requests to read and

write logical disk blocks
Solid State Disk (SSD)
Flash
translation layer
Flash memory
Block 0 Block B-1
Page 0 Page 1 … Page P-1 … Page 0 Page 1 … Page P-1

 Pages: 512KB to 4KB, Blocks: 32 to 128 pages

 Data read/written in units of pages.
 Page can be written only after its block has been erased
 A block wears out after 100,000 repeated writes.
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SSD Performance Characteristics

Sequential read tput 250 MB/s Sequential write tput 170 MB/s
Random read tput 140 MB/s Random write tput 14 MB/s
Rand read access 30 us Random write access 300 us

 Why are random writes so slow?

▪ Erasing a block is slow (around 1 ms)
▪ Write to a page triggers a copy of all useful pages in the block
▪ Find an used block (new block) and erase it
▪ Write the page into the new block
▪ Copy other pages from old block to the new block

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SSD Tradeoffs vs Rotating Disks

 Advantages
▪ No moving parts → faster, less power, more rugged

 Disadvantages
▪ Have the potential to wear out
▪ Mitigated by “wear leveling logic” in flash translation layer
▪ E.g. Intel X25 guarantees 1 petabyte (1015 bytes) of random
writes before they wear out
▪ In 2010, about 100 times more expensive per byte

 Applications
▪ MP3 players, smart phones, laptops
▪ Beginning to appear in desktops and servers

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Storage Trends
SRAM
Metric 1980 1985 1990 1995 2000 2005 2010 2010:1980

$/MB 19,200 2,900 320 256 100 75 60 320

access (ns) 300 150 35 15 3 2 1.5 200

DRAM
Metric 1980 1985 1990 1995 2000 2005 2010 2010:1980

$/MB 8,000 880 100 30 1 0.1 0.06 130,000

access (ns) 375 200 100 70 60 50 40 9
typical size (MB) 0.064 0.256 4 16 64 2,000 8,000 125,000

Disk
Metric 1980 1985 1990 1995 2000 2005 2010 2010:1980

$/MB 500 100 8 0.30 0.01 0.005 0.0003 1,600,000

access (ms) 87 75 28 10 8 4 3 29
typical size (MB) 1 10 160 1,000 20,000 160,000 1,500,000 1,500,000
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CPU Clock Rates Inflection point in computer history

when designers hit the “Power Wall”

1980 1990 1995 2000 2003 2005 2010 2010:1980

CPU 8080 386 Pentium P-III P-4 Core 2 Core i7 ---

Clock
rate (MHz) 1 20 150 600 3300 2000 2500 2500

Cycle
time (ns) 1000 50 6 1.6 0.3 0.50 0.4 2500

Cores 1 1 1 1 1 2 4 4

Effective
cycle 1000 50 6 1.6 0.3 0.25 0.1 10,000
time (ns)

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The CPU-Memory Gap

The gap between DRAM, disk, and CPU speeds.
100,000,000.0
Disk
10,000,000.0

1,000,000.0
SSD
100,000.0
Disk seek time
10,000.0
Flash SSD access time
DRAM access time
1,000.0
ns

SRAM access time

100.0
DRAM CPU cycle time
Effective CPU cycle time

10.0

1.0

0.1 CPU
0.0
1980 1985 1990 1995 2000 2003 2005 2010
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Locality to the Rescue!

The key to bridging this CPU-Memory gap is a fundamental

property of computer programs known as locality

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Today
 Storage technologies and trends
 Locality of reference
 Caching in the memory hierarchy

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Locality
 Principle of Locality: Programs tend to use data and
instructions with addresses near or equal to those they
have used recently

 Temporal locality:
▪ Recently referenced items are likely
to be referenced again in the near future

 Spatial locality:
▪ Items with nearby addresses tend
to be referenced close together in time

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Locality Example
sum = 0;
for (i = 0; i < n; i++)
sum += a[i];
return sum;

 Data references
▪ Reference array elements in succession
(stride-1 reference pattern). Spatial locality
▪ Reference variable sum each iteration. Temporal locality
 Instruction references
▪ Reference instructions in sequence. Spatial locality
▪ Cycle through loop repeatedly. Temporal locality

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Qualitative Estimates of Locality

 Claim: Being able to look at code and get a qualitative
sense of its locality is a key skill for a professional
programmer.

 Question: Does this function have good locality with

respect to array a?

int sum_array_rows(int a[M][N])

{
int i, j, sum = 0;

for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
sum += a[i][j];
return sum;
}
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Locality Example
 Question: Does this function have good locality with
respect to array a?

int sum_array_cols(int a[M][N])

{
int i, j, sum = 0;

for (j = 0; j < N; j++)

for (i = 0; i < M; i++)
sum += a[i][j];
return sum;
}

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Memory Hierarchies
 Some fundamental and enduring properties of hardware
and software:
▪ Fast storage technologies cost more per byte, have less capacity,
and require more power (heat!).
▪ The gap between CPU and main memory speed is widening.
▪ Well-written programs tend to exhibit good locality.

 These fundamental properties complement each other

beautifully.

 They suggest an approach for organizing memory and

storage systems known as a memory hierarchy.

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Today
 Storage technologies and trends
 Locality of reference
 Caching in the memory hierarchy

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An Example Memory Hierarchy

L0: CPU registers hold words retrieved
Registers from L1 cache

L1: L1 cache
Smaller, (SRAM) L1 cache holds cache lines retrieved
from L2 cache
faster,
costlier L2:
L2 cache
per byte L2 cache holds cache lines
(SRAM)
retrieved from main memory
L3:
Larger, Main memory
(DRAM) Main memory holds disk blocks
slower, retrieved from local disks
cheaper
per byte L4: Local secondary storage Local disks hold files
(local disks) retrieved from disks on
remote network servers

Remote secondary storage

L5: (tapes, distributed file systems, Web servers)

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Caches
 Cache: A smaller, faster storage device that acts as a staging
area for a subset of the data in a larger, slower device.
 Fundamental idea of a memory hierarchy:
▪ For each k, the faster, smaller device at level k serves as a cache for the
larger, slower device at level k+1.
 Why do memory hierarchies work?
▪ Because of locality, programs tend to access the data at level k more
often than they access the data at level k+1.
▪ Thus, the storage at level k+1 can be slower, and thus larger and
cheaper per bit.
 Big Idea: The memory hierarchy creates a large pool of
storage that costs as much as the cheap storage near the
bottom, but that serves data to programs at the rate of the
fast storage near the top.
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General Cache Concepts

Smaller, faster, more expensive

Cache 8
4 9 14
10 3 memory caches a subset of
the blocks

Data is copied in block-sized

10
4 transfer units

Larger, slower, cheaper memory

Memory 0 1 2 3 viewed as partitioned into “blocks”

4 5 6 7
8 9 10 11
12 13 14 15

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General Cache Concepts: Hit

Request: 14 Data in block b is needed

Block b is in cache:
Cache 8 9 14 3
Hit!

Memory 0 1 2 3
4 5 6 7
8 9 10 11
12 13 14 15

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General Cache Concepts: Miss

Request: 12 Data in block b is needed

Block b is not in cache:

Cache 8 9
12 14 3
Miss!

Block b is fetched from

12 Request: 12
memory

Block b is stored in cache

Memory 0 1 2 3 • Placement policy:
4 5 6 7 determines where b goes
• Replacement policy:
8 9 10 11
determines which block
12 13 14 15 gets evicted (victim)

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General Caching Concepts:

Types of Cache Misses
 Cold (compulsory) miss
▪ Cold misses occur because the cache is empty.
 Conflict miss
▪ Most caches limit blocks at level k+1 to a small subset (sometimes a
singleton) of the block positions at level k.
▪ E.g. Block i at level k+1 must be placed in block (i mod 4) at level k.
▪ Conflict misses occur when the level k cache is large enough, but multiple
data objects all map to the same level k block.
▪ E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every time.

 Capacity miss
▪ Occurs when the set of active cache blocks (working set) is larger than
the cache.

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Examples of Caching in the Hierarchy

Cache Type What is Cached? Where is it Cached? Latency (cycles) Managed By

Registers 4-8 bytes words CPU core 0 Compiler

TLB Address translations On-Chip TLB 0 Hardware

L1 cache 64-bytes block On-Chip L1 1 Hardware

L2 cache 64-bytes block On/Off-Chip L2 10 Hardware
Virtual Memory 4-KB page Main memory 100 Hardware + OS
Buffer cache Parts of files Main memory 100 OS
Disk cache Disk sectors Disk controller 100,000 Disk firmware
Network buffer Parts of files Local disk 10,000,000 AFS/NFS client
cache
Browser cache Web pages Local disk 10,000,000 Web browser

Web cache Web pages Remote server disks 1,000,000,000 Web proxy
server
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Summary
 The speed gap between CPU, memory and mass storage
continues to widen.

 Well-written programs exhibit a property called locality.

 Memory hierarchies based on caching close the gap by

exploiting locality.

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Cache Memories

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Today
 Cache memory organization and operation
 Performance impact of caches
▪ The memory mountain
▪ Rearranging loops to improve spatial locality
▪ Using blocking to improve temporal locality

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Cache Memories
 Cache memories are small, fast SRAM-based memories
managed automatically in hardware.
▪ Hold frequently accessed blocks of main memory
 CPU looks first for data in caches (e.g., L1, L2, and L3),
then in main memory.
 Typical system structure:
CPU chip
Register file
Cache
ALU
memories
System bus Memory bus

I/O Main
Bus interface
bridge memory

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General Cache Organization (S, E, B)

E = 2e lines per set

set
line

S = 2s sets

Cache size:
v tag 0 1 2 B-1 C = S x E x B data bytes
valid bit
B = 2b bytes per cache block (the data)
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• Locate set
Cache Read • Check if any line in set
has matching tag
E = 2e lines per set • Yes + line valid: hit
• Locate data starting
at offset

Address of word:
t bits s bits b bits

S = 2s sets
tag set block
index offset

data begins at this offset

v tag 0 1 2 B-1

valid bit
B = 2b bytes per cache block (the data)
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What about writes?

 Multiple copies of data exist:
▪ L1, L2, Main Memory, Disk
 What to do on a write-hit?
▪ Write-through (write immediately to memory)
▪ Write-back (defer write to memory until replacement of line)
▪ Need a dirty bit (line different from memory or not)
 What to do on a write-miss?
▪ Write-allocate (load into cache, update line in cache)
▪Good if more writes to the location follow
▪ No-write-allocate (writes immediately to memory)
 Typical
▪ Write-through + No-write-allocate
▪ Write-back + Write-allocate

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Intel Core i7 Cache Hierarchy

Processor package
Core 0 Core 3 L1 i-cache and d-cache:
32 KB, 8-way,
Regs Regs Access: 4 cycles

L1 L1 L1 L1 L2 unified cache:
d-cache i-cache
… d-cache i-cache 256 KB, 8-way,
Access: 11 cycles

L2 unified cache L2 unified cache L3 unified cache:

8 MB, 16-way,
Access: 30-40 cycles
L3 unified cache
(shared by all cores) Block size: 64 bytes for
all caches.

Main memory
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Knights Landing (KNL): 2nd Generation

Intel® Xeon Phi™ Processor (2016)

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Intel Xeon Scalable processors

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Cache Performance Metrics

 Miss Rate
▪ Fraction of memory references not found in cache (misses / accesses)
= 1 – hit rate
▪ Typical numbers (in percentages):
▪ 3-10% for L1
▪ can be quite small (e.g., < 1%) for L2, depending on size, etc.
 Hit Time
▪ Time to deliver a line in the cache to the processor
▪ includes time to determine whether the line is in the cache
▪ Typical numbers:
▪ 1-2 clock cycle for L1
▪ 5-20 clock cycles for L2
 Miss Penalty
▪ Additional time required because of a miss
▪ typically 50-200 cycles for main memory (Trend: increasing!)

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Lets think about those numbers

 Huge difference between a hit and a miss
▪ Could be 100x, if just L1 and main memory

 Would you believe 99% hits is twice as good as 97%?

▪ Consider:
cache hit time of 1 cycle
miss penalty of 100 cycles

▪ Average access time:

97% hits: 1 cycle + 0.03 * 100 cycles = 4 cycles
99% hits: 1 cycle + 0.01 * 100 cycles = 2 cycles

 This is why “miss rate” is used instead of “hit rate”

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Writing Cache Friendly Code

 Make the common case go fast
▪ Focus on the inner loops of the core functions

 Minimize the misses in the inner loops

▪ Repeated references to variables are good (temporal locality)
▪ Stride-1 reference patterns are good (spatial locality)

Key idea: Our qualitative notion of locality is quantified

through our understanding of cache memories.

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Concluding Observations
 Programmer can optimize for cache performance
▪ How data structures are organized
▪ How data are accessed
▪ Nested loop structure
▪ Blocking is a general technique
 All systems favor “cache friendly code”
▪ Getting absolute optimum performance is very platform specific
▪Cache sizes, line sizes, associativities, etc.
▪ Can get most of the advantage with generic code
▪ Keep working set reasonably small (temporal locality)
▪ Use small strides (spatial locality)

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