Parallel Operation Of Semiconductor Switches

Application Note June 1993 AN-7513

In uninterruptable power supplies demands for current han- (Figure 1). The dynamic area is only a fraction of the total
/Title dling capability to meet load current In uninterruptable power waveform, but it is by far the most important when it comes
supplies demands for current handling capability to meet to parallel operation.
AN75 load current requirements plus margins for overload and reli-
3) In power electronics, there are three different load types;
ability purposes often exceed the capability of the largest
resistive, capacitive, and inductive. The resulting waveforms
Sub- semiconductor device type considered and paralleling may
are sufficiently different to require either different switching
ect become an attractive alternative. All switching power semi-
devices or the circuit designer may have to change the
conductors starting with SCR’s [1], bipolar transistors [2-4]
Paral- darlingtons [5] and field effect transistors [6-10], have been
switching circuit to meet the different requirements, espe-
el cially when devices are operated in parallel.
successfully paralleled, but proper precaution had to be
pera- taken. We will review some of these methods, describe the Off-State
characteristics of the insulated gate transistors, and show
ion Of The off-state is probably the least demanding state in paral-
the proper methods to operate this relatively new family of
emi- devices in parallel. lel operation of semiconductor devices. As long as leakage
on- current is low, even differences of more than 100% would not
All semiconductor circuits using parallel connected devices create any difficulties.
uctor to switch a higher load current can easily be analyzed by
witch using Kirchoff’s law. As long as all voltage drops in the paral- On-State
lel branches are equal, the currents through the branches The on-state is again a relatively uncritical and uneventful
are equal. period (Figure 2). Most devices in switching applications are
)
This sounds sensible and logical, but as soon as we con- overdriven and differences in gain or transconductance do
Autho not translate into proportional output current.
sider the different stages every switching device has to
() assume and we consider the parameters of each switching Even if a bipolar device takes a larger share of the total current,
Key- device which guarantees equal voltage drops in the the rapid fall-off in gain and the increase in V SAT as it takes the
ords branches over the required temperature range and over the higher share will prevent disaster. Thermal runaway in bipolar
Inter- duration of the switching cycle, complications begin to applications is not as frequent as we may believe [2-4].
appear.
il For bipolar devices, the parameter having a clear negative
orpo- At first glance, each switching device has only two functional temperature coefficient is VBE. VCE(SAT), on the other hand,
states, an “off- state” and an “on-state”. But by closer exami- can have positive or negative temperature coefficient depend-
ation, nation, we have to consider how we get from “off” to “on” and ing on the device type (npn or pnp) and operating point.
emi- back to “off”, the “dynamic” area of the switching waveform
on-
uctor,
va-
DYNAMIC STATIC DYNAMIC
anche STATIC
nergy DYNAMIC DYNAMIC
AREA STATIC AREA AREA STATIC AREA
ated, (TURN ON) ON TIME (TURN ON) ON TIME
witch
ng CONTROL SIGNAL CONTROL

ower SIGNAL

up- CURRENT SWITCHING

WAVEFORM
lie
OUTPUT
, TURN ON “OFF” CURRENT
DELAY TIME OFF
ower “ON”
DELAY
(STORAGE
witch TURN ON
(RISE TIME)
TIME) TURN OFF
(FALL TIME)
ng
FIGURE 1. SWITCHING WAVEFORM DEFINITIONS

©2002 Fairchild Semiconductor Corporation Application Note 7513 Rev. A1

 Application Note 7513

The ease of paralleling of power FETs has been pointed out Rise Time
by many authors [6-9], and has been demonstrated in many
Rise time is an interesting part of the switching waveform
applications, although each application requires analysis of
(Figure 4). The device operates in an analog domain,
both dynamic and static sharing.
although for a very short time, but nevertheless, analog.
ON TIME
IOUT
• GAIN 90%
• TRANSCONDUCTANCE
• TEMPERATURE
• DC CURRENT GAIN • RISE TIME OF
• SATURATION VOLTAGE BIPOLAR • DRIVING SIGNAL
• BASE EMITTER • INDUCTOR
VOLTAGE
• EMITTER RESISTORS
FET
• TRANSCONDUCTANCE
• RDS(ON)
10%

tR
FIGURE 2. ON TIME OF SWITCHING WAVEFORM AND
CONTROLLING PARAMETERS

Turn-On Delay Time

Turn-on delay time is the time from where the control signal FIGURE 4. RISE TIME OF LOUT WAVEFORMS AND PARAMETERS
is applied, reaches 10% amplitude, to the point where the INFLUENCING IT
switched current rises to the 10% amplitude (Figure 3). Again, transconductance and junction temperature become
IOUT important considerations, but junction temperature differ-
ences as a result of rise time differences are relatively small.
CONTROLLED BY:
• TEMPERATURE tD(ON) Inductors inserted into the emitter lead on bipolars, source
• RISE TIME OF CURRENT lead on FET’s or cathode lead on diodes, can be extremely
CONTROL WAVEFORM effective [3]. All differences in turn-on delay and rise time
SIGNAL become visible at thin part of the waveform. Differences
• DEVICE TYPE
which may exist, although small, require the evaluation of the
forward biased safe operating area (FBSOA).
10% In most cases, transistors have almost rectangular FBSOA
for the short durations they remain in the analog domain of
the turn-on period. Problems seldom exist, but precautions
CONTROL SIGNAL should not be ignored either.
90% Note that the device with the shortest turn-on delay and the
shortest rise-time will take most of the current. Most transis-
tR tors have a negative temperature coefficient of input voltage
and Miller effect feedback which can cause current begging
if power dissipation is high during turn on.
FIGURE 3. DEFINITION OF TURN-ON, DELAY TIME, tD(ON)
AND CONTROLLING PARAMETERS Turn-Off Delay Time (Storage Time)
Fortunately, differences is turn-on delay are relatively small. Turn-off delay time is the prelude to the most important part
Although this delay is significant in large-area SCR’s, but it is of the switching waveform, especially on bipolar devices
much less a problem with bipolars or power FET’s. It is less (Figure 5). On bipolar devices, it is important to remove the
important when switching inductive loads, but should be stored charge as fast as possible, which may require more
monitored when devices to be paralleled switch resistive expensive drive circuitry. Especially on large power darling-
load, discharge capacitor or have to carry the recovery cur- tons, negative bias or baker clamps result in significant
rent of a diode. reduction of storage time and improve parallel operations.
The transition time of the base current signal from positive to
Needless to say, it is desirable to have small turn-on delays
negative (npn device) is important in the removal rate of the
for parallel operation. To reduce deltas in tD(ON), it is advis-
stored charge.
able to drive devices with fast rising control signals and use
devices from the same mask design. The same device type
number does not guarantee that they are made from the
same mask design. Therefore, devices from different manu-
facturers should not be intermixed.

©2002 Fairchild Semiconductor Corporation Application Note 7513 Rev. A1

 Application Note 7513

IGT Structure and Operation

The basic device structure is illustrated by the unit cell cross
90% section of Figure 7. Like the MOSFET, the IGT consists of
BIPOLAR CONTROLLED
BY: many individual cells connected in parallel. Processing of the
• STORED CHARGE IGT is similar to the vertical D-MOS technology used in
• STATE OF MOSFETs. In the steady state, the n-channel IGT may be
SATURATION modeled as a bipolar pnp driven by an n-channel MOSFET.
tD(OFF)
• NEGATIVE BIAS
• TEMPERATURE
The MOSFET supplies base current to the pnp thus the
MOSFETs gate voltage controls the total current.
POWER FET
CONTROL SIGNAL HOW FAST CAN
C’s BE DISCHARGED
90%
EMITTER
O-LINE

NEGATIVE
BIAS

TRANSITION POLYSILICON
TIME GATE

n+ n+ p- n+ n+
FIGURE 5. TURN-OFF WAVEFORM AND PARAMETERS
INFLUENCING IT

Fall Time WELL

p+ p+ CHANNEL p+

Parameters which reduce storage time will also reduce fall J1

time (Figure 6). For paralleled devices, differences in turn-off RMOD
delay or storage time will have a noticeable effect on fall n- EPITAXIAL LAYER
time.
When inductive loads are turned off, the reverse biased safe
operating area (RBSOA) must be considered on bipolar n+ BUFFER LAYER
devices. Hot spot formation [11] which results in sudden J2
p+ SUBSTRATE
reduction of the VBE and further increase in IB could result in
permanent damage.

BIPOLAR:
STORED CHARGE REMOVAL COLLECTOR
tFALL RATE OF CONTROL SIGNAL
NEGATIVE BIAS (TRANSITION
UNIT CELL STRUCTURE
TIME) SATURATION VOLTAGE
TEMPERATURE.
90%
C

RMOD STEADY
PNP STATE
FET: EQUIV.
CIRCUIT
RDS(ON) CAPACITANCE G NMOS
OF FET DISCHARGE
IMPEDANCE (TIME 10%
CONSTANT)

FIGURE 6. FALL TIME AND INFLUENCING PARAMETERS

FIGURE 7. UNIT CELL CROSS SECTION AND STEADY STATE
The Insulated Gate Transistor EQUIVALENT CIRCUIT OF IGT TRANSISTOR.

The insulated gate transistor (IGT) combines the high input In normal operation, the emitter is grounded, the collector
impedance, voltage controlled turn on/turn off capabilities of biased positive and with no gate-emitter voltage applied; J1
power MOSFETs and the low on-state conduction losses of is reverse biased. The device is in the forward blocking
bipolar transistors, making it an ideal device for many power mode. When a positive voltage is applied to the gate with
electronics switching control applications. respect to the emitter, an inversion channel is formed under
the gate and MOSFET current flows from the n+ source
region into the n-epi-layer to become the base current for the
pnp. Junction J2 becomes forward biased and the device
enters the conduction state. Holes are injected from the bot-

©2002 Fairchild Semiconductor Corporation Application Note 7513 Rev. A1

 Application Note 7513

tom percent region into the n-epi-layer. The injected minority References
carrier density is 100 to 1000 times higher that the doping
level of the n-type epi-region. This conductivity modulation [1] SCR Manual, 6th Edition, General Electric Semiconduc-
allows the IGT to operate at a forward conduction current tor Department, Auburn, New York, Chapter 6.2, Paral-
density 20 times that of an equivalent MOSFET. It is prima- lel Operation of SCR’s.
rily in the thick epi, high-voltage devices where conductivity [2] Use Equations to Parallel Transistors. Otto R. Buhler,
modulation has its major impact to reduce on-resistance. IBM, Boulder, Colorado, Electronics Design 4, February
The typical output characteristics and the symbol of the IGT 15,1977.
are shown in Figure 8. Like on MOSFETs, the output charac- [3] Parallel Operations of Power Transistors in Switching
teristics curves are generated by plotting collector emitter Applications. Sebald R. Korn, General Electric Com-
currents, collector emitter voltage. Unlike the MOSFET, there pany, Application Note 660.39, 10/79.
is an offset voltage generated by the collector emitter junc-
tion of the npn-transistor. However, once this offset is over- [4] Paralleling Switching Bipolar Power Transistors, J. T.
come, the effective on-resistance in the saturation region is Hutchinson, PCIM, September 1985.
much lower for the IGT than for the MOSET.
[5] Paralleling High Current Darlingtons, Warren Schulz,
Motorola, Phoenix, Arizona, Powertechnics Magazine,
VGE = 16V
December 1985.
60
T = +25oC VGE = 14V [6] Paralleling Power MOSFET’s in Switching Applications,
MAX PULSE WIDTH = 300µs
50 by Kim Gauen, Motorola, Application Note AN-918,
MAX DUTY CYCLE 2%
VGE = 12V 1984.
COLLECTOR CURRENT (A)

20A, 500V DEVICE

40 COLLECTOR [7] Parallel Operation of MOSFET’s in DC-DC Converters,
VGE = 10V
Rudy Severns, Siliconix, Powertechnics Magazine,
30 June 1985.
GATE
[8] A Chopper for Motor Speed Control Using Parallel Con-
20 nected Power HEXFET’sTM, by S. Clemente, B. Pelly,
EMITTER VGE = 8V
IR.
10 [9] MOS Power Applications Handbook, Siliconix, Inc.,
VGE = 6V
Chapter 5.3, Parallel Operation of Power MOSFET’s
0 (TA84-5).
0 1.0 2.0 3.0 4.0
[10] Motor Control Applications of Second Generation
IGTTM Power Transistors, by Donald J Maclntyre, Jr.,
FIGURE 8. OUTPUT CHARACTERISTICS AND CIRCUIT Application Note 200.95.
SYMBOL FOR N-CHANNEL IGT TRANSISTOR
[11] Non-destructive Forward Biased Second Breakdown
Testing, No. 78-3, by Sebald Korn, Internal General
Electric Report.

©2002 Fairchild Semiconductor Corporation Application Note 7513 Rev. A1

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Rev. H5