Order this document by MC34151/D



  
 
The MC34151/MC33151 are dual inverting high speed drivers specifically HIGH SPEED
designed for applications that require low current digital circuitry to drive
large capacitive loads with high slew rates. These devices feature low input DUAL MOSFET DRIVERS
current making them CMOS and LSTTL logic compatible, input hysteresis for
fast output switching that is independent of input transition time, and two high SEMICONDUCTOR
current totem pole outputs ideally suited for driving power MOSFETs. Also TECHNICAL DATA
included is an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and motor
controllers. P SUFFIX
These devices are available in dual–in–line and surface mount packages. PLASTIC PACKAGE
• Two Independent Channels with 1.5 A Totem Pole Output 8
CASE 626

• Output Rise and Fall Times of 15 ns with 1000 pF Load 1

• CMOS/LSTTL Compatible Inputs with Hysteresis

• Undervoltage Lockout with Hysteresis
• Low Standby Current D SUFFIX
• Efficient High Frequency Operation PLASTIC PACKAGE
CASE 751
•
8
Enhanced System Performance with Common Switching Regulator 1 (SO–8)
Control ICs
• Pin Out Equivalent to DS0026 and MMH0026

PIN CONNECTIONS

N.C. 1 8 N.C.

Representative Block Diagram

Logic Input A 2 7 Drive Output A

VCC
6 Gnd 3 6 VCC

+ Logic Input B 4 5 Drive Output B

+ –
+ +
5.7V (Top View)
+
Drive Output A
Logic Input A
7
2
100k

+
ORDERING INFORMATION
+
Drive Output B Operating
Logic Input B Device Temperature Range Package
5
100k

4
MC34151D SO–8
TA = 0° to +70°C
MC34151P Plastic DIP
MC33151D SO–8
3 TA = – 40° to +85°C
Gnd MC33151P Plastic DIP

 Motorola, Inc. 1996 Rev 0

MOTOROLA ANALOG IC DEVICE DATA 1
 MC34151 MC33151
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 20 V
Logic Inputs (Note 1) Vin –0.3 to VCC V
Drive Outputs (Note 2) A
Totem Pole Sink or Source Current IO 1.5
Diode Clamp Current (Drive Output to VCC) IO(clamp) 1.0
Power Dissipation and Thermal Characteristics
D Suffix SO–8 Package Case 751
Maximum Power Dissipation @ TA = 50°C PD 0.56 W
Thermal Resistance, Junction–to–Air RθJA 180 °C/W
P Suffix 8–Pin Package Case 626
Maximum Power Dissipation @ TA = 50°C PD 1.0 W
Thermal Resistance, Junction–to–Air RθJA 100 °C/W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature TA °C
MC34151 0 to +70
MC33151 –40 to +85
Storage Temperature Range Tstg –65 to +150 °C

ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA is the only operating ambient
temperature range that applies [Note 3], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
LOGIC INPUTS
Input Threshold Voltage – High State Logic 1 VIH 2.6 1.75 – V
Input Threshold Voltage – Low State Logic 0 VIL – 1.58 0.8

Input Current – High State (VIH = 2.6 V) IIH – 200 500 µA

Input Current – Low State (VIL = 0.8 V) IIL – 20 100

DRIVE OUTPUT
Output Voltage – Low State (ISink = 10 mA) VOL – 0.8 1.2 V
Output Voltage – Low State (ISink = 50 mA) – 1.1 1.5
Output Voltage – Low State (ISink = 400 mA) – 1.7 2.5
Output Voltage – High State (ISource = 10 mA) VOH 10.5 11.2 –
Output Voltage – High State (ISource = 50 mA) 10.4 11.1 –
Output Voltage – High State (ISource = 400 mA) 9.5 10.9 –
Output Pull–Down Resistor RPD – 100 – kΩ
SWITCHING CHARACTERISTICS (TA = 25°C)
Propagation Delay (10% Input to 10% Output, CL = 1.0 nF) ns
Logic Input to Drive Output Rise tPLH(in/out) – 35 100
Logic Input to Drive Output Fall tPHL(in/out) – 36 100
Drive Output Rise Time (10% to 90%) CL = 1.0 nF tr – 14 30 ns
Drive Output Rise Time (10% to 90%) CL = 2.5 nF – 31 –

Drive Output Fall Time (90% to 10%) CL = 1.0 nF tf – 16 30 ns

Drive Output Fall Time (90% to 10%) CL = 2.5 nF – 32 –

TOTAL DEVICE
Power Supply Current ICC mA
Standby (Logic Inputs Grounded) – 6.0 10
Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz) – 10.5 15
Operating Voltage VCC 6.5 – 18 V
NOTES: 1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. Tlow = 0°C for MC34151 Thigh = +70°C for MC34151
–40°C for MC33151 +85°C for MC33151

2 MOTOROLA ANALOG IC DEVICE DATA

 MC34151 MC33151

Figure 1. Switching Characteristics Test Circuit Figure 2. Switching Waveform Definitions

12V
4.7 0.1
+
6 5.0 V 90%
Logic Input
+ tr, tf ≤ 10 ns
+ 10%
– + 0V
+
tPLH
5.7V Drive Output tPHL
+
7 90%
Logic Input 2

100k
Drive Output 10%
50 CL
tf tr
+

+
5
4

100k

Figure 3. Logic Input Current versus Figure 4. Logic Input Threshold Voltage
Input Voltage versus Temperature
2.4 2.2
V th , INPUT THRESHOLD VOLTAGE (V)

VCC = 12 V VCC = 12 V
2.0 TA = 25°C 2.0
I in , INPUT CURRENT (mA)

1.6 1.8
Upper Threshold
Low State Output
1.2 1.6

0.8 1.4 Lower Threshold

High State Output
0.4 1.2

0 1.0
0 2.0 4.0 6.0 8.0 10 12 –55 –25 0 25 50 75 100 125
Vin, INPUT VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

Figure 5. Drive Output Low–to–High Propagation Figure 6. Drive Output High–to–Low Propagation
t PLH(IN/OUT) , DRIVE OUTPUT PROPAGATION DELAY (ns)

t PHL(IN/OUT) , DRIVE OUTPUT PROPAGATION DELAY (ns)

Delay versus Logic Overdrive Voltage Delay versus Logic Input Overdrive Voltage
200 200
VCC = 12 V Overdrive Voltage is with Respect Overdrive Voltage is with Respect VCC = 12 V
CL = 1.0 nF to the Logic Input Lower Threshold to the Logic Input Lower Threshold CL = 1.0 nF
160 TA = 25°C 160 TA = 25°C

120 120

80 80

40 40

Vth(lower) Vth(upper)
0 0
–1.6 –1.2 –0.8 –0.4 0 0 1.0 2.0 3.0 4.0
Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V) Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)

MOTOROLA ANALOG IC DEVICE DATA 3

 MC34151 MC33151

Figure 8. Drive Output Clamp Voltage

Figure 7. Propagation Delay versus Clamp Current
3.0

V clamp , OUTPUT CLAMP VOLTAGE (V)

High State Clamp
(Drive Output Driven Above VCC)
VCC = 12 V
90% 2.0 80 µs Pulsed Load
VCC = 12 V
Vin = 5 V to 0 V 120 Hz Rate
Logic Input
CL = 1.0 nF TA = 25°C
1.0
TA = 25°C
VCC
0

Drive Output 0 Low State Clamp

10% (Drive Output Driven Below Ground)
Gnd

–1.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
50 ns/DIV IO, OUTPUT LOAD CURRENT (A)

Figure 9. Drive Output Saturation Voltage Figure 10. Drive Output Saturation Voltage
versus Load Current versus Temperature
0 0
V sat , OUTPUT SATURATION VOLTAGE(V)
V sat , OUTPUT SATURATION VOLTAGE(V)

Source Saturation VCC = 12 V Source Saturation VCC = 12 V

VCC –0.5
(Load to Ground) 80 µs Pulsed Load (Load to Ground) VCC Isource = 10 mA
–1.0 120 Hz Rate –0.7
TA = 25°C –0.9 Isource = 400 mA
–2.0
–1.1
–3.0
1.9 Isink = 400 mA
3.0 1.7
1.5
2.0
1.0 Isink = 10 mA
1.0 0.8
Sink Saturation Sink Saturation Gnd
Gnd 0.6
(Load to VCC) (Load to VCC)
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 –55 –25 0 25 50 75 100 125
IO, OUTPUT LOAD CURRENT (A) TA, AMBIENT TEMPERATURE (°C)

Figure 11. Drive Output Rise Time Figure 12. Drive Output Fall Time

90% 90% VCC = 12 V

Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25°C

VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
10% TA = 25°C 10%

10 ns/DIV 10 ns/DIV

4 MOTOROLA ANALOG IC DEVICE DATA

 MC34151 MC33151

Figure 13. Drive Output Rise and Fall Time Figure 14. Supply Current versus Drive Output
versus Load Capacitance Load Capacitance
80 80
t r –t f , OUTPUT RISE-FALL TIME(ns)

VCC = 12 V
VCC = 12 V
Both Logic Inputs Driven

ICC, SUPPLY CURRENT (mA)

VIN = 0 V to 5.0 V
0 V to 5.0 V
60 TA = 25°C 60
50% Duty Cycle
Both Drive Outputs Loaded
f = 200 kHz
TA = 25°C
40 40
f = 500 kHz

tf
20 20
f = 50 kHz
tr

0 0
0.1 1.0 10 0.1 1.0 10
CL, OUTPUT LOAD CAPACITANCE (nF) CL, OUTPUT LOAD CAPACITANCE (nF)

Figure 15. Supply Current versus Input Frequency Figure 16. Supply Current versus Supply Voltage
80 8.0
Both Logic Inputs Driven TA = 25°C

ICC , SUPPLY CURRENT (mA)

0 V to 5.0 V,
ICC , SUPPLY CURRENT (mA)

1
50% Duty Cycle Logic Inputs at VCC
60 6.0 Low State Drive Outputs
Both Drive Outputs Loaded
TA = 25°C 2
1 – VCC = 18 V, CL = 2.5 nF 3
40 2 – VCC = 12 V, CL = 2.5 nF 4.0
3 – VCC = 18 V, CL = 1.0 nF 4
4 – VCC = 12 V, CL = 1.0 nF Logic Inputs Grounded
High State Drive Outputs
20 2.0

0 0
10 k 100 1.0 M 0 4.0 8.0 12 16
f, INPUT FREQUENCY (Hz) VCC, SUPPLY VOLTAGE (V)
APPLICATIONS INFORMATION
Description 1.0 A. The low ‘on’ resistance allows high output currents to
The MC34151 is a dual inverting high speed driver be attained at a lower VCC than with comparative CMOS
specifically designed to interface low current digital circuitry drivers. Each output has a 100 kΩ pull–down resistor to keep
with power MOSFETs. This device is constructed with the MOSFET gate low when VCC is less than 1.4 V. No over
Schottky clamped Bipolar Analog technology which offers a current or thermal protection has been designed into the
high degree of performance and ruggedness in hostile device, so output shorting to VCC or ground must be avoided.
industrial environments. Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turn–on transition,
Input Stage and below ground during the turn–off transition. With CMOS
The Logic Inputs have 170 mV of hysteresis with the input drivers, this mode of operation can cause a destructive
threshold centered at 1.67 V. The input thresholds are output latch–up condition. The MC34151 is immune to output
insensitive to VCC making this device directly compatible with latch–up. The Drive Outputs contain an internal diode to VCC
CMOS and LSTTL logic families over its entire operating for clamping positive voltage transients. When operating with
voltage range. Input hysteresis provides fast output switching VCC at 18 V, proper power supply bypassing must be
that is independent of the input signal transition time, observed to prevent the output ringing from exceeding the
preventing output oscillations as the input thresholds are maximum 20 V device rating. Negative output transients are
crossed. The inputs are designed to accept a signal clamped by the internal NPN pull–up transistor. Since full
amplitude ranging from ground to VCC. This allows the output supply voltage is applied across the NPN pull–up during the
of one channel to directly drive the input of a second channel negative output transient, power dissipation at high
for master–slave operation. Each input has a 30 kΩ frequencies can become excessive. Figures 19, 20, and 21
pull–down resistor so that an unconnected open input will show a method of using external Schottky diode clamps to
cause the associated Drive Output to be in a known high reduce driver power dissipation.
state.
Undervoltage Lockout
Output Stage An undervoltage lockout with hysteresis prevents erratic
Each totem pole Drive Output is capable of sourcing and system operation at low supply voltages. The UVLO forces
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at the Drive Outputs into a low state as VCC rises from 1.4 V to

MOTOROLA ANALOG IC DEVICE DATA 5

 MC34151 MC33151
the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V, completely switch the MOSFET ‘on’, the gate must be
yielding about 500 mV of hysteresis. brought to 10 V with respect to the source. The graph shows
that a gate charge Qg of 110 nC is required when operating
Power Dissipation
the MOSFET with a drain to source voltage VDS of 400 V.
Circuit performance and long term reliability are enhanced
with reduced die temperature. Die temperature increase is Figure 17. Gate–To–Source Voltage
directly related to the power that the integrated circuit must versus Gate Charge
dissipate and the total thermal resistance from the junction to 16

V GS , GATE–TO–SOURCE VOLTAGE (V)

ambient. The formula for calculating the junction temperature MTM15N50
with the package in free air is: ID = 15 A
TJ = TA + PD (RθJA) TA = 25°C
12
where: TJ = Junction Temperature VDS = 100 V VDS = 400 V
TA = Ambient Temperature
PD = Power Dissipation 8.0
RθJA = Thermal Resistance Junction to Ambient 8.9 nF
There are three basic components that make up total
power to be dissipated when driving a capacitive load with 4.0
2.0 nF ∆ Qg
respect to ground. They are: CGS =
∆ VGS
PD = PQ + PC + PT 0
where: PQ = Quiescent Power Dissipation 0 40 80 120 160
PC = Capacitive Load Power Dissipation Qg, GATE CHARGE (nC)
PT = Transition Power Dissipation
The capacitive load power dissipation is directly related to the
The quiescent power supply current depends on the
required gate charge, and operating frequency. The
supply voltage and duty cycle as shown in Figure 16. The
capacitive load power dissipation per driver is:
device’s quiescent power dissipation is:
PC(MOSFET) = VC Qg f
PQ = VCC ICCL (1–D) + ICCH (D)
The flat region from 10 nC to 55 nC is caused by the
drain–to–gate Miller capacitance, occuring while the
where: ICCL = Supply Current with Low State Drive MOSFET is in the linear region dissipating substantial
Outputs amounts of power. The high output current capability of the
ICCH = Supply Current with High State Drive MC34151 is able to quickly deliver the required gate charge
Outputs for fast power efficient MOSFET switching. By operating the
D = Output Duty Cycle MC34151 at a higher VCC, additional charge can be provided
The capacitive load power dissipation is directly related to to bring the gate above 10 V. This will reduce the ‘on’
the load capacitance value, frequency, and Drive Output resistance of the MOSFET at the expense of higher driver
voltage swing. The capacitive load power dissipation per dissipation at a given operating frequency.
driver is: The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
PC = VCC (VOH – VOL) CL f Drive Outputs change state. The transition power dissipation
where: VOH = High State Drive Output Voltage per driver is approximately:
VOL = Low State Drive Output Voltage
CL = Load Capacitance PT ≈ VCC (1.08 VCC CL f – 8 × 10–4)
f= frequency PT must be greater than zero.

When driving a MOSFET, the calculation of capacitive load Switching time characterization of the MC34151 is
power PC is somewhat complicated by the changing gate to performed with fixed capacitive loads. Figure 13 shows that
source capacitance CGS as the device switches. To aid in this for small capacitance loads, the switching speed is limited by
calculation, power MOSFET manufacturers provide gate transistor turn–on/off time and the slew rate of the internal
charge information on their data sheets. Figure 17 shows a nodes. For large capacitance loads, the switching speed is
curve of gate voltage versus gate charge for the Motorola limited by the maximum output current capability of the
MTM15N50. Note that there are three distinct slopes to the integrated circuit.
curve representing different input capacitance values. To

6 MOTOROLA ANALOG IC DEVICE DATA

 MC34151 MC33151
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are optimum drive performance, it is recommended that the initial
imperative to prevent excessive output ringing and circuit design contains dual power supply bypass capacitors
overshoot. Do not attempt to construct the driver circuit connected with short leads as close to the VCC pin and
on wire–wrap or plug–in prototype boards. When driving ground as the layout will permit. Suggested capacitors are a
large capacitive loads, the printed circuit board must contain low inductance 0.1 µF ceramic in parallel with a 4.7 µF
a low inductance ground plane to minimize the voltage spikes tantalum. Additional bypass capacitors may be required
induced by the high ground ripple currents. All high current depending upon Drive Output loading and circuit layout.
loops should be kept as short as possible using heavy copper Proper printed circuit board layout is extremely critical
runs to provide a low impedance high frequency path. For and cannot be over emphasized.

Figure 18. Enhanced System Performance with

Common Switching Regulators Figure 19. MOSFET Parasitic Oscillations

VCC

47 0.1 Vin

6
+ Vin
++ – + +
5.7V
+
2 7 Rg
100k

100k
D1

TL494 +
1N5819
or +
TL594 4 5
100k

3 Series gate resistor Rg may be needed to damp high frequency parasitic

oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate–source circuit. Rg will decrease the
MOSFET switching speed. Schottky diode D1 can reduce the driver’s
The MC34151 greatly enhances the drive capabilities of common switching power dissipation due to excessive ringing, by preventing the output pin
regulators and CMOS/TTL logic devices. from being driven below ground.

Figure 20. Direct Transformer Drive Figure 21. Isolated MOSFET Drive
+
+

7
+ Isolation
100k

Boundary

4X
+ 1N5819
100k

+ 1N
5819
5
100k

Output Schottky diodes are recommended when driving inductive loads at

high frequencies. The diodes reduce the driver’s power dissipation by
preventing the output pins from being driven above VCC and below ground.

MOTOROLA ANALOG IC DEVICE DATA 7

 MC34151 MC33151
Figure 22. Controlled MOSFET Drive Figure 23. Bipolar Transistor Drive

Vin IB
Vin
+

+ 0
– Base Charge
Rg(on) Removal
+
C1
100k
Rg(off)

100k
In noise sensitive applications, both conducted and radiated EMI can The totem–pole outputs can furnish negative base current for enhanced
be reduced significantly by controlling the MOSFET’s turn–on and transistor turn–off, with the addition of capacitor C1.
turn–off times.

Figure 24. Dual Charge Pump Converter

VCC = 15 V

4.7 0.1
+
6

+
+ –
+ +
5.7V
+ 6.8 10
7 1N5819
2 +
+ VO ≈ 2.0 VCC
+
100k

47

+ 6.8 10
5 1N5819
4 +
– VO ≈ – VCC
100k

47
330pF +

3
10k

The capacitor’s equivalent series resistance limits the Drive Output Current Output Load Regulation
to 1.5 A. An additional series resistor may be required when using tantalum
or other low ESR capacitors. IO (mA) +VO (V) –VO (V)
0 27.7 –13.3
1.0 27.4 –12.9
10 26.4 –11.9
20 25.5 –11.2
30 24.6 –10.5
50 22.6 –9.4

8 MOTOROLA ANALOG IC DEVICE DATA

 MC34151 MC33151
OUTLINE DIMENSIONS

P SUFFIX
PLASTIC PACKAGE
CASE 626–05
8 5
ISSUE K
NOTES:
–B– 1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 4 2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
F
MILLIMETERS INCHES
NOTE 2 –A– DIM MIN MAX MIN MAX
L A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
C F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
–T– J J 0.20 0.30 0.008 0.012
N K 2.92 3.43 0.115 0.135
SEATING
PLANE L 7.62 BSC 0.300 BSC
M M ––– 10_ ––– 10_
D K N 0.76 1.01 0.030 0.040
H G
0.13 (0.005) M T A M B M

D SUFFIX
PLASTIC PACKAGE
CASE 751–05 NOTES:
1. DIMENSIONING AND TOLERANCING PER
(SO–8) ANSI Y14.5M, 1982.
–A– ISSUE N 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
4X P DAMBAR PROTRUSION. ALLOWABLE
–B– DAMBAR PROTRUSION SHALL BE 0.127
0.25 (0.010) M B M (0.005) TOTAL IN EXCESS OF THE D
1 4 DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 4.80 5.00 0.189 0.196
B 3.80 4.00 0.150 0.157
R X 45 _ F C 1.35 1.75 0.054 0.068
C D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
SEATING J 0.18 0.25 0.007 0.009
–T– PLANE K 0.10 0.25 0.004 0.009
8X D
K M_ J M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

MOTOROLA ANALOG IC DEVICE DATA 9

 MC34151 MC33151

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:

USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

*MC34151/D*
10 ◊ MOTOROLA ANALOG IC DEVICE DATA
MC34151/D