UNIT-4

Counter:
A Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit.

Counter Classification/Types

Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following flip flop is driven by output of previous flip
flops. We can understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse
is encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock
pulse for second flip flop) and so on. In this way ripples are generated through Q0,Q1,Q2,Q3
hence it is also called RIPPLE counter and serial counter. A ripple counter is a cascaded
arrangement of flip flops where the output of one flip flop drives the clock input of the
following flip flop

2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each
flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop. It is also
called as parallel counter.
Distinguish between synchronous and asynchronous counters:

S.NO Synchronous Counter Asynchronous Counter

In asynchronous counter main clock is only
In synchronous counter we use a applied to the first flip flop and then for rest of
universal clock that is common to all flip flops the output of previous flip flop is
1. flip flops throughout the circuit. taken as a clock.
Synchronous Counter is faster in
operation as compared to Asynchronous Counter is slower as compared to
2. Asynchronous Counter. synchronous counter in operation.
Synchronous Counter does not Asynchronous Counter produces decoding
3. produce any decoding errors. error.
Synchronous Counter is also called Asynchronous Counter is also called Serial
4. Parallel Counter. Counter.
Synchronous Counter designing as
well implementation are complex due Asynchronous Counter designing as well as
5. to increasing the number of states. implementation is very easy.
Synchronous Counter will operate in Asynchronous Counter will operate only in
6. any desired count sequence. fixed count sequence (UP/DOWN).
Synchronous Counter examples Asynchronous Counter examples
7. are: Ring counter, Johnson counter. are: Ripple UP counter, Ripple DOWN counter.
In synchronous counter, propagation In asynchronous counter, there is high
8. delay is less. propagation delay.

Module-8 Ripple Counter/ 3-Bit Ripple Counter:

A 3-bit counter having three negative edge triggered JK flip-flops connected in asynchronous
mode is shown in Figure 3. External clock goes to the clock input of first flipflop (FF0), Q0
output of first flip-flop goes to the clock input of second flip-flop (FF1) and Q1 output of second
flip-flop goes to the clock input of third flip-flop (FF2). First flip-flop (FF0) changes its state at
every negative going edge of the clock input so Q0 output of FF0 is considered as LSB. Second
flip-flop (FF1) changes its state at the negative going edge of Q0 output and third flip-flop (FF2)
changes its state at the negative going edge of Q1 output. In a 3-bit counter, Q2 output of FF2 is
considered as MSB.
Figure 3. Logic diagram of 3-bit asynchronous counter using JK flip-flops.

Assume that all flip-flops are initially reset (Q0=Q1=Q2=0, means 000 state). The timing
diagram of 3-bit asynchronous counter is shown in Figure 4 and its stepwise description is as
follows:

1. The first negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1 as well as Q2 output of FF2 remain unchanged. So after first negative going edge of clock
Q0=1, Q1=0 and Q2=0 (means 001 state).

2. The second negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 remains unchanged. So after second negative
going edge of clock Q0=0, Q1=1 and Q2=0 (means 010 state).

3. The third negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1 as well as Q2 output of FF2 remain unchanged. So after third negative going edge of clock
Q0=1, Q1=1 and Q2=0 (means 011 state).

4. The fourth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0 and Q2 output of FF2 changes from 0 to 1. So after fourth negative
going edge of clock Q0=0, Q1=0 and Q2=1 (means 100 state).

5. The fifth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1 as well as Q2 output of FF2 remain unchanged. So after fifth negative going edge of clock
Q0=1, Q1=0 and Q2=1 (means 101 state).

6. The sixth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 remains unchanged. So after sixth negative going
edge of clock Q0=0, Q1=1 and Q2=1 (means 110 state).

7. The seventh negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1
output of FF1 as well as Q2 output of FF2 remain unchanged. So after seventh negative going
edge of clock Q0=1, Q1=1 and Q2=1 (means 111 state).

8. The eighth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0 and Q2 output of FF2 changes from 1 to 0. So after eighth negative
going edge of clock Q0=0, Q1=0 and Q2=0 (means 000 state) and counter goes back to its
original state.
Figure 4. Timing diagram of 3-bit asynchronous counter using JK flip-flops.

A 3-bit asynchronous counter counts number of clock cycles from zero to seven (000 to 111
state) and repeats afterward (Table 2). So initial count for a 3-bit counter is 000 and terminal
count is 111.

Module-16/4-bit ripple counter :

Figure 5 shows a 4-bit asynchronous up counter having four negative edge triggered JK flipflops.
External clock goes to the clock input of first flip-flop (FF0), Q0 output of first flip-flop goes to
the clock input of second flip-flop (FF1), Q1 output of second flip-flop goes to the clock input of
third flip-flop (FF2) and Q2 output of third flip-flop goes to the clock input of fourth flip-flop
(FF3). First flip-flop (FF0) changes its state at every negative going edge of the clock input so
Q0 output of FF0 is considered as LSB. Second flip-flop (FF1) changes its state at the negative
going edge of Q0 output, third flip-flop (FF2) changes its state at the negative going edge of Q1
output and fourth flip-flop (FF3) changes its state at the negative

going edge of Q2 output. In a 4-bit counter, Q3 output of FF3 is considered as MSB. This
counter counts upward like 0, 1, 2, …, N so termed as up counter.
Figure 5. Logic diagram of 4-bit asynchronous up counter using JK flip-flops.

Assume that all flip-flops are initially reset (Q0=Q1=Q2=Q3=0, means 0000 state). Figure 6
shows the timing diagram of 4-bit asynchronous up counter and its stepwise description is as
follows:

1. The first negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after first negative
going edge of clock Q0=1, Q1=0, Q2=0 and Q3=0 (means 0001 state).

2. The second negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3 remain unchanged.
So after second negative going edge of clock Q0=0, Q1=1, Q2=0 and Q3=0 (means 0010 state).

3. The third negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after third negative
going edge of clock Q0=1, Q1=1, Q2=0 and Q3=0 (means 0011 state).

4. The fourth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0, Q2 output of FF2 changes from 0 to 1 and Q3 output of FF3 remains
unchanged. So after fourth negative going edge of clock Q0=0, Q1=0, Q2=1 and Q3=0 (means
0100 state).

5. The fifth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after fifth negative
going edge of clock Q0=1, Q1=0, Q2=1 and Q3=0 (means 0101 state).

6. The sixth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3.

remain unchanged. So after sixth negative going edge of clock Q0=0, Q1=1, Q2=1 and Q3=0
(means 0110 state).

7. The seventh negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1
output of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after seventh
negative going edge of clock Q0=1, Q1=1, Q2=1 and Q3=0 (means 0111 state).

8. The eighth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0, Q2 output of FF2 changes from 1 to 0 and Q3 output of FF3 changes
from 0 to 1. So after eighth negative going edge of clock Q0=0, Q1=0, Q2=0 and Q3=1 (means
1000 state).

9. The ninth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output
of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after ninth negative
going edge of clock Q0=1, Q1=0, Q2=0 and Q3=1 (means 1001 state).

10. The tenth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3 remain unchanged.
So after tenth negative going edge of clock Q0=0, Q1=1, Q2=0 and Q3=1 (means 1010 state).

11. The eleventh negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1
output of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after
eleventh negative going edge of clock Q0=1, Q1=1, Q2=0 and Q3=1 (means 1011 state).

12. The twelfth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0, Q2 output of FF2 changes from 0 to 1 and Q3 output of FF3 remains
unchanged. So after twelfth negative going edge of clock Q0=0, Q1=0, Q2=1 and Q3=1 (means
1100 state).

13. The thirteenth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1
output of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after
thirteenth negative going edge of clock Q0=1, Q1=0, Q2=1 and Q3=1 (means 1101 state).

14. The fourteenth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1
output of FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3 remain
unchanged. So after fourteenth negative going edge of clock Q0=0, Q1=1, Q2=1 and Q3=1
(means 1110 state).

15. The fifteenth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1
output of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after
fifteenth negative going edge of clock Q0=1, Q1=1, Q2=1 and Q3=1 (means 1111 state).

16. The sixteenth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output
of FF1 changes from 1 to 0, Q2 output of FF2 changes from 1 to 0 and Q3 output of FF3 changes
from 1 to 0. So after sixteenth negative going edge of clock Q0=0, Q1=0, Q2=0 and Q3=0
(means 0000 state) and counter goes back to its original state.
Figure 6. Timing diagram of 4-bit asynchronous up counter using JK flip-flops.

A 4-bit asynchronous up counter counts number of clock cycles from zero to fifteen (0000 to
1111 state) and repeats afterward (Table 3). So initial count for a 4-bit up counter is 0000 and
terminal count is 1111.

Mod-10 asynchronous counter /Decade counter

As a 4-bit counter has four flip-flops so it has maximum modulus (full modulus) of sixteen. In
case of a truncated modulus counter, the number of states is less than its maximum modulus.
Mod-10 counter (shorthand notation of modulus-10 counter) is a truncated modulus counter
which counts from 0 to 9. Mod-10 counter is commonly called as decade counter as it has a total
of ten states from 0000 to 1001. As 10≤24 , so four flip-flops are required to design a mod-10
counter.
 Figure 9 shows a mod-10 asynchronous counter having four negative edge triggered JK
flipflops. External clock goes to the clock input of first flip-flop (FF0), Q0 output of first flip-
flop goes to the clock input of second flip-flop (FF1), Q1 output of second flip-flop goes to the
clock input of third flip-flop (FF2) and Q2 output of third flip-flop goes to the clock input of
fourth flip-flop (FF3). Q1 output of FF1 and Q3 output of FF3 go to NAND gate whose output is
connected to clear (CLR ) terminal of all flip-flops.

Figure 9. Logic diagram of mod-10 asynchronous counter using JK flip-flops.

First flip-flop (FF0) changes its state at every negative going edge of the clock input so Q0
output of FF0 is considered as LSB. Second flip-flop (FF1) changes its state at the negative
going edge of Q0 output and third flip-flop (FF2) changes its state at the negative going edge of
Q1 output and fourth flip-flop (FF3) changes its state at the negative going edge of Q2 output. In
a mod-10 asynchronous counter, Q3 output of FF3 is considered as MSB.

Initially, all flip-flops are assumed to be reset (Q0=Q1=Q2=Q3=0, means 0000 state) so CLR
=1. Figure 10 shows the timing diagram of mod-10 asynchronous counter and its stepwise
description is as follows:

1. The first negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after first negative
going edge of clock Q0=1, Q1=0, Q2=0 and Q3=0 (means 0001 state).

2. The second negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3 remain unchanged.
So after second negative going edge of clock Q0=0, Q1=1, Q2=0 and Q3=0 (means 0010 state).

3. The third negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after third negative
going edge of clock Q0=1, Q1=1, Q2=0 and Q3=0 (means 0011 state).

4. The fourth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0, Q2 output of FF2 changes from 0 to 1 and Q3 output of FF3 remains
unchanged. So after fourth negative going edge of clock Q0=0, Q1=0, Q2=1 and Q3=0 (means
0100 state).
5. The fifth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output of
FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after fifth negative
going edge of clock Q0=1, Q1=0, Q2=1 and Q3=0 (means 0101 state).

6. The sixth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3 remain unchanged.
So after sixth negative going edge of clock Q0=0, Q1=1, Q2=1 and Q3=0 (means 0110 state).

7. The seventh negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1
output of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after seventh
negative going edge of clock Q0=1, Q1=1, Q2=1 and Q3=0 (means 0111 state).

8. The eighth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 1 to 0, Q2 output of FF2 changes from 1 to 0 and Q3 output of FF3 changes
from 0 to 1. So after eighth negative going edge of clock Q0=0, Q1=0, Q2=0 and Q3=1 (means
1000 state).

9. The ninth negative going edge of clock changes Q0 output of FF0 from 0 to 1 and Q1 output
of FF1, Q2 output of FF2 as well as Q3 output of FF3 remain unchanged. So after ninth negative
going edge of clock Q0=1, Q1=0, Q2=0 and Q3=1 (means 1001 state).

10. The tenth negative going edge of clock changes Q0 output of FF0 from 1 to 0, Q1 output of
FF1 changes from 0 to 1 and Q2 output of FF2 as well as Q3 output of FF3 remain unchanged.
So after tenth negative going edge of clock Q0=0, Q1=1, Q2=0 and Q3=1 (means 1010 state). As
Q1 output of FF1 and Q3 output of FF3 are connected to NAND gate to generate clear (CLR )
signal so as soon as they become high, the output of NAND gate becomes low which clears each
flip-flop. So the counter is in 1010 state for a small time (sum of the propagation delay of all
flipflops and NAND gate) and then goes to 0000 state. That is how mod-10 counter goes back to
its original state while skipping some states.

Figure 10. Timing diagram of mod-10 asynchronous counter using JK flip-flops.

A mod-10 asynchronous counter counts number of clock cycles from zero to nine (0000 to 1001
state) and repeats afterward (Table 5). So initial count for a decade counter is 0000 and terminal
count is 1001.

Module-8/3-bit synchronous counter :

These are the following steps to Design a 3 bit synchronous up counter using T Flip
flop:

Step 1: To design a synchronous up counter, first we need to know what number of flip
flops are required. we can find out by considering a number of bits mentioned in the
question. So, in this, we required to make 3 bit counter so the number of flip flops
required is 3 [2 n where n is a number of bits].

Step 2: After that, we need to construct state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table
of respective flip flop, in this case, it is T flip flop. So check the excitation table for T
flip flop Which is:

T Flip Flop Excitation Table

PRESENT STATE NEXT STATE T

0 0 0

0 1 1

1 0 1

1 1 0

So, the above table is the excitation table for T Flip Flop.

State Table with excitation table

 PRESENT STATE NEXT STATE FLIP FLOP

Q2 Q1 Q'3 Q'2 Q'1 T3 T2 T1

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1 0 0 1

1 1 1 0 0 0 1 1 1

Above table is created as per follow :

When Q 3 =0 which is present state and Q 3 ‘=0 which is next state then T 3 become 0 [As
per excitation table, have a look ]
Similarly, if Q 3 is 0 and Q 3 ‘ is 1 then T 3 become 1.
In similar way it goes on .

Step 3: After making the excitation table the next thing to do is dig out the equation
from the boolean algebra or K map for the design of the counter. So, for T 1 , T 2 and T 3 we
got 1, Q 1 and Q 1 .Q 2

K-Map

For T 3 Flip flop,

T 3 = Q 1 .Q 2

For T 2 Flip flop,

 T2= Q1

For T 1 Flip flop,

T 1 =1

Step 4: Lastly according to the equation got from K map create the design for 3 bit
synchronous up counter.

In above design, T 1 is getting input 1 and T 2 is getting input from the output of the T 1 flip
flop and lastly, T 3 is getting input from the output of T 1 and T 2 .
Module-16 synchronous counter:

These are the following steps to design a 4 bit synchronous up counter using T flip flop:

Step 1: To design a synchronous up counter, first we need to know what number of flip
flops are required. we can find out by considering a number of bits mentioned in the
question. So, in this, we required to make 4 bit counter so the number of flip flops
required is 4 [2 n where n is a number of bits].

Step 2: After that, we need to construct a state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table
of respective flip flop, in this case, it is T flip flop. So check the excitation table for T
flip flop Which is:

T Flip Flop Excitation Table

PRESENT STATE NEXT STATE T

0 0 0

0 1 1

1 0 1

1 1 0
So, the above table is the excitation table for T Flip Flop.

State Table with excitation table

Above table is created as per follow :

When Q 4 =0 which is present state and Q 4 ‘=0 which is next state then T 4 become 0 [As
per excitation table, have a look ]
Similarly, if Q 4 is 0 and Q 4 ‘ is 1 then T 3 become 1.
In similar way it goes on .

Step 3: After making the excitation table the next thing to do is dig out the equation
from the boolean algebra or K map for the design of the counter. So, for T 1 , T 2, T 3 and
T 4 we got 1, Q 1, Q 1 .Q 2 and Q 1 .Q 2 .Q 3

K-Map
For T 4 Flip flop,

T 4 = Q 1 .Q 2 .Q 3

For T 3 Flip flop,

For T2 Flip flop,

For T 1 Flip flop,

T 1 =1

Step 4: Lastly according to the equation got from K map create the design for 4 bit
synchronous up counter.
In above design T 1 is getting input logic 1 and T 2 is getting input from the output of the
T 1 flip flop and T 3 is getting input from the output of T 1 and T 2 lastly, T 4 is getting input
from the output of T 1 T 2 and T 3 .

DRAWBACKS OF RIPPLE COUNTERS :

1. Propagation Delay: Ripple counters experience propagation delay due to the sequential nature
of their flip flops.

2. Timing Skew: Clock pulses travelling through cascaded flip flops may introduce timing skew’
potentially causing unreliable behavior.

3. Glitches: The cascaded structure can result in undesired positive or negative pulses impacting
counter reliability.

4. Limited operating system: Ripple counters are slower than the synchronous counter parts,
limiting their maximum operating speed.

5. Power consumption: All flip flops toggle on each clock cycle, even if the counter is not
actively counting, leading to higher power consumption.

6. Complexity in decoding: Decoding the output to determine a specific count can become
complex especially in large ripple counters with more stages.
7. Non-Synchronous operation: Ripple counters are non-synchronous,meaning each flip flop
operates independently, leading to potential timing and synchronization challenges.

8. Limited Modules: Ripple counters have limited modules, less suitable for certain applications
as stage increases.

9. Limited applications in High-Frequency systems: Cumulative delay makes ripple counters less
suitable for high frequency and precision-timing applications.

ADVANTAGES OF SYNCHRONOUS COUNTERS:

1. Elimination of propagation delay: Synchronous counters avoid the propagation delay issue
seen in ripple counters , resulting in faster and more reliable performance.

2. Reduced timing skew: Clock signals reach all the flip flops simultaneously, minimizing time
skew and ensuring accurate timing relationships.

3. Glitch-free operation: Synchronous counters eliminate glitches, providing stable and reliable
output transactions without any unwanted signal fluctuations.

4. Higher operating speeds: Due to the absence of cumulative delays, Synchronous counters can
operate at high speeds compared to ripple counters.

5. Lower power consumption: Power consumption is generally lower as flip flops only toggle
when a Synchronous clock signal is received, minimizing the unnecessary power consumption.

6. Simplified decoding: Decoding specific counts is more straightforward in Synchronous

counters, contributing to ease of design and implementation.

7. Module flexibility: Synchronous counters offer flexibility in achieving a desired modulus

without the constraints seen in ripple counters, making them adaptable to various applications.

Synchronous 3 bit Up/Down counter:

Steps to design Synchronous 3 bit Up/Down Counter :

1. Decide the number and type of FF –
 Here we are performing 3 bit or mod-8 Up or Down counting, so 3 Flip Flops are
required, which can count up to 23-1 = 7.
 Here T Flip Flop is used.
2. Write excitation table of Flip Flop –

Excitation table of T FF

3. Decision for Mode control input M –

 When M=0 ,then the counter will perform up counting.
 When M=1 ,then the counter will perform down counting.
4. Draw the state transition diagram and circuit excitation table –

State transition diagram for 3 bit up/down counting.

5. Circuit excitation table –

The circuit excitation table represents the present states of the counting sequence and the next
states after the clock pulse is applied and input T of the flip-flops. By seeing the transition
between the present state and the next state, we can find the input values of 3 Flip Flops using
the Flip Flops excitation table. The table is designed according to the required counting
sequence.

Circuit excitation table

If there is a change in the output state of a flip flop (i.e. 0 to 1 or 1 to 0), then the
corresponding T value becomes 1 otherwise 0.
6. Find a simplified equation using k map –
Here we are finding the minimal Boolean expression for each Flip Flop input T using k map.

Simplified equation for K map

7. Create a circuit diagram –

The simplified expression for Flip Flops is used to design circuit diagrams. Here all the
connections are made according to simplified expressions for Flip Flops.

3 bit synchronous up/down counter.

8. Timing Diagram –

Timing diagram for 3 bit synchronous Up/Down counter

Explanation :
Here -ve edge triggered clock pulse is used for toggling purpose.

Characteristics table of T FF

After every falling edge, when T = 1, the output state of Flip Flop will toggle.
 Initially Q3 = 0 , Q2= 0 , Q1= 0.
Case 1 : When M=0 ,then M’= 1
 T3 = M’Q2Q1 + MQ’2Q’1 = Q2Q1.
 T2 = M’Q1 + MQ’1= 1.Q1= Q1.
 T1= 1.
 Because T1= 1, therefore FF1 output state toggles for every falling edge.
The output state of FF 2 will toggle when Q 1 = 1 and the falling edge of the clock pulse
occurs.
The output state of FF 3 will toggle only when Q 2.Q1= 1 and the falling edge of the clock
pulse occurs.
 In this way, after every falling edge, state transition takes place and we can get our desired
counting sequence.
Case 2 : When M=1 ,then M’ =0
 T3 = M’Q2Q1+MQ’2Q’1 = Q’2Q’1
 T2 = M’Q1+ MQ’1= 1.Q1= Q’1.
 T1= 1.
 Because T1= 1,therefore FF1 output state toggles for every falling edge.
The output state of FF 2 will toggle when Q’ 1 = 1 and the falling edge of the clock pulse
occurs.
The output state of FF 3 will toggle only when Q’ 2.Q’1= 1 and the falling edge of the clock
pulse occurs.
 In this way, after every falling edge, state transition takes place and we can get our desired
counting sequence.

Need of Programmable Counter:

A fixed counter typically counts within a predefined range of start and end values. For example,
it may count from 1 to 100 in increments of 1. In contrast programmable counter provides the
flexibility to set parameters such as start value, end value, increment, clock speed etc. the
following are some of the key reasons highlighting the need of a programmable counter.

 Programmable counters allow users to define a program the counting sequence according
to their specific requirements.
 Programmable counters have the ability to count in both up and down directions.
 Programmable counters can implement conditional counting based on external inputs.
 Different applications may demand unique counting patterns or specific sequences.
 Programmable counters offer more efficient use of hardware resources which leads to
better System performance.

Programmable Counter/ Presettable Counter:

A presettable counter is such a counter which counts up or down from a presettable value. In
other words, a counter which has the capability of loading or pre-setting just one number,
counting down or up from which is desired to be started, is called pre- settable counter (preset
means setting a device on some value in advance or direct set). As the liberty or choice of
loading any number higher than 0, rests with the user to decide as to from which particular
number the up or down counting has to be started, therefore this counter is also known as a
programmable counter. Thus, a presettable counter is a counter, in which counting starts from the
value, which you load or enter into it, or the number, programming of which is done in it. These
counters can either be synchronous or asynchronous

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In figure 8.14 (a), a presettable counter has been displayed, which consists of four JK flip-flops
and due to it, it is also called a 4-bit pre-settable counter. This counter can count up or down any
number between 0000 and 1111, which has been set via P0, P1, P2, P3. That’s any one number
between 0000 to 1111 is programmed in counter via P0, P1, P2, P3 at the outset, as a result of
which counter tends to set on this loaded or programmed number (as a result of an initial
deliberate and intentional programming in the counter, this counter is known as a pre-settable
counter) and starts counting from that number. If the logic diagram of this counter is analyzed, it
becomes clear that when its load control line is dropped, the outputs of all AND gates associated
with the line become high. As a result, clear and preset inputs of all flip-flops become inactive or
disabled. In this case, this circuit counts in an upward direction and there is no effect of data
inputs (P0 to P3) on the circuit.
When LOAD line is high, data inputs and its complements pass through NAND gates and pre-
set counter on P0, P1, P2, P3. (in figure PR implies pre-set whereas RST means re-set). For
example, presume that preset input is as follows;

P0, P1, P2, P3 = 0 1 1 0

According to this input data, as P3 is low, therefore both corresponding NAND gates towards left
of P3, produce a high preset and a low clear for Q 3 flip-flop (remember that when both inputs of
NAND gate are high, its output is low and when either one or both of its inputs are low, its
output will be high). In this way, Q 3 flip-flop clears and tends to reset (i.e. any binary bit stored
previously within it, now becomes clear and 0 is stored in place of it). Similarly, as a result of a
high (i.e. 1) P2 value, Q2 flip-flop sets and through a high P1 value, Q1 flip-flop sets. Whereas low
bit on P0 (i.e. 0) clears Q0 flip-flop. As such, counter presets on the following value;

Q = 0 1 1 0 (decimal 6)

After presetting the counter on a specific number (i.e. 0110) when LOAD line is dropped or
turned low once again, circuit starts to operate just like a normal counter and clock pulses being
received continuously on which, produce following outputs turn by turn;

Q = 0 1 1 1 (decimal 7)
Q = 1 0 0 0 (decimal 8)
Q = 1 0 0 1 (decimal 9)

This output changes continuously with each clock pulse, until maximum count or highest binary
number is received i.e.

Q = 1 1 1 1 (decimal 15)

After this, when next clock pulse strikes, counter becomes reset i.e.

Q=0000

Thus, in order to inculcate operation of a pre-settable counter, following points should be kept in
mind as summary;

(1). When LOAD line is low, circuit counts

(2). When LOAD line is high, counter resets on P0, P1, P2, P3
(3). Preset means changing output from low state to a high state whereas reset means changing
output from a high state to a low state. After programming the counter, it is up to you to decide
whether to start counting from a down direction or in an up-direction.

The most important application of a pre-settable counter is its programming of a modulus. For
this purpose, a NOR gate as shown in figure (b) is inducted with a pre – settable counter as
illustrated by figure (a). In this way, Q outputs of pre-settable counter drive NOR gate, whereas
NOR gate controls LOAD line of pre- settable counter. A NOR gate identifies and selects just
one number, entire bits values of which are binary 0 and rejects all other numbers except this,
therefore LOAD line is high when Q = 0000 and on all other numbers, LOAD line is low
(remember that when all inputs of a NOR gate are low, its output is high at that time and when
any one or both of its are high, its output becomes low). It means that when Q = 0000, the circuit
becomes preset and when there is any other number from Q = 0001 to Q = 1111, circuit counts.
Suppose that if preset input is 0110, then continuous clock pulses 0111, 1000 and 1001 etc.
received from clock, reach its maximum value during output process i.e.;

Q=1111

After this, when next clock pulse strikes, counter resets i.e. Q = 0 0 0 0

As soon as counter resets, NOR gate output turns out to be high immediately and data inputs
preset counter on the following binary numbers;
Q=0110

In other words, counter reaches its preset value 0110 (decimal 6) by means of effectively
jumping (i.e. blanking out or leaving) numbers from decimal 0 to decimal 5, as has been
demonstrated in figure ©. As such, whatever value has been pre-set on the counter, counter re-
starts counting from the preset value after reaching its highest or maximum value. That’s the
reason it is called a pre-settable counter.

Ring Counter

A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The
only difference between the shift register and the ring counter is that the last flip flop outcome is
taken as the output in the shift register. But in the ring counter, this outcome is passed to the first
flip flop as an input. All of the remaining things in the ring counter are the same as the shift
register.

In the Ring counter

No. of states in Ring counter = No. of flip-flop used

Below is the block diagram of the 4-bit ring counter. Here, we use 4 D flip flops. The same clock
pulse is passed to the clock input of all the flip flops as a synchronous counter. The Overriding
input(ORI) is used to design this circuit.

The Overriding input is used as clear and pre-set.

The output is 1 when the pre-set set to 0. The output is 0 when the clear set to 0. Both PR and
CLR always work in value 0 because they are active low signals.
PR = 0, Q = 1
CLR = 0, Q = 0

These two values(always fixed) are independent with the input D and the Clock pulse (CLK).

Working
The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also passed to the
clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3. The pre-set input set to 0
for the first flip flop. So, the output of the first flip flop is one, and the outputs of the remaining
flip flops are 0. The output of the first flip flop is used to form the ring in the ring counter and
referred to as Pre-set 1.

In the above table, the highlighted 1's are pre-set 1.

The Pre-set 1 is generated when

o ORI input set to low, and that time the Clk doesn't care.
o
o When the ORI input set to high, and the low clock pulse signal is passed as the negative
clock edge triggered.
A ring forms when the pre-set 1 is shifted to the next flip-flop at each clock pulse.

So, 4-bit counter, 4 states are possible which are as follows:

1000
0100
0010
0001

Application of Counters in Digital Electronics:

1) DIGITAL CLOCKS: Counters are utilized for time generation. 74LS160A synchronous decade
counters are commonly employed for seconds and minutes counting.
2) FREQUENCY DIVIDERS: Counters are used as programmable frequency dividers. Pre-setting a
specific count allows for achieving desired frequency dividers.
3) MULTIPLEXING: Counters are employed as programmable frequency dividers in multiplexing
operations using predefined counts.
4) AUTO PARKING CONTROL: Counters are used as programmable frequency dividers in auto
parking systems using pre-setting counts aids.
5) INDUSTRIAL DIGITALM CONTROL SYSTEMS: Counters are integral in various industrial digital
control applications such as objects, tracking finished products, frequency measurements, and
speed measurement.

REGISTERS:

Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital data. For
storing a large number of bits, the storage capacity is increased by grouping more than one flip
flops. If we want to store an n-bit word, we have to use an n-bit register containing n number of
flip flops.

Neeed of Register:

It serves as temporary storage for the data that the CPU requires for, immediate processing
during arithmetic, logic, and other operations. The Registers play a critical role in enhancing
CPU performance by providing fast access to frequently used data and facilitating efficient
data manipulation.

Methods of Data Transfer in Registers:

The two methods of data transfer in registers are serial and parallel, which differ in how they
transfer data and have different trade-offs:
 Serial transfer
Transfers data one bit at a time, with a clock pulse for each bit. Serial transfer is not sensitive
to time and requires less hardware than parallel transfer.
 Parallel transfer
Transfers register contents simultaneously with a single clock cycle. Parallel transfer is faster
than serial transfer, but circuitry is more complex and it is sensitive to time.

Types of Registers:

There are four types of Registers. They are

1) Serial-In Serial-Out

2) Serial-In Parallel-Out

3) Parallel-In Serial-Out

4) Parallel-In Parallel-Out

Serial-In Serial-Out:

A Serial-In Serial-Out shift register is a sequential logic circuit that allows data to be shifted in
and out one bit at a time in a serial manner. It consists of a cascade of flip-flops connected in
series, forming a chain.
Serial-In Parallel-Out:

A serial-in, parallel-out (SIPO) shift register is a digital circuit that changes serial data into
parallel data. It receives data bits one at a time on a single input line and then outputs all the bits
at once on multiple output lines.

Parallel-In Serial-Out:

A parallel-in serial-out (PISO) shift register is a type of shift register that stores data in parallel
and shifts it out serially. It can be used to read data into a microprocessor or to read multiple
switch closures into a microprocessor using only a few pins.

Parallel-In Parallel-Out:

A parallel in, parallel out (PIPO) register is a device that takes in parallel data, shifts it, and then
outputs it. It's a type of D-type register that's very fast, producing an output within a single clock
pulse.

Shift Register
A group of flip flops which is used to store multiple bits of data and the data is moved from one
flip flop to another is known as Shift Register. The bits stored in registers shifted when the clock
pulse is applied within and inside or outside the registers. To form an n-bit shift register, we have
to connect n number of flip flops. So, the number of bits of the binary number is directly
proportional to the number of flip flops. The flip flops are connected in such a way that the first
flip flop's output becomes the input of the other flip flop.

Serial IN Serial OUT Register with Circuit Digram

In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a single bit is
shifted at a time in either right or left direction under clock control.

Initially, all the flip-flops are set in "reset" condition i.e. Y 3 = Y2 = Y1 = Y0 = 0. If we pass the
binary number 1111, the LSB bit of the number is applied first to the Din bit. The D3 input of the
third flip flop, i.e., FF-3, is directly connected to the serial data input D3. The output Y 3 is passed
to the data input d2 of the next flip flop. This process remains the same for the remaining flip
flops. The block diagram of the "Serial IN Serial OUT" is given below.

Block Diagram:

Operation
When the clock signal application is disabled, the outputs Y 3 Y2 Y1 Y0 = 0000. The LSB bit of
the number is passed to the data input D in, i.e., D3. We will apply the clock, and this time the
value of D3 is 1. The first flip flop, i.e., FF-3, is set, and the word is stored in the register at the
first falling edge of the clock. Now, the stored word is 1000.

The next bit of the binary number, i.e., 1, is passed to the data input D 2. The second flip flop, i.e.,
FF-2, is set, and the word is stored when the next negative edge of the clock hits. The stored
word is changed to 1100.
The next bit of the binary number, i.e., 1, is passed to the data input D 1, and the clock is applied.
The third flip flop, i.e., FF-1, is set, and the word is stored when the negative edge of the clock
hits again. The stored word is changed to 1110.

Similarly, the last bit of the binary number, i.e., 1, is passed to the data input D 0, and the clock is
applied. The last flip flop, i.e., FF-0, is set, and the word is stored when the clock's negative edge
arrives. The stored word is changed to 1111.

Truth Table
Waveforms

Serial IN Parallel OUT with Circuit Diagram

In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and
outputs are fetched in a parallel way. The data is passed bit by bit in the register, and the output
remains disabled until the data is not passed to the data input. When the data is passed to the
register, the outputs are enabled, and the flip flops contain their return value

Below is the block diagram of the 4-bit serial in the parallel-out shift register. The circuit
having four D flip-flops contains a clear and clock signal to reset these four flip flops. In SIPO,
the input of the second flip flop is the output of the first flip flop, and so on. The same clock
signal is applied to each flip flop since the flip flops synchronize each other. The parallel outputs
are used for communication.

Block Diagram
Shift Left Register with Circuit Diagram
A shift register, wherein input data is entered from the right side, whereas digits already present
on the register leave out/ remove from the left side, are called shift left registers. In other words,
registers which shift input data towards left, are called shift left registers.

In figure 7.5, a shift left register has been elucidated, which consists of four D type flip-flops.
According to the figure, Din sets the right most flip-flop, Q0 sets the second flip-flop, Q1 sets third
flip-flop and Q2 sets fourth or final flip-flop. Remember that every time this register receives
next positive clock pulse its stored bits shift leftwards as per one position / clock pulse principle.
For example, if a state of Din = 1 and Q = 0000 exits on register, in such a situation, the rightmost
flip-flop (Q0) sets with the arrival of first clock pulse (or rising clock edge), as a result values of
all data inputs are 0, except 1 existing on the right end. In other words, stored word in the register
is as follows;
Q=0000
As first flip-flop’s output (Q0) located on right end, is input of the second flip-flop (i.e. D 1 = D0),
thus D1 value is 1 or equal to the value of D 0. Therefore, as a result of collision of next clock
pulse, Q1 flip-flop gets set and stored number in the register turns out to be as follows;
Q=0011
Similarly, as a result of third and fourth positive clock pulses, following changes take place in
the register;
Q=0111
Q=1111
Similarly, after four shift pulses, already existing number on the register shifts out completely
from the register and turn lost or disappear. And external number on right end of the register
completely gets shifted and stored in the register after four shift pulses. It remains in the register
so long as the value of Din is 1 (i.e. Din = 1) or as long as change does not occur in Din.
Figure 7.5 – shift – left register

Suppose that Din value has now been changed to 0 (i.e. D in = 0). Thus, in such a situation,
continuous clock pulses cause following changes in the register;
Q=1110
Q=1100
Q=1000
Q=0000
It must be remembered that as long as binary value of D in is 0 (i.e. Din = 0) no change occurs in
the stored register numbers even in the presence of insistent clock pulses.
The function of shift left register has further been elaborated with the help of its simple
manifestation vide figure 7.6. this register consists on four binary storage elements and binary
number 0000 is pre – stored on it. This can be seen in figure “A” via its primitive state.
Whereas, binary number 1111 is desired to be stored on the register. On the arrival of first clock
pulse, all bits of pre–stored numbers in the register shift towards left according to one – bit
position. As such, one bit moves out from left end of the register and is lost. And most rightward
bit of the external bits present on right side of the register, shifts inside the register, as has been
illustrated vide figure B.
Figure 7.6 – operation of shift left register

Exactly similarly, on receiving the next clock pulse, bits on left side of the register leave or quit
one by one and vacant space on the right side of the register, all external number bits enter and
stored on the register turn by turn. It must be remembered that movement or shifting direction of
external bits which entered register, has to be from right to left according to one–bit position.
This has been shown via an arrow sign above figure. Therefore, this type of register is called
shift–left register.

Shift Right Register with Circuit Diagram

Shift registers wherein input enters from left side and numbers already present on it, effuse or
excrete from right side, are called shift right registers. In other words, registers which transfers or
shifts input data rightwards, are called shift right registers. In figure 7.2, a shift right register has
been illustrated, which contains four flip-flops (it means that this register can store only a 4 – bits
binary number). According to this figure, every Q output keeps on setting D input of every next
flip-flop. When rising clock edge arrives, then stored bits shift rightward according to the “one–
bit position per clock pulse” principle. For example, D in value is 1 (i.e. Din = 1) and Q = 0000,
then upon influx of the first positive clock edge (i.e. clock pulse), leftward flip-flop tends to set.
In such a situation, all data inputs except input on the left side, are 0s. Thus, as a result of flip-
flop D3 being set, the word stored within a register is as follows;
Q=1000
With the appearance of this word, values of D 2 and D3 turn out 1 (i.e. D2 = D3 = 1s), because
Q3 output tends to set output D3 (see figure). Similarly, following results with the advent of
second rising clock edge.
Q=1100
Similarly, following changes take place as a result of 3rd clock pulse and 4th clock pulse.
Q=1110
Q=1111
Fig7.2
For further clarification, operation of a shift right register has been illustrated in figure 7.3. This
shift register also comprises four binary storage elements (i.e. four flip-flops) and number 1011
is pre-stored on it. A binary number 0110 exists on the serial outside this shift register, which is
desired to be stored in this register. As clock or shift pulses are applied on the register, then
according to one-bit position per class pulse principle, stored digits in shift register disappear
after exuding one by one from the right end. And at the same time, outer digits present on the
left, keep on shifting to register one by one.
Figure 7.3 – operation of shift register

In figure (A) initial state of a shift register has been depicted. According to figure (B), after the
advent of first clock pulse, already stored numbers in the register, as per one–bit position shift
rightward from its place. Thus, most rightward lying bit (1) in shift register, shifts or transfer out
of the register and rightward lying first bit (0) of the external number, moves to the leftmost
space of the shift register (remember that as a result of each shift pulse, all inputs present within
a shift register shift one position towards right. Thus, empty space which is created towards left
of the register, an external bit is inserted on it).
Similarly, after the arrival of second shift pulse (as has been shown in figure C), the most
rightward lying bit of the shift register, shifts out of the register. Whereas the most rightward
lying next bit present outside register, enters the most leftward lying empty space of the register.
As such, similar kind of situation repeats with the arrival of third shift pulse and fourth shift
pulse (as can be seen via figure D and E). Hence, after four shift pulses, the pre-stored number in
the register, disappears after completely shifting out of the register while the external number on
left end of the register, completely shifts from outside and stores on the register after four shift
pulses. It remains in it until some other external number is applied on register’s input after the
entrance of a new shift pulse.

Universal Shift Register with Circuit

Definition: A register that can store the data and /shifts the data towards the right and left along
with the parallel load capability is known as a universal shift register. It can be used to perform
input/output operations in both serial and parallel modes. Unidirectional shift registers and
bidirectional shift registers are combined together to get the design of the universal shift register.
It is also known as a parallel-in-parallel-out shift register or shift register with the parallel load.
Universal shift registers are capable of performing 3 operations as listed below.

 Parallel load operation – stores the data in parallel as well as the data in parallel
 Shift left operation – stores the data and transfers the data shifting towards left in the serial
path
 Shift right operation – stores the data and transfers the data by shifting towards right in the
serial path.
Hence, Universal shift registers can perform input/output operations with both serial and parallel
loads.

 Serial input for shift-right control enables the data transfer towards the right and all the serial
input and output lines are connected to the shift-right mode. The input is given to the AND
gate-1 of the flip-flop -1 as shown in the figure via serial input pin.
 Serial input for shift-left enables the data transfer towards the left and all the serial input and
output lines are connected to shift-left mode.
 In parallel data transfer, all the parallel inputs and outputs lines are associated with the
parallel load.
 Clear pin clears the register and set to 0.
 CLK pin provides clock pulses to synchronize all the operations.
 In the control state, the information or data in the register would not change even though the
clock pulse is applied.
 If the register operates with a parallel load and shifts the data towards the right and left, then it
acts as a universal shift register.

Design of Universal Shift Register

The design of a 4-bit universal shift register using multiplexers and flip-flops is shown below.
 S0 and S1 are the selected pins that are used to select the mode of operation of this register. It
may be shift left operation or shift right operation or parallel mode.
 Pin-0 of first 4×1 Mux is fed to the output pin of the first flip-flop. Observe the connections
as shown in the figure.
 Pin-1 of the first 4X1 MUX is connected to serial input for shift right. In this mode, the
register shifts the data towards the right.
 Similarly, pin-2 of 4X1 MUX is connected to the serial input for shift-left. In this mode, the
universal shift register shifts the data towards the left.
 M1 is the parallel input data given to the pin-3 of the first 4×1 MUX to provide parallel mode
operation and stores the data into the register.
 Similarly, remaining individual parallel input data bits are given to the pin-3 of related
4X1MUX to provide parallel loading.
 F1, F2, F3, and F4 are the parallel outputs of Flip-flops, which are associated with the 4×1
MUX.

Universal Shift Register Working

 From the above figure, selected pins the mode of operation of the universal shift register.
Serial input shifts the data towards the right and left and stores the data within the register.
 Clear pin and CLK pin are connected to the flip-flop.
 M0, M1, M2, M3 are the parallel inputs while F0, F1, F2, F3 are the parallel outputs of flip-
flops
  When the input pin is active HIGH, then the universal shift register loads / retrieve the data in
parallel. In this case, the input pin is directly connected to 4×1 MUX
 When the input pin (mode) is active LOW, then the universal shift register shifts the data. In
this case, the input pin is connected to 4×1 MUX via NOT gate.
 When the input pin (mode) is connected to GND (Ground), then the universal shift register
acts as a Bi-directional shift register.
 To perform the shift-right operation, the input pin is fed to the 1st AND gate of the 1st flip-
flop via serial input for shit-right.
 To perform the shift-left operation, the input pin is fed to the 8th AND gate of the last flip-
flop via input M.
 If the selected pins S0= 0 and S1 = 0, then this register doesn’t operate in any mode. That
means it will be in a Locked state or no change state even though the clock pulses are applied.
 If the selected pins S0 = 0 and S1 = 1, then this register transfers or shifts the data to left and
stores the data.
 If the selected pins S0 = 1 and S1 = 0, then this register shifts the data to right and hence
performs the shift-right operation.
 If the selected pins S0 = 1 and S1 = 1, then this register loads the data in parallel. Hence it
performs the parallel loading operation and stores the data.

S0 S1
Mode of Operation
0
0 Locked state (No change)

0
1 Shift-Left

Shift-Right
1 0

Parallel Loading
1 1

From the above table, we can observe that this register operates in all modes with serial/parallel
inputs using 4×1 multiplexers and flip-flops.

Use of Shift Registers as Memory:

shift registers are used as temporary memory in computers and other digital
devices:
 Data storage: Shift registers are used as temporary storage units for binary data while
the CPU processes it.
 Data transfer: Shift registers can be used to transfer data from one form to another.
 Data manipulation: Shift registers can be used to manipulate data.
 Data input and output: Shift registers can be used to get data into and out of
microprocessors.
 Data conversion: Shift registers can be used to convert parallel data to serial form for
transmission over long distances.
 Shift registers are digital memory circuitry that can be implemented in a
variety of ways:
 Data entry: Data can be entered into a shift register serially or in parallel.
 Data movement: Data can move left to right, right to left, or in both directions.
 Data latching: Each bit can be held in a latch, and the output of one latch can be
connected to the input of another.