#09 - Static Timing Analysis
#09 - Static Timing Analysis
#09 - Static Timing Analysis
Objective
Learn how to use PrimeTime to validate the timing performance of a design by checking all possible
paths for timing violations, without using logic simulation or test vectors.
Introduction
PrimeTime is a full-chip, gate-level static timing analysis tool that is an essential part of the design and
analysis flow for today's large chip designs.
Laboratory Tasks
PrimeTime can be used after Design Compiler or IC Compiler. The difference is that after IC Compiler
parasitics netlist in SPEF format can be used by PrimeTime for timing calculation. The steps to run
PrimeTime with the results from Design Compiler are very similar.
1. Start PrimeTime graphical user interface (GUI) from work directory, which is located in post_lay
directory. To start it enter:
% pt_shell
pt_shell> start_gui
2. The libraries are appended to the search path from .synopsys_pt.setup file located in work
directory. The setup file includes the following:
3. Use script created to carry out complex commands. There are two scripts in scripts directory,
which is located in post_lay directory. The names of these scripts are: sta_post_max.tcl and
sta_post_min.scr. The first is created for checking the setup timing and the second for checking
hold timing. To source the script write:
To check hold timing first enter reset_design command in command line, then source the
sta_post_min.tcl script.
3.1 Read the design netlist. (Fig. 2) PrimeTime accepts design gate-level netlists in Verilog and VHDL
formats. Read design netlist with the following command: read_verilog, read_vhdl.
3.2 For a design to be complete, it needs to be connected to all of the library components and designs
it references. So to perform a name-based resolution of design references for the current design
use the link command. The references must be located and linked to the current design in order
for the design to be functional. The purpose of this command is to locate all of the designs and
library components referenced in the current design and connect (link) them to the current design.
pt_shell> link
3.3 Read the design constraints and parasitics. Read design constraints using following command:
read_sdc.
3.4 Apply a constant value to input ports r and SE with the set_case_analysis command. It specifies
that a port or pin is at a constant logic value 1 or 0, or is considered with a rising or falling
transition. The ports in this lab are non active with the value 0 so the port r and Se is given 0.
3.5 Get a detailed report on all constraint violations in the design with report_constraint -
all_violators.
3.6 The report_timing command is the most flexible and powerful PrimeTime analysis command. The -
delay_type option specifies the type of timing checks to report. Set the delay type to max for setup
checks, min for hold checks.
In reports it is possible to have violations, for example hold or setup violation. To correct the hold
violation, add buffers to the respective port. And for correcting the setup violation increase the area of
cells. Here is an example of a report that has no violations.
****************************************
Report : timing
-path_type full
-delay_type max
-max_paths 1
-sort_by slack
Design : johnson
Version: L-2016.06-SP2
Date : Mon Jul 23 07:20:35 2018
****************************************
Startpoint: out_reg[7] (rising edge-triggered flip-flop
clocked by clk)
Endpoint: out_reg[0] (rising edge-triggered flip-flop clocked
by clk)
Last common pin: clk
Path Group: clk
Path Type: max
The report can also be seen in the Timing Analysis Driver Console by remarking one of the rows
and clicking the inspector button. See Fig. 2, and Fig.3.
pt_shell> exit