1.

Write the number of bins created for each bins mentioned in the below questions
where arrows are marked.

bit[15:0] addr;
covergroup g1 @(posedge clk)

ac:coverpoint add riff (!reset)

{
bins adrbin1 = {[0:6]};
bins adrbin2[] = {[8:10]};
bins adrbin3[2] = {[12:16]};
bins adrbin4[3] = {[18:20]};
bins adrbin5[] = {[18:24]’[22:32]};
bins heretoend ={[31:$];
bins others = default ;
}
endgroup
g1 g1_inst =new();

2. How many bins will be created in this question and what are the values taken for
consideration for coverage ?

logic [5:0] address;

covergroup cg4 @(posedge sample);
addr_cp: coverpoint address {
bins valid [4] = {[4:15], 21};
bins unused [] = {28, 29, 30};
bins out_of_range = {[48:$]};
ignore_bins ignore_vals = {[16:31]};
bins others = default;
}
endgroup : cg4
3. Please come up with the transition state diagram for the coverage code given and
also explain about how many bins are creates and each bins how does the
transitions are associated with

enum { Idle, Standby, Go1, Go2 } states;

covergroup cg_FSM @(posedge Clock);
coverpoint State {
bins valid_states[] = { Idle, Standby, Go1, Go2 };
bins valid_trans = ( Idle => Go1 => Go2 => Idle ), ( Idle => Standby => Idle );
bins reset_trans = ( Go1, Go2, Standby => Idle );
bins idle_range = ( Idle[*5:7] => Go1 );
bins go1_repeat = ( Go1 [-> 5] );
wildcard bins idle_trans =( 2’bx1 => Idle );
}
Endgroup

4. Can you run the example and get a report on the functional coverage?
module cg_test();
bit [4:0]a;
covergroup cg;
c1:coverpoint a {
option.at_least = 2;
bins a1[10]={[0:$]};
}
endgroup

cg c1;

initial
begin
c1 = new();
for(int i = 0;i < 16;i++)
begin
a = i;
c1.sample();
end
a = 4'b1010;
c1.sample();
end
endmodule
 5. Execute the code and explain the total percentage of functional coverage attained
class trans;
typedef enum {CLIENT1, CLIENT2, CLIENT3} client_e;
typedef enum {READ, WRITE} dir_e;

client_e all_clients[] = {CLIENT1, CLIENT2, CLIENT3};

client_e read_only_clients[] = {CLIENT1, CLIENT2};

covergroup cg with function sample(client_e client, dir_e dir);

client_cp: coverpoint client;

dir_cp: coverpoint dir;

client_dir_cr : cross client_cp, dir_cp {

ignore_bins ignore_read_only_clients = client_dir_cr with (client_cp inside
{read_only_clients} && dir_cp == WRITE);
}
endgroup

function new();
cg = new;
endfunction

function run();
foreach(all_clients[i])
begin
cg.sample(all_clients[i], READ);
cg.sample(all_clients[i], WRITE);
end
endfunction
endclass

module top;
trans t = new();

initial begin
 t.run();
end
endmodule

6. how many bins will be created for following covergroup

int i,j;

covergroup ct;

coverpoint i { bins i[] = { [0:1] }; }

coverpoint j { bins j[] = { [0:1] }; }

x1: cross i,j;

x2: cross i,j {

bins i_zero = binsof(i) intersect { 0 };

endgroup

7. How many bins will be created for following covergroup

bit [7:0] v_a, v_b;

covergroup cg @(posedge clk);

a: coverpoint v_a

bins a1 = { [0:63] };

bins a2 = { [64:127] };

bins a3 = { [128:191] };

bins a4 = { [192:255] };

}
b: coverpoint v_b

bins b1 = {0};

bins b2 = { [1:84] };

bins b3 = { [85:169] };

bins b4 = { [170:255] };

c : cross a, b

bins c1 = ! binsof(a) intersect {[100:200]};

bins c2 = binsof(a.a2) || binsof(b.b2);

bins c3 = binsof(a.a1) && binsof(b.b4);

endgroup

8. In the below code ,the addr,data [3:0] range is 0-15, randomized it for 16 time the
bins are coverd but did not get 100% coverage . what could be the problem for not
getting 100% coverage.

class transaction ;

randc bit[3:0] addr;

randc bit[3:0] data;

covergroup cg;

coverpoint addr;

coverpoint data;

endgroup
 function new();

cg=new();

endfunction

endclass

module tb();

transaction tr;

initial

begin

tr=new();

repeat(16)

begin

tr.cg.sample();

tr.randomize();

$display("the values of addr=%0d,data=%0d",tr.addr,tr.data);

end

end

endmodule

9. How many bins will be created and which bin will get hit in below example
program main;
bit [0:3] y;
bit [0:2] values[$]= '{3,3,3,4,4};
covergroup cg;
cover_point_y : coverpoint y {
bins trans_3 = (3[*5]);
bins trans_4 = (4[*2]); }
endgroup
 cg cg_inst = new();
initial
begin
foreach(values[i])
begin
y = values[i];
cg_inst.sample();
end
end
endprogram

10. What are the values going to be ignored here and how does the intersect work
cp_cmds : coverpoint command {
bins rnop = {1};
bins act = {2};
bins pre ={3};
}
cp_bank : coverpoint row_bank {
bins all_bank ={[0:63]};
}
cp_cross_cmd_bank : cross cp_cmds,cp_bank{
ignore_bins = binsof(cp_cmds) intersect{1} && binsof(cp_bank);
}
11. For a 32 bit memory controller (1kByte memory) like sel , address,w data,r data and
read_en/_write_en . Write covergroup for it ,also write corresponding cross
coverage for applicable scenarios
12. Inside a packet generator class that randomly generates packets for an Ethernet
switch
Create a covergroup that looks for coverage on packet attributes
Assume following packet attributes
Destination address – 4Bytes
Source Address – 4Bytes
Packet size 64 to 1518 Bytes
CRC field of 4 bytes at end
Everytime the packet is send to a driver - sample the covergroup to collect coverage on then
generated pack
13.

class trans;
rand logic wrd;
rand logic [2:0] addr;
rand logic [7:0] din;
rand logic [2:0] no_of_rst;
covergroup cg;
type_option.merge_instances = 1;
option.per_instance = 1;
option.get_inst_coverage = 1;
op_t: coverpoint addr;
op_r: coverpoint din;
endgroup
function new();
cg = new();
endfunction : new
endclass
program main();
trans trans_0 = new();
trans trans_1 = new();
trans trans_2 = new();
initial begin
trans_0.randomize();
trans_1.randomize();
trans_2.randomize();
trans_0.cg.sample();
trans_2.cg.sample();
$display(“coverage:%f”,trans_0.cg.get_coverage());
$display(“coverage1:%f”,trans_2.cg.get_inst_coverage());
$display(“coverage1:%f”,trans_2.cg.get_coverage());
end
endprogram