LT1671

60ns, Low Power,

Single Supply, Ground-Sensing
Comparator
U
FEATURES DESCRIPTIO
■ Low Power: 450µA The LT ®1671 is a low power 60ns comparator with comple-
■ Fast: 60ns at 20mV Overdrive mentary outputs and latch. The input common mode
85ns at 5mV Overdrive range extends from 1.5V below the positive supply down
■ Low Offset Voltage: 0.8mV to the negative supply rail. Like the LT1394, LT1016 and
■ Operates Off Single 5V or Dual ±5V Supplies LT1116, this comparator has complementary outputs
■ Input Common Mode Extends to Negative Supply designed to interface directly to TTL or CMOS logic. The
■ No Minimum Input Slew Rate Requirement LT1671 may operate from either a single 5V supply or dual
■ Complementary TTL Outputs ±5V supplies. Low offset voltage specifications and high
■ Inputs Can Exceed Supplies without Phase Reversal gain allow the LT1671 to be used in precision applications.
■ Pin Compatible with LT1394, LT1016 and LT1116
The LT1671 is designed for improved speed and stability
■ Output Latch Capability
for a wide range of operating conditions. The output stage
■ Available in 8-Lead MSOP and SO Packages
provides active drive in both directions for maximum
U speed into TTL, CMOS or passive loads with minimal
APPLICATIO S cross-conduction current. Unlike other fast comparators,
the LT1671 remains stable even for slow transitions
■ High Speed A/D Converters through the active region, which eliminates the need to
■ Zero-Crossing Detectors specify a minimum input slew rate.
■ Current Sense for Switching Regulators
■ Extended Range V/F Coverters The LT1671 has an internal, TTL/CMOS compatible latch
■ Fast Pulse Height/Width Discriminators for retaining data at the outputs. The latch holds data as
■ High Speed Triggers long as the LATCH pin is held high. Device parameters
■ Line Receivers such as gain, offset and negative power supply current are
■ High Speed Sampling Circuits not significantly affected by variations in negative supply
voltage.
, LTC and LT are registered trademarks of Linear Technology Corporation.

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TYPICAL APPLICATIO Propagation Delay vs Overdrive
140
1MHz Crystal Oscillator VS = ±5V
VSTEP = 100mV
5V 120 TA = 25°C
RL = 1M
1MHz CRYSTAL
2k (AT-CUT) 100
TIME (ns)

80
+ FALLING EDGE (tPDHL)
LT1671 OUTPUT 60
2k
–
2k 40 RISING EDGE (tPDLH)

0.068µF 20
0 10 20 30 40 50
1671 TA01
1671 TA01
OVERDRIVE (mV)
1671 TA02

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LT1671
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ABSOLUTE MAXIMUM RATINGS (Note 1)

Total Supply Voltage (V+ to V–) ............................... 12V Operating Temperature Range ................ – 40°C to 85°C
Positive Supply Voltage ............................................. 7V Specified Temperature Range (Note 3) ... – 40°C to 85°C
Negative Supply Voltage .......................................... – 7V Junction Temperature ........................................... 150°C
Differential Input Voltage ....................................... ±12V Storage Temperature Range ................. – 65°C to 150°C
Input and Latch Current (Note 2) ........................ ±10mA Lead Temperature (Soldering, 10 sec.)................. 300°C
Output Current (Continuous)(Note 2) ................. ±20mA

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PACKAGE/ORDER INFORMATION
ORDER PART TOP VIEW ORDER PART
TOP VIEW NUMBER NUMBER
V+ 1 8 Q OUT
V+ 1 8 Q OUT +
+IN 2 7 Q OUT LT1671CMS8 +IN 2 7 Q OUT LT1671CS8
–IN 3 6 GND –
V– 4 5 LATCH
–IN 3 6 GND LT1671IS8
ENABLE V– 4 5 LATCH
ENABLE
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 250°C/ W LTCT 1671
TJMAX = 150°C, θJA = 190°C/ W
1671I
Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
V + = 5V, V – = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage RS ≤ 100Ω (Note 4) 0.8 2.5 mV
● 4.0 mV
∆VOS Input Offset Voltage Drift ● 4 µV/°C
∆T
IOS Input Offset Current 10 100 nA
● 150 nA
IB Input Bias Current (Note 5) 120 280 nA
● 350 nA
VCMR Input Voltage Range (Note 6) ● –5 3.5 V
Single 5V Supply ● 0 3.5 V
CMRR Common Mode Rejection Ratio – 5V ≤ VCM ≤ 3.5V, TA > 0°C 55 100 dB
– 5V ≤ VCM ≤ 3.3V, TA ≤ 0°C 55 dB
Single 5V Supply
0V ≤ VCM ≤ 3.5V, TA > 0°C 55 100 dB
0V ≤ VCM ≤ 3.3V, TA ≤ 0°C 55 dB
PSRR Power Supply Rejection Ratio 4.6V ≤ V + ≤ 5.4V ● 50 85 dB
– 7V ≤ V – ≤ – 2V ● 60 90 dB
AV Small Signal Voltage Gain 1V ≤ VOUT ≤ 2V 2500 5000 V/V

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 LT1671
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
V + = 5V, V – = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOH Output Voltage Swing High V+ ≥ 4.6V, IOUT = 400µA ● 2.7 3.1 V
V + ≥ 4.6V, IOUT = 4mA ● 2.4 3.0 V
VOL Output Voltage Swing Low IOUT = – 400µA ● 0.3 0.5 V
IOUT = – 4mA 0.4 V
I+ Positive Supply Current 450 800 µA
● 1000 µA
I– Negative Supply Current 75 200 µA
● 250 µA
VIH LATCH Pin High Input Voltage ● 2 V
VIL LATCH Pin Low Input Voltage ● 0.8 V
IIL LATCH Pin Current VLATCH = 0V ● – 1000 – 250 nA
t PD1 Propagation Delay ∆VIN = 100mV, VOD = 20mV 60 80 ns
● 110 ns
t PD2 Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 85 100 ns
● 130 ns
∆t PD Differential Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 15 30 ns
t LPD Latch Propagation Delay (Note 8) 60 ns
t SU Latch Setup Time (Note 8) – 15 ns
tH Latch Hold Time (Note 8) 35 ns
t PW(D) Minimum Disable Pulse Width 30 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 7: tPD and ∆tPD cannot be measured in automatic handling
of a device may be impaired. equipment with low values of overdrive. The LT1671 is 100% tested with a
Note 2: This parameter is guaranteed to meet specified performance 100mV step and 20mV overdrive. Correlation tests have shown that tPD
through design and characterization. It has not been tested. and ∆tPD limits can be guaranteed with this test, if additional DC tests are
Note 3: The LT1671CS8 and LT1671CMS8 are guaranteed to meet performed to guarantee that all internal bias conditions are correct.
specified performance from 0°C to 70°C and are designed, characterized Propagation delay (t PD) is measured with the overdrive added to the actual
and expected to meet these extended temperature limits, but are not tested VOS. Differential propagation delay is defined as:
at – 40°C and 85°C. The LT1671IS8 is guaranteed to meet the extended ∆t PD = t PDLH – t PDHL
temperature limits. Note 8: Latch propagation delay (t LPD) is the delay time for the output to
Note 4: Input offset voltage (VOS) is defined as the average of the two respond when the LATCH pin is deasserted. Latch setup time (t SU) is the
voltages measured by forcing first one output, then the other to 1.4V. interval in which the input signal must remain stable prior to asserting the
Note 5: Input bias current (IB) is defined as the average of the two input latch signal. Latch hold time (tH) is the interval after the latch is asserted in
currents. which the input signal must remain stable.
Note 6: Input voltage range is guaranteed in part by CMRR testing and in
part by design and characterization.

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LT1671
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TYPICAL PERFORMANCE CHARACTERISTICS
Propagation Delay vs Propagation Delay vs
Gain Characteristics Load Capacitance Positive Supply Voltage
5.0 100 90
TA = 125°C VS = ±5V
4.5 RL = 1M
TA = 25°C FALLING EDGE (tPDHL) FALLING EDGE (tPDHL)
4.0 90
80
OUTPUT VOLTAGE (V)

3.5 TA = – 55°C
3.0 80 RISING EDGE (tPDLH)

TIME (ns)
TIME (ns)
2.5 RISING EDGE (tPDLH) 70

2.0 70
VS = ±5V V – = –5V
1.5
VSTEP = 100mV 60 VSTEP = 100mV
1.0 60 VOD = 5mV
VOD = 5mV
TA = 25°C TA = 25°C
0.5 RL = 1M
RL = 1M
0 50 50
–3 –2 –1 0 1 2 3 0 10 20 30 40 50 4.4 4.6 4.8 5.0 5.2 5.4 5.6
DIFFERENTIAL INPUT VOLTAGE (mV) OUTPUT LOAD CAPACITANCE (pF) POSITIVE SUPPLY VOLTAGE (V)
1671 G01 1671 G02 1671 G03

Propagation Delay vs Propagation Delay vs Propagation Delay vs

Input Overdrive Source Resistance Temperature
140 200 100
VS = ±5V VS = ±5V
90 t PDHL
VSTEP = 100mV 180 RL = 1M
120 TA = 25°C VOD = 20mV STEP SIZE = 800mV 80
RL = 1M 160 TA = 25°C t PDLH
400mV 70
100
140 60
TIME (ns)

TIME (ns)
TIME (ns)

200mV
80 120 50

FALLING EDGE (tPDHL) 40

100
60
30
80 VS = ±5V
STEP SIZE = 100mV 20 VSTEP = 100mV
40 RISING EDGE (tPDLH) 60 VOD = 5mV
10
RL = 1M
20 40 0
0 10 20 30 40 50 0 5 10 15 –50 –25 0 25 50 75 100 125
OVERDRIVE (mV) SOURCE RESISTANCE (kΩ) TEMPERATURE (°C)
1671 TA02
1671 G05 1671 G06

Input Offset Voltage vs Input Bias Current vs Positive Common Mode Limit vs
Temperature Temperature Temperature
4 500 6
VS = ±5V VS = ±5V VS = ±5V
3 RL = 1M RL = 1M RL = 1M
5
400
INPUT BIAS CURRENT (nA)

2
4
VOLTAGE (mV)

VOLTAGE (V)

300
1
3
0
200 VCM = –5V
2
–1
VCM = 0V
100
–2 1
VCM = 3.5V
–3 0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
1671 G07 1671 G08 1671 G09

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 LT1671
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TYPICAL PERFORMANCE CHARACTERISTICS
Negative Common Mode Limit vs Output Low Voltage (VOL) vs Output High Voltage (VOH) vs
Temperature Output Sink Current Output Source Current
1 0.8 5.0
RL = 1M VS = ±5V VS = ±5V
0 0.7 VIN = 30mV 4.5 VIN = –30mV
VS = SINGLE 5V SUPPLY
0.6 4.0
TA = 125°C

OUTPUT VOLTAGE (V)

–1 TA = 25°C
INPUT VOLTAGE (V)

TA = –55°C
0.5 3.5

VOLTAGE (V)
–2
TA = 125°C TA = –55°C
0.4 3.0
–3
0.3 TA = 25°C 2.5
–4
0.2 2.0
VS = ±5V
–5 0.1 1.5

–6 0 1.0
–50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
TEMPERATURE (°C) OUTPUT SINK CURRENT (mA) OUTPUT SOURCE CURRENT (mA)
1671 G10 1671 G11 1671 G12

Positive Supply Current vs Positive Supply Current vs Negative Supply Current vs

V + Supply Voltage Switching Frequency V – Supply Voltage
0.6 3.5 100
V – = 0V VS = ±5V V+ = 5V
VIN = –60mV 3.0 VSTEP = ±50mV VIN = –60mV
0.5 IOUT = 0 IOUT = 0 90 IOUT = 0
2.5
0.4
CURRENT (mA)

CURRENT (mA)

CURRENT (µA)
2.0 80
0.3 TA = 25°C TA = 125°C
1.5 TA = 125°C
TA = 125°C TA = –55°C 70
0.2
1.0 TA = 25°C
TA = 25°C
60
0.1 0.5 TA = –55°C TA = –55°C

0 0 50
0 1 2 3 4 5 6 7 8 0.1 1 10 –8 –7 –6 –5 –4 –3 –2 –1 0
SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (MHz) NEGATIVE SUPPLY VOLTAGE (V)
1671 G13 1671 G14
1671 G15

Response to 15MHz
Latch Pin Current vs Temperature ±10mV Sine Wave
1.0
VS = ±5V
+IN
0.8 20mVP-P
10mV/DIV
CURRENT (µA)

0.6 3V

Q OUT
0.4 1V/DIV

0V
0.2
50ns/DIV 1671 G17

0
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
1671 G16

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LT1671
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TYPICAL PERFORMANCE CHARACTERISTICS
tPD+ Response Time to tPD– Response Time to
5mV Overdrive 5mV Overdrive

1.4V 1.4V
5mV 5mV
+IN +IN

– 95mV Q OUT – 95mV Q OUT

0V 0V
VS = ±5V 20ns/DIV VS = ±5V 20ns/DIV
VOD = 5mV 1671 G18 VOD = 5mV 1671 G19

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PIN FUNCTIONS
V + (Pin 1): Positive Supply Voltage. Normally 5V. GND (Pin 6): Ground.
+IN (Pin 2): Noninverting Input. Q OUT (Pin 7): Noninverting Logic Output. This pin is high
when +IN is above – IN and LATCH ENABLE is low.
–IN (Pin 3): Inverting Input.
Q OUT (Pin 8): Inverting Logic Output. This pin is low
V – (Pin 4): Negative Supply Voltage. Normally either 0V
when +IN is above – IN and LATCH ENABLE is low.
or – 5V.
LATCH ENABLE (Pin 5): Latch Control Pin. When high, the
outputs remain in a latched condition, independent of the
current state of the inputs.

WU W
TI I G DIAGRA S

VOD

LATCH
∆VIN ENABLE
VIN
tSU tH
tPD
VIN
VOUT
tPD
1671 TD01
VOUT

1671 TD02

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 LT1671
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APPLICATIONS INFORMATION
Common Mode Considerations Input Bias Current
The LT1671 is specified for a common mode range of – 5V Input bias current is measured with the output held at
to 3.5V on a ±5V supply or a common mode range of 0V 1.4V. As with any PNP differential input stage, the LT1671
to 3.5V on a single 5V supply. A more general consider- bias current flows out of the device. It will go to zero on an
ation is that the common mode range is 0V below the input which is high and double on an input which is low.
negative supply and 1.5V below the positive supply, inde-
pendent of the actual supply voltage. The criterion for LATCH Pin Dynamics
common mode limit is that the output still responds The LATCH pin is intended to retain input data (output
correctly to a small differential input signal. latched) when the LATCH pin goes high. The pin will float
When either input signal falls below the negative common to a high state when disconnected, so a flow-through
mode limit, the internal PN diode formed with the sub- condition requires that the LATCH pin be grounded. The
strate can turn on, resulting in significant current flow LATCH pin is designed to be driven with either a TTL or
through the die. An external Schottky clamp diode CMOS output. It has no built-in hysteresis.
between the input and the negative rail can speed up To guarantee data retention, the input signal must remain
recovery from negative overdrive by preventing the sub- valid at least 35ns after the latch goes high (hold time), and
strate diode from turning on. must be valid at least – 15ns before the latch goes high
The zero crossing detector in Figure 1 demonstrates the (setup time). The negative setup time simply means that
use of a fast clamp diode. The zero crossing detector the data arriving 15ns after (rather than before) the latch
terminates the transmission line at its 50Ω characteristic signal is valid. When the latch signal goes low, new data
impedance. Negative inputs should not fall below –2V to will appear at the output in approximately 60ns (latch
keep the signal current within the clamp diode’s maximum propagation delay).
forward rating. Positive inputs should not exceed the
devices absolute maximum ratings nor the power rating Measuring Response Time
on the terminating resistor. To properly measure the response of the LT1671 requires
an input signal source with very fast rise times and
RS
5V
exceptionally clean settling characteristics. The last
50Ω CABLE
VIN + Q
requirement comes about because the standard compara-
1N5712
RT
LT1671 tor test calls for an input step size that is large compared
50Ω
– Q to the overdrive amplitude. Typical test conditions are
100mV step size with 5mV overdrive. This requires an
1671 F01
input signal that settles to within 1% (1mV) of final value
in only a few nanoseconds with no ringing or settling tail.
Figure 1. Fast Zero Crossing Detector
Ordinary high speed pulse generators are not capable of
generating such a signal, and in any case, no ordinary
Either input may go above the positive common mode
oscilloscope is capable of displaying the waveform to
limit without damaging the comparator. The upper voltage
check its fidelity. Some means must be used to inherently
limit is determined by an internal diode from each input to
generate a fast, clean edge with known final value. The
the positive supply. The input may go above the positive
circuit shown in Figure 2 is the best electronic means of
supply as long as it does not go far enough above it to
generating a fast, clean step to test comparators. It uses
conduct more than 10mA. Functionality will continue if the
a very fast transistor in a common base configuration. The
remaining input stays within the allowed common mode
transistor is switched off with a fast edge from the genera-
range. There will, however, be an increase in propagation
tor and the collector voltage settles to exactly 0V in just a
delay as the input signal switches back into the common
few nanoseconds. The most important feature of this
mode range.

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LT1671
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APPLICATIONS INFORMATION
5V 0.01µF*

0V
–100mV 25Ω
+ Q
FET PROBE
25Ω LT1671
10k FET PROBE
0.1µF 130Ω – Q

PULSE * TOTAL LEAD LENGTH INCLUDING DEVICE PIN.

2N3866 V1** 50Ω 0.01µF SOCKET AND CAPACITOR LEADS SHOULD BE
IN
LESS THAN 0.5 IN. USE GROUND PLANE
0V
** (VOS + OVERDRIVE)/200
–3V 50Ω 400Ω 750Ω –5V 1671 F02

–5V

Figure 2. Response Time Test Circuit

circuit is the lack of feedthrough from the generator to the Bypass capacitors should be as close as possible to the
comparator input. This prevents overshoot on the com- LT1671. A good high frequency capacitor such as a 0.1µF
parator input, which would give a false fast reading on ceramic is recommended, in parallel with a larger capaci-
comparator response time. tor such as a 4.7µF tantalum.
To adjust the circuit for exactly 5mV overdrive, V1 is Poor trace routes and high source impedances are also
adjusted so that the LT1671 output under test settles to common sources of problems. Be sure to keep trace
1.4V (in the linear region). Then V1 is changed by – 1V to lengths as short as possible, and avoid running any output
set overdrive to 5mV. trace adjacent to an input trace to prevent unnecessary
coupling. If output traces are longer than a few inches, be
High Speed Design Techniques sure to terminate them with a resistor to eliminate any
A substantial amount of design effort has made the LT1671 reflections that may occur. Resistor values are typically
relatively easy to use. It is much less prone to oscillation 250Ω to 400Ω. Also, be sure to keep source impedances
than some slower comparators, even with slow input as low as possible, preferably 1kΩ or less.
signals. However, as with any high speed comparator,
there are a number of problems which may arise because About Level Shifts
of PC board layout and design. The most common prob- The LT1671’s logic output will interface with many cir-
lem involves power supply bypassing. Bypassing is nec- cuits directly. Many applications, however, require some
essary to maintain low supply impedance. DC resistance form of level shifting of the output swing. With LT1671-
and inductance in supply wires and PC traces can quickly based circuits this is not trivial because it is desirable to
build up to unacceptable levels. This allows the supply line maintain very low delay in the level shifting stage. When
to move with changing internal current levels of the designing level shifters, keep in mind that the TTL output
connected devices. This will almost always result in of the LT1671 is a sink-source pair (Figure 3) with good
improper operation. In addition, adjacent devices con- ability to drive capacitance (such as feedforward capaci-
nected through an unbypassed supply can interact with tors). Figure 4 shows a noninverting voltage gain stage
each other through the finite supply impedances. Bypass with a 15V output. When the LT1671 switches, the base-
capacitors furnish a simple solution to this problem by emitter voltages at the 2N2369 reverse, causing it to
providing a local reservoir of energy at the device, keeping switch very quickly. The 2N3866 emitter-follower gives a
supply impedances low. low impedance output and the Schottky diode aids cur-
rent sink capability.

8
 LT1671
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APPLICATIONS INFORMATION
+V LT1671 is the key to low delay, providing Q2’s base with
nearly ideal drive. This capacitor loads the LT1671’s
output transition, but Q2’s switching is clean with 3ns
OUTPUT = 0 → +V (TYPICALLY 3V TO 4V) delay on the rise and fall of the pulse. Figure 6 is similar to
Figure 4 except that a sink transistor has replaced the
Schottky diode. The two emitter-followers drive a power
1671 F03 MOSFET that switches 1A at 15V. Most of the 7ns to 9ns
delay in this stage occurs in the MOSFET and the 2N2369.
Figure 3. Simplified LT1671 Output Stage When designing level shifters, remember to use transis-
tors with fast switching times and high fT. To get the kind
15V of results shown, switching times in the nanosecond
1k
range and an fT approaching 1GHz are required.
2N2369
+ 2N3866

LT1671 HP5082-2810
15V
– OUT
1k 12pF 1k
1k
RL
2N2369
RISE TIME = 4ns 1671 F04
+ 2N3866
FALL TIME = 5ns
POWER
LT1671
FET

Figure 4. Level Shift Has Noninverting Voltage Gain – 2N5160 1k

1k 12pF

1671 F06
Figure 5 is a very versatile stage. It features a bipolar swing RISE TIME = 7ns
FALL TIME = 9ns
that is set by the output transistor’s supplies. This 3ns
delay stage is ideal for driving FET switch gates. Q1, a
gated current source, switches the Baker-clamped output Figure 6. Noninverting Voltage Gain Level Shift
transistor, Q2. The heavy feedforward capacitor from the

5V

+
INPUT LT1671 4.7k 430Ω
1N4148
–
5V (TYP)
Q1
2N2907
1000pF 0.1µF 820Ω 330Ω
HP5082-2810 5V OUTPUT TRANSISTOR SUPPLIES
OUTPUT (SHOWN IN HEAVY LINES)
CAN BE REFERENCED ANYWHERE
–10V BETWEEN 15V AND –15V
Q2
2N2369 1671 F05

RISE TIME = 3ns 820Ω

FALL TIME = 3ns

–10V (TYP)

Figure 5. Level Shift with Inverting Voltage Gain—Bipolar Swing

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LT1671
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APPLICATIONS INFORMATION
Crystal Oscillators Switchable Output Crystal Oscillator
Figure 7 shows a crystal oscillator circuit. In the circuit, the Figure 8 permits crystals to be electronically switched by
resistors at the LT1671’s positive input set a DC bias point. logic commands. This circuit is similar to the previous
The 2k-0.068µF path sets up phase shifted feedback and examples, except that oscillation is only possible when
the circuit looks like a wideband unity-gain follower at DC. one of the logic inputs is biased high.
The crystal’s path provides resonant positive feedback
and stable oscillation occurs. XTAL X RX LOGIC INPUTS
AS MANY STAGES
AS DESIRED
XTAL B DX
5V 1k
B
1MHz TO 10MHz
2k 5V XTAL A
CRYSTAL (AT-CUT) 1k
A
1k
D1 D2
+ +
LT1671 OUTPUT
LT1671 OUTPUT 1k
2k
–
– 2k

2k 1671 F08
1671 F07

75pF = 1N4148
0.068µF
GROUND XTAL CASES

Figure 7. 1MHz to 10MHz Crystal Oscillator Figure 8. Switchable Output Crystal Oscillator. Biasing A or B
High Places Associated Crystal in Feedback Path. Additional
Crystal Branches Are Permissible

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 LT1671
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PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)

0.118 ± 0.004*
(3.00 ± 0.102)
8 7 6 5

0.192 ± 0.004 0.118 ± 0.004**

(4.88 ± 0.10) (3.00 ± 0.102)

1 2 3 4

0.040 ± 0.006 0.034 ± 0.004

(1.02 ± 0.15) (0.86 ± 0.102)
0.007 0° – 6° TYP
(0.18)
SEATING
PLANE 0.012
0.021 ± 0.006 0.006 ± 0.004
(0.53 ± 0.015) (0.30) (0.15 ± 0.102)
0.0256
REF MSOP (MS8) 1197
(0.65)
TYP
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8 7 6 5

0.228 – 0.244 0.150 – 0.157**

(5.791 – 6.197) (3.810 – 3.988)

1 2 3 4

0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

0.016 – 0.050
0.014 – 0.019 0.050
0.406 – 1.270
(0.355 – 0.483) (1.270)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE SO8 0996

11
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1671
U
TYPICAL APPLICATION
4MHz Adaptive Trigger Circuit LT1671’s positive input. The LT1671’s negative input is
biased directly from A1’s output. The LT1671’s output, the
Line and fiber-optic receivers often require an adaptive
circuit’s output, is unaffected by > 85:1 signal amplitude
trigger to compensate for variations in signal amplitude
variations. Bandwidth limiting in A1 does not affect trig-
and DC offsets. The circuit in Figure 9 triggers on 2mV to
gering because the adaptive trigger threshold varies
175mV signal from 100Hz to 4MHz while operating from
ratiometrically to maintain circuit output.
a single 5V rail. A1, operating at a gain of 15, provides
wideband AC gain. The output of this stage biases a 2-way Figure 10 shows operating waveforms at 4MHz. Trace A’s
peak detector (Q1 through Q4). The maximum peak is input produces Trace B’s amplified output at A1. The
stored in Q2’s emitter capacitor, while the minimum comparator’s output is Trace C.
excursion is retained in Q4’s emitter capacitor. The DC
value of the midpoint of A1’s output signal appears at the
A = 10mV/DIV
junction of the 500pF capacitor and the 3MΩ units. This
point always sits midway between the signal’s excursions, B = 50mV/DIV

regardless of absolute amplitude. This signal-adaptive

voltage is buffered by A2 to set the trigger voltage at the C = 1mV/DIV

5V
2k
50ns/DIV
1671F10
3 6
Q1
1 5
Q2 Figure 10. Adaptive Trigger
2 4
Responding to a 4MHz, 5mV Input.
5V 3M
Input Amplitude Variations from 2mV
+ 0.005µF 500pF 5V to 175mV Are Accommodated
A1 +
LT1227
A2
– 0.005µF
LT1006
–
13 10 3M
2k 750ΩΩ 510ΩΩ 14 12
5V Q3 Q4
36ΩΩ 15 11
470ΩΩ
+ 2k
+
10µF + 0.1µF 100µF 0.1µF
0.1µF TRIGGER
LT1671 OUT
470Ω –
INPUT
1671 F09
Q1, Q2, Q3, Q4 = CA3096 ARRAY: TIE SUBSTRATE (PIN 16) TO GROUND
= 1N4148

Figure 9. 4MHz Single Supply Adaptive Trigger. Output Comparator’s Threshold Varies Ratiometrically with
Input Amplitude, Maintaining Data Integrity over >85:1 Input Amplitude Range

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UltraFast is a trademark of Linear Technology Corporation.

1671fs, sn1671 LT/TP 0499 4K • PRINTED IN USA

Linear Technology Corporation
12 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1998