L2 - Internal Architecture of 8086
L2 - Internal Architecture of 8086
2 . M i c r o p r o c e s s o r s a n d i nt e r fa ci ng p r og r a mmi n g a n d
h a r d w a r e , s e c o n d e d i t i o n , D . V. H a l l – c h a p t e r 2
Internal Architecture of 8086
The BIU has four 16-bit segment registers. These are the Code Segment (CS)
register, the Data Segment (DS) register, the Stack Segment (SS) register, and
the Extra Segment (ES) register.
The SS register points to the current stack. The 20-bit physical stack address is
calculated from SS and SP for stack instruction such as PUSH and POP.
The DS register points to the current data segment; operands for most
instructions are fetched from this segment. The 16-bit contents of Source Index
(SI) or Destination Index (DI) are used as offset for computing the 20-bit
physical address.
The ES register points to the extra segment in which data (in excess of 64k
pointed to by DS) is stored. String instructions always use ES and DI to
determine the 20-bit physical address for the destination.
Functionality of Segment Registers of 8086
Examples
Example 3.1
Example 3.2
Do Exercise
Segment Address of 8086
Instruction
Opcode Operand
ADDRESSING MODES OF 8086 (2)
Instruction
Opcode DS [SI]
Memory
Registers
+ Operand
ADDRESSING MODES OF 8086 (6)