Chapter 10

Active Mixer Design

PathWave Advanced Design System (ADS)

Taken from Keysight EEsof EDA Technical Note: Low Power Mixer Design Example
Using Advanced Design System

Introduction
This chapter describes a method for designing a low-power single-transistor active
mixer using Keysight Advanced Design System (ADS). It includes details on the
design steps, simulation setups and data displays. The workspace file discussed in
this lab is available in ADS. To find it, click the button labeled Open an Example
Workspace in the ADS homepage. Under All Examples (in alphabetical order) click
example titled MixerPager_wrk.7zads. Chose a workspace to place this file in and
then let it unarchive itself. After the file has unarchived, in the list of available files in
the folder, open and read the schematic in 01 ReadMe.

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Figure 1. How to open the ReadMe Schematic

Figure 2. ReadMe File

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Circuit Specifications
The mixer is an upper sideband down converter, with an RF of 900 MHz RF, and a 45 MHz IF. The
simplified specifications supplied for this design call for it to provide a 10 dB conversion gain, operating
from a 1 Volt DC supply at 600 μA current. This very low power consumption is typical of applications
such as pagers and cellular phones, where battery lifetime is critical. Low cost is another driving factor
in such applications. Other typical specifications a mixer would have to meet in a “real-world” design,
such as linearity, port-to-port isolation, spurious response and noise figure, are not included in this
particular example. Open the examples in the workspace Mixers_wrk.7zads for examples of how to
include these simulations in your design.

Device Selection
One of the first steps in the design process is to select the device. The device used for this example is
the Motorola MMBR941, a bipolar junction transistor (BJT) packaged in a standard SOT-23 plastic
package. While bipolar devices do not generally have as good of mixing properties as field-effect
transistors, the low operating voltage precludes using FETs in this case. The chosen device has
acceptable performance for this application and offers several other advantages: it is extremely low
cost, and accurate models are readily available. A rule of thumb in high-volume, low-cost applications is
to use the least expensive device that will accomplish the job, the MMBR941 is a good choice for this
mixer. It is equally true that, no matter how good a device is, if there are no models with which to
simulate it, it becomes impossible to use in a design.

The device model, taken from the ADS RF Transistor Library, is a Gummel-Poon model where the
parameters were extracted by the manufacturer, Motorola. Initially, the model’s DC performance is
verified by comparing DC I-V curves. Next, a bias network will be designed to establish the desired
operating point. The model’s RF behavior will then be checked by comparing the simulated S-
parameters with measured S-parameters taken at the same bias conditions. Finally, the model’s
nonlinear performance is verified by simulating gain compression and comparing to measured results.

Device Model DC Verification (Cell: DC_curves)

DC_curves (see Figure 3) shows one way to set up a swept-parameter DC analysis. Open the
MixerPager_wrk workspace. It is in 02_DC & Bias Point > DC_curves > schematic. The DC voltage
supply at the collector is set to a variable, VCE, which is initialized in the VAR block. The VAR block
also initializes the variable, IBB, used in the DC current source at the base of the BJT. The actual
values used for VCE are determined in the DC simulation controller (DC1). In this example, VCE is
swept from 0 V to 6 V, so that the model can be verified over a relatively wide operating range. The DC
controller can only sweep a single variable, so the values for IBB are swept using the ParamSweep
component. The range chosen for the base current, IBB, is set to 50 to 350 μA. This IV characteristics
simulation setup is available as a default template in ADS and designers can obtain the same under
Schematic page by selecting Insert > Template > BJT Curve Tracer. It can be used after setting IBB
and VCE values as desired by designers.

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Figure 3. File location for DC_curves schematic

Figure 4. Transistor swept-parameter DC Analysis setup

Results from this simulation are displayed in DC_curves.dds. The available output variables can be
viewed by either placing a new plot or selecting the existing plot for edit, which opens the Insert Plot
dialog window shown in Figure 5. Notice that voltages at each of the named nodes are automatically
supplied, as is the current at the DC supply (VCC.i).

The data from rom the current probe, ICC.i, is redundant in this case. The numbered nodes are used to
store information for DC back annotation, discussed in the section on Device Model RF Verification.

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Figure 5. Insert Plot Diagram Box

Figure 6 shows there is good agreement between simulated and measured results. Measured data may
be read into ADS from either data files or instruments by selecting Window > New File/Instrument
Server. ADS will convert files in Touchstone, MDIF, Citifile or ICCAP formats to ADS datasets, which
can then be displayed alongside simulated results. The I-V curves clearly show that, at the specified
operating point of VCE = 1 V, ICE < 0.6 mA, the device will be operating in a low current regime. If
designers do not have measure datafile, this step can be omitted.

Figure 6. Comparison of Measured (symbols) and Simulated (solid line) DC I -V Curves for MMBR941

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Bias Network Design (Cell: BiasPoint)
The next step, selecting the device operating point and calculating the required bias resistors, is done
using the set-up in Bias-Point (02_DC & Bias Point > BiasPoint > schematic) as shown in Figure 7.
Since the collector voltage and current have been specified, only the base current needs to be determined.
In the schematic, VCC is fixed at 1V and IBB is swept from 1 to 10 μA, using the DC controller.

Figure 7. Calculation of Bias Point

The schematic contains bias tee components (the DC_Feed and DC_Block components) and 50 Ω
terminations that mimic the actual test setup used to measure the device. However, since the DC
simulation does not include any RF signals, they are not necessary at this point, and can be omitted
without changing the results. The results are displayed in tabular format in BiasPoint.dds (see Figure
8), so the appropriate base current can be selected. Note that the bias point current is actually lower
than the specified final value. This is because the device will be pumped with a relatively large LO
signal, causing a shift in the DC component of the collector current.

This shift will be calculated more precisely later on but, for now, IBB is selected to be 5 μA so that the
corresponding collector current (514 μA) is well below the specification.

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Figure 8. Device Operating Point Selection

The bias resistor values, shown in Figure 9, are calculated next. Base current, collector current, and
VCC are known, but the designer must make an assumption about the voltage drop across R to be able
to solve for Rc and Rb. In this case, a collector-emitter voltage of 0.75 V is chosen, providing a
reasonable working voltage at the output and realizable resistor values. The equations, written in the
data display page, calculate the exact values required for each value of base current, but of course the
nearest standard values must be chosen. The next step is to confirm bias operation using these
standard values and then verify the S-parameters of the model against measured values.

Figure 9. Calculation of Bias Network Resistors

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Device Model RF Verification (Cell: BiasNet)
BiasNet (02_DC & Bias Point > BiasNet > schematic), shown in Figure 10, includes both DC and S-
parameter simulations so, in this case, bias tee components (DC feeds and blocks) are required to
ensure proper RF performance. DC results are displayed directly on the schematic page, using the DC
back annotation feature. Once the simulation has been run, select Simulate > Annotate DC Solution
to see the DC voltages and currents at each node. This simulation can be done with both the exact
resistor values and nearest standard values (Rc = 470 Ω, Rb = 8.2 kΩ) to confirm that the operating
point is correct.

Figure 10. DC and S-Parameter Simulation Setup

The device S-parameters are calculated at this operating point and displayed, together with measured
data in Figure 11. The good agreement obtained here verifies the small-signal RF performance. The
device compression point will be simulated next to confirm large-signal operation.

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Figure 11. Comparison of Measured and Simulated S-Parameters for MMBR941.

Device Model Large-Signal Verification (Cell: Compression)

Compression (03_Compression & IF Match > Compression > schematic), shown in Figure 12,
shows two ways of calculating the device output compression at the RF frequency of 900 MHz. The
conventional way, implemented here with the Harmonic Balance controller, is to sweep the input power
level from low (i.e. small-signal) to high values until the output power compresses (the ratio Pout/Pin
starts to fall off from its small-signal value). The input power variable, “PwrIn” is swept from -45 to
-5 dBm and a Measurement Equation component is used to define the output power at 900 MHz, in
dBm. Notice that the dBm function assumes the power is being delivered to a 50 Ω load, unless
otherwise specified by the user. The argument of the function, “HB.Vout[1]”, specifies the fundamental
frequency. Figure 13 shows the equation and graph used to determine the 1 dB compression point and
includes the measured results as well.

Figure 12. Device Comparison Measurement Setup

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The second method, unique to ADS, is more direct and does not require graphs or sweeping variables.
The Gain Compression controller “XDB” performs a harmonic balance analysis that correctly calculates
and outputs the input and output power levels at the specified compression point. The default setting is
1 dB, but the user can specify any amount of compression. Figure 13 also shows the output from this
method: the input and output power levels at 1 dB compression are listed in dBm.

Figure 13. Two Methods of Determining 1 dB Compression – both show input P1 dB is -24 dBm.

ADS offers a great deal of flexibility in where and how output data are defined. To take a simple
example, “PwrOut” has been defined on the schematic page using a MeasEqn component, but it could
equally well have been defined on the data display page as an equation. An advantage of defining
outputs on the schematic is that they can be used in optimizations. On the other hand, defining them on
the data display page is useful for setting up templates (where complex calculations can be easily
applied to many different schematics). Also, any outputs that were overlooked before the simulation was
run can be calculated afterwards by adding them on the data display page.

Notice that, at this point, the design still uses ideal bias tee components to isolate the DC and RF signal
paths. These will be replaced with the real components that make up the matching networks in the next
stage of the design.

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Mixer Matching Circuit Design
An important step in mixer design is determining what impedances are seen at each port for both the RF
and IF. The finished input network will match the device base to 50 Ω at the RF and present a short
circuit at the IF (to prevent any noise at the input being amplified and interfering with the IF at the
output). Similarly, the output network will match the collector to 50 Ω at the IF, while presenting a short
circuit to the RF. Thus, for each frequency, the terminations seen at the input and output of the device
are completely different. Since the device is not unilateral, the presence of a short circuit on one side of
the device will affect the impedance seen at the other side for matching purposes.

The first step in designing the input matching network, then, is to determine the device input impedance
at the RF when the output is terminated in a short circuit. For the output matching network, the designer
needs to know the BJT’s output impedance at the IF when the input is terminated in a short circuit. In
ADS, equation-based 1-port Z-parameter components are used to simulate this sort of idealized
frequency-dependent termination, as seen in RFIFmatch1 (03_Compression & IF Match >
RFIFmatch1 > schematic) in Figure 14.

Figure 14. Calculating Device Impedance for Matching Network Design

The Z1P_Eqn components are defined in a VAR block. The one at the input, ZIN, is set to be a short-
circuit at the IF and an open at the RF. This provides the required termination for S22 at the IF, while
leaving S11 unperturbed at the RF. Similarly, ZOUT, at the output, is set to be a short at the RF and an
open at the IF. Notice also that the LO source is represented at this point as an ideal 50 Ω termination,
coupled to the mixer through a 0.5pF capacitor. The capacitor was chosen to be so small in order to
isolate the LO source from the RF input signal.

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The return loss looking back through the capacitor towards the LO source is only 0.33 dB at RF, so that
it almost appears like an open circuit to the incoming RF signal. The penalty is that the LO, which is
close in frequency to the RF, is also isolated from the circuit, meaning that a higher LO drive level is
required. For example, when the LO source is set at -10 dBm, only -22 dBm reaches the mixer.

The resulting S-parameters at the RF show that the input impedance is (11.5 - j51.4) Ω with a short-
circuit on the output. At the IF, the output impedance is (2065 - j2010) Ω. These values can be used to
decide on matching network topologies and component values. The designer always has several
topologies to choose from in developing a matching network, and which one is best will depend on
factors such maximizing yield (some topologies are more sensitive to component variation than others),
minimizing component count (to reduce cost) and combining functions where possible (incorporating the
bias decoupling components into the matching, in this case).

- To illustrate, Figure 15, shows that, starting at the device input impedance (A), a shunt inductor
followed by a series inductor will move the circuit impedance successively from B1 to 50 Ω. The
resulting network “A” has some advantages: the shunt inductor will provide a short to the IF at the input,
as required, and it can be used in the bias decoupling network (to replace the ideal DC_feed). However,
network “B” is even better: using a smaller value of shunt inductance brings the impedance to B2, where
a match is achieved using a series capacitor. C1 can also serve as the DC blocking capacitor, thereby
saving a component, so this network is used for the mixer. ADS provides an easy to use interactive
Smith Chart tool utility that can be used for designing Matching Networks. S

add series L2 Network A

B1

add shunt L1

add series C1
B2
Network B

add shunt L2
A

Figure 15. Choosing an Input Matching Topology

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The output matching network was developed using a similar approach: starting from the Smith Chart, a
matching network consisting of a shunt inductor followed by a series capacitor was designed. However,
this topology would result in any RF at the output being dumped to the load instead of being short
circuited as intended. To solve this, the shunt inductor (originally nearly 910 nH, a very high impedance
at RF) is replaced by an equivalent parallel LC combination. The capacitor must be large enough to
provide a near-short for the RF, and a value of 33 pF is chosen. The shunt inductor is then decreased,
so the total reactance provided by the LC pair at the IF is the same as that of the original inductor.

Although it was not done in this example, the actual component values for the network can be
calculated using ADS, as illustrated in examples like LNA_1GHz_prj. In this case, components were
calculated manually from the Smith Chart, and the resulting circuit is shown in LOdrive, (04_LO Drive >
LOdrive > schematic). The final matching networks are shown in Figure 16. Notice that, in addition to
components for the matching and bias networks, a load resistor, RL, has been added to control the
mixer’s conversion gain. The initial value of 4.7 kΩ was chosen to be high enough not to have an effect
on the mixer’s performance and will be adjusted as required once the conversion gain is known. Also,
two large RF bypass capacitors (BlkL1 and BlkL2) are added to provide RF ground to the output load
resistor and inductor and to the input shunt inductor, respectively.

Figure 16. Mixer Matching Network

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Mixer Conversion Gain Versus LO Drive Level (Cell: LOdrive)
LOdrive (04_Compression & LO Drive > LOdrive > schematic) shows how to simulate conversion
gain for the mixer and how to determine the effect of LO drive level on gain and DC bias. The RF and
LO frequencies and the LO power level have been defined as variables. The RF drive level is specified
at -50 dBm, while the harmonic balance controller is set up to sweep the LO drive level from -30 to -5
dBm. (The controller has many parameters, and the user can control which are visible on the schematic
by editing the component and choosing the “Display” page in the edit dialog window.) A simulation
measurement equation defines the output power, in dBm, at the IF. Defining it here instead of the data
display page makes it possible to optimize for output IF power, if needed. The “mix” function will return
the component of the Vout spectrum defined by {-1, 1}, meaning {-Freq[1] + Freq[2]} or -LO + RF = IF
(45 MHz).

The P_IF equation calculates the dBm value of the mix function.

The data display shows the effect of the load resistor (see Figure 17).

Figure 17. Setup for Swept LO Drive Level Mixer Simulation

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Since the conversion gain is the difference between P_IF and the RF, and the RF power is fixed at -50
dBm, the conversion gain can be calculated with a simple expression. Note that the default dataset,
LODrive, contains results for a 4.7 kΩ load resistor, and the conversion gain for this simulation is
calculated by the equation “ConvGain”. The conversion gain for a -10 dBm LO drive is 17 dB, which is
unacceptably high. A second simulation was run with the load resistor reduced 1.5 kΩ, which creates a
lossy mismatch on the output. The results for that simulation were output to dataset LOdrive15, and
equation “ConvGain_Rl5kOhm” shows the conversion gain is reduced to 13.7 dB. This is still higher
than the specification of 10 dB but will be left at this value for now since conversion gain can be
expected to decrease further when non-ideal surface mount components replace the ideal components.

The second graph in the data display shown in Figure 18 illustrates the effect of the LO drive level on
DC bias. Increasing the LO signal at the base drives the output swing on the collector harder, shifting
the DC component higher (see Figure 19). In practice, a 5 to 15 percent shift in collector bias current
typically gives good performance for a mixer of this type.

Figure 18. Conversion Gain and Bias Current Vary with LO Drive Level

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Figure 19. Variation in Output Current with LO Drive Level

Mixer Conversion Gain Versus RF Signal Level (Cell: MixCompr)

The set-up for measuring mixer compression used in MixCompr (03_Compression & IF Match >
MixCompr) is very similar to LOdrive, except that the LO power level is now held constant at -10 dBm,
while the RF power is swept from -50 to 0 dBm. As the results in Figure 20 show, the mixer’s conversion
gain reaches 1 dB compression at an input signal level of -27 dBm.

Figure 20. Mixer Conversion Gain Compression

Now that the mixer’s performance is verified, the next step is to replace the ideal passive components
with realistic models of the surface-mount resistors, capacitors and inductors that will be used in the
actual circuit.

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Creating the Mixer Layout (Cell: MixerLayout)
MixerLayout (05_Mixer Design & Sim > MixerLayout) contains a layout as well as a schematic.
There are many possible ways to create layouts, and the best method will depend on the application. In
this example, the first step was to convert all the components in the schematic to their nearest
equivalent SMT part from the Passive Component Library. Next, these parts were placed in the layout
window in their approximate locations. Interconnects were made in the layout window using the Trace
command or microstrip components, and the final positioning of the components was adjusted. Finally,
the schematic was updated using the design synchronization function.

MixerLayout was created by saving MixCompr under a new name and modifying it. Since the finished
circuit will be simulated using the layout representation, it will have to be placed as a subnetwork in
another schematic. This is because the layout file cannot contain simulator controllers, sources or
terminations. The first step is to remove those components from the schematic and add ports to each
point in the circuit that will be connected externally, either to sources, grounds or other circuits. The
labels for each port will appear on the schematic symbol used when the design is placed in another
schematic, so meaningful names should be provided. At this stage, the designer may also create a
custom symbol for the circuit by selecting View > Create/Edit Schematic Symbol.

Figure 21. Substitution of SMT component for ideal component requires use of SMT_Pad

The next step is to replace each resistor, capacitor and inductor with a model of the SMT component
that will be used in the actual circuit. The models are all found in the SMT Component Libraries by
selecting the Browse and Search function in the Component Library List window. In this case, all the
capacitors are MuRata Erie parts: the matching and bias capacitors are all MuRata Erie series GRM39
parts, while the RF bypass capacitors are GRM36 series. The resistors are taken from the Dale CRCW
series and the inductors are Coilcraft parts.

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Where possible, parts are chosen to have a standard 0.060”x 0.030” footprint, although the inductors
and RF bypass capacitors have different dimensions. Note that each SMT component specifies the
name of the SMT_Pad component it uses. This SMT_Pad defines the pad-size to be used in layout, as
shown in Figure 21. The designer must define these on the schematic page to ensure the pads appear
correctly in the layout. Since each user will define the pads to suit their own board-fabrication process,
the models do not include pad characteristics.

Once the components are placed and the pads defined, the designer can select Layout > Place
Components from Schematic to Layout and place each part in its approximate location in the layout
window. Traces are a convenient way to create the interconnects. They can be converted to equivalent
microstrip components using the Edit > Path/Trace/Convert Traces command. In general, when
moving back and forth between the schematic and layout representations, it is best to work on small
sub-sections and synchronize the two representations manually. Synchronization ensures that both
layout and schematic describe the same circuit: for example, if the designer has made some changes to
the layout, the schematic can be updated to reflect them by selecting Schematic > Generate/Update
Schematic in the layout window. Changes made to the schematic can be similarly transferred to the
layout by choosing Layout > Generate/Update Layout in the schematic window.

Figure 22 shows the finished layout. A ground-plane has been added to the top-side metallization to
eliminate the need for vias, thus reducing fabrication costs. This can be easily created in ADS by
drawing a rectangle the size of the final circuit board and using the Edit > Create Clearance feature to
generate the required spacing around transmission lines and component footprints.

Figure 22. Finished Layout for Mixer Circuit

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Finally, in this example the design will be simulated from layout, so the “SimLay” option is selected in
the File > Design/Parameters dialog box. This allows the designer to see the effects of changes in the
layout directly, without having to re-enter parameters in the schematic. Notice that components in the
schematic can be modified (or even deleted entirely) without affecting the simulation, as long as the
layout remains intact.

Simulation from Layout (Cell: SimFromLayout)

SimFromLayout (05_Mixer Design & Sim > SimFromLayout > schematic) contains MixerLayout,
together with the simulation controller, sources and terminations required to simulate it. The simulation
setup is identical to the one used in LOdrive so the results using the non-ideal components may be
compared directly. MixerLayout uses microstrip lines, so an “MSub” component is also included
(Figure 23).

Figure 23. MixerLayout called as a sub-network in SimFromLayout

Figure 24 shows the mixer conversion gain as a function of LO drive level when simulated using both
the ideal components and the SMT model components. As expected, the conversion gain has drops
significantly, due mainly to the resistive losses in the inductors. This can be verified by replacing
individual components with their ideal counterparts and re- simulating. The load resistor can now be
adjusted to compensate for these losses:

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 Figure 24. Comparison of Mixer Conversion Grain using Ideal and SMT Components

Changing Rl from 1.5 kΩ to 3.3 kΩ restores the simulated conversion gain to 10.76 dB, providing a
0.76 dB margin over the specification. Note that these changes must be made in the layout file in order
to be reflected in the simulation results. Once any such final corrections have been made to the layout,
the circuit board is ready to be exported for fabrication.

Conclusion
An example mixer design using Keysight ADS has been presented, including details of the design
process and simulation set-ups. This example is included with Keysight ADS and can be readily copied
and modified by users for their own projects.

Additional material and various Mixer design examples can be found at the Keysight EEsof EDA
Knowledge Center: http://www.keysight.com/find/eesof-knowledgecenter

Congratulations! You have completed Active Mixer Design. Check out more examples:
http://www.keysight.com/find/eesof-ads-rfmw-examples

Learn more at: www.keysight.com

For more information on Keysight Technologies’ products, applications or services,
please contact your local Keysight office. The complete list is available at:
www.keysight.com/find/contactus

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This information is subject to change without notice. © Keysight Technologies, 2016 - 2021, Published in USA, March 10, 2021, 5992-1634EN