SC8701英文原版
SC8701英文原版
SC8701英文原版
1 Description 2 Features
The SC8701 is a synchronous 4-switch buck-boost High efficient buck-boost operation
controller. It is able to effectively output voltage no Dynamic adjustable output voltage
matter it is higher, lower or equal to the input voltage.
Dynamic adjustable Input and Output current limit
The SC8701 supports very wide input and output
Wide input voltage range: 2.7 V to 36 V
voltage range. It can support applications from 2.7V to
36V input range and 2V to 36V output range. The Wide output range: 2V to 36V
driver voltage is set to 10V to fully utilize external
Integrated 10V, 2A gate driver
MOSFETs for highest efficiency.
Adjustable frequency 200kHz to 600kHz
The SC8701 supports input current limit, output current
limit and over temperature protections to ensure safety Under voltage protection
3 Applications
Power Bank
USB PD
Car Charger
Industrial applications
4 Device Information
ORDER NUMBER PACKAGE BODY SIZE
SC8701QDER 32 pin QFN 4mm x 4mm x 0.75mm
OPT
VIN VOUT
VCC
SNS1P
SW1
SNS1N
LD1
PGND
HD1
BT1
VCC
VIN LD2
SW2
CEb VCC
PWM SC8701 BT2
IPWM HD2
VCC SNS2P
PG
AGND SNS2N
ITUNE
COMP
FREQ
ILIM2
ILIM1
VOUT
DT
FB
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SNS1N
SNS1P
PGND
SW1
HD1
BT1
LD1
VIN
/CE VCC
NC LD2
PWM SW2
PG HD2
PGND
IPWM BT2
ITUNE VOUT
NC SNS2P
DT SNS2N
AGND
COMP
FB
NC
FREQ
ILIM1
ILIM2
TERMINAL NC
I/O DESCRIPTION
NUMBER NAME
1 /CE I Chip Logic Enable, CE=Low, chip enable. Internal pull low
2 NC I Floating
PWM pin accepts square waveform from 20K to 100K. By adjusting duty cycle, output voltage can
be adjusted according to needs. When duty=0, output voltage = 1/6 of the preset value by the
feedback resistor divider at FB pin. When duty = 100%, output voltage = preset value.
3 PWM I
1 5
VOUT = VOUT_SET×( + ×D)
6 6
4 PG O Open drain, active high when VOUT is within 90% to 110% * VOUT target.
IPWM pin is used together with ITUNE pin to adjust the current limit value of either ILIM1 or ILIM2.
The ITUNE pin is used to select the control object between ILIM1 and ILIM2, and IPWM signal is to
adjust the limit value.
IPWM pin accepts PWM waveform from 20kHz to 100kHz, and the current limit value is
proportional to its duty cycle.
For example, if ITUNE pin selects ILIM1, then the input current limit is set by:
5 IPWM I
IIN = ILIM1_SET×D
In the equation above, ILIM1_SET is the current limit value set by the resistor at ILIM1 pin, D is the duty
cycle of the IPWM signal.
Similarly, if ITUNE pin selects ILIM2, then the output current limit is set by:
IOUT = ILIM2_SET×D
ITUNE pin selects the IPWM control object between ILIM1 and ILIM2. .
If ILIM1 current limit needs to be controlled, connect the ILIM1 resistor between ILIM1 pin and
ITUNE pin. If ILIM2 current limit is to be controlled, connect the ILIM2 resistor between ILIM2 pin
and ITUNE pin.
6 ITUNE IO
Only one current limit can be selected by ITUNE pin.
If IPWM function is not needed, leave ITUNE pin and IPWM pin floating, and connect the ILIMx
resistor from the ILIMx pin to AGND accordingly.
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7 NC I Floating.
9 NC I Floating
Frequency selection
10 FREQ I
Short to ground: 200kHz; 68kΩ: 400kHz; Open: 600kHz
RSS1 are the resistors connected to SNS1P,SNS1N. The two resistors must be equal and the
recommended value is 1kΩ.
A 2.2nF capacitor to ground is needed to bypass noise. If IPWM function is applied to ILIM1,
increase the capacitor value to 10nF. If current limiting function is not needed, please short ILIM1 to
ground.
VREF RSS2
ILIM2_SET = ×
RILIM2 RSNS2
VREF is the internal reference voltage 1.21V;
RSS2 are the resistors connected to SNS2P,SNS2N. The two resistors must be equal and the
recommended value is 1kΩ.
A 2.2nF capacitor to ground is needed to bypass noise. If IPWM function is applied to ILIM2,
increase the capacitor value to 10nF. If current limiting function is not needed, please short ILIM2 to
ground.
13 NC I Floating
Negative input of current sense amplifier. Connect an external current sense resistor between
17 SNS2N I
SNS2P and SNS2N. Current flows from SNS2P to SNS2N.
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Positive input of current sense amplifier. Connect an external current sense resistor between SNS2P
18 SNS2P I
and SNS2N. Current flows from SNS2P to SNS2N.
Connect a capacitor between BT2 pin and SW2 pin to bootstrap a voltage to provide the bias
20 BT2 PWR
voltage for high side MOSFET gate driver2.
Output of internal regulator to provide 10V voltage for the bias voltage of internal gate drivers.
24 VCC PWR
Connect a 1 µF ceramic capacitor from VCC to PGND pin.
Connect a capacitor between BT1 pin and SW1 pin to bootstrap a voltage to provide the bias
29 BT1 PWR
voltage for high side MOSFET gate driver1.
Negative input of current sense amplifier. Connect an external current sense resistor between
31 SNS1N I
SNS1P and SNS1N. Current flows from SNS1P to SNS1N.
Positive input of current sense amplifier. Connect an external current sense resistor between
32 SNS1P I
SNS1P and SNS1N. Current flows from SNS1P to SNS1N.
Thermal
For thermal dissipation. Connect to AGND or PGND.
Pad
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
Over operating free-air temperature range (unless otherwise noted)
Voltage range at FREQ, ILIM1, ILIM2, COMP, DT, FB, ITUNE -0.3 5.5 V
terminals (2) LD1, LD2 -0.3 12 V
BT1, HD1 to SW1 -0.3 12 V
BT2, HD2 to SW2 -0.3 12 V
BT1, BT2 -0.3 50 V
Operating Junction, TJ -40 150 °C
Temperature Range
Storage temperature range, Tstg -65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
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fSW Switching frequency RFREQ = 68kΩ (±10%) 360 410 460 kHz
INDICATION
tPG_deglitch PG signal deglitch time fsw = 200kHz 27 38.5 50 ms
ISINK_PG PG sink current VPG = 0.4 V 3.6 4.1 4.6 mA
High limit falling edge (PG from low
110%
to high)
High limit hysteresis (PG from high
5%
to low)
VOUT_PG VOUT power good threshold
Low limit rising edge (PG from low
90%
to high)
Low limit hysteresis (PG from high
5%
to low)
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LOGIC CONTROL
/CE internal pull down resistor 1 MΩ
PWM pin internal pull down
0.5 MΩ
RPD resistor
IPWM pin internal pull down
1 MΩ
resistor
/CE, PWM, IPWM input low
VIL 0.4 V
voltage
/CE, PWM, IPWM input high
VIH 1.2 V
voltage
Soft Start
tSS Internal soft-start time From /CE low to 90% VOUT 8 15 ms
THERMAL SHUTDOWN
Thermal shutdown temperature (1) 165 °C
TSD (1)
Thermal shutdown hysteresis 15 °C
(1) Guarantee by design
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D
8.1.1 Chip Enable (/CE) 0 100%
Where;
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SNS2P
SNS2N
SNS1N
SNS1P
SC8701
The IPWM signal should be in the range of 20kHz ~ 100kHz,
ILIM2
ILIM1
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When the IPWM signal is logic high, which means the duty
cycle is 100%, the current limit is then the ILIMx set value.
For the ILIMx pin which is controlled by IPWM signal, its filter
capacitor should still be connected to ground. If the IPWM SC8701
frequency is low, higher capacitance should be applied. For
COMP
example, 22nF capacitor is suggested for 20kHz frequency.
If real-time current control is not required, connect ILIMx
resistor to GND and float IPWM and ITUNE pins. 4.99k
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The inductor saturation current ISAT should be higher than The MOSFET RDS(ON) and input capacitor CISS impact power
input / output current with sufficient margin. efficiency directly. Typically, lower RDS(ON) MOSFET has
higher CISS. The RDS(ON) is related to conduction loss. Higher
RDS(ON) results in higher conduction loss, thus lower
efficiency and higher thermal dissipation; the CISS is related
9.3 Current sense resistor to MOSFET switch on/off time, and longer on/off time results
in higher switching loss and lower efficiency. The proper
The RSNS1 and RSNS2 are current sense resistors and
MOSEFT should be selected based on tradeoff between the
5mΩ ~ 20mΩ resistor value is recommended. RDS(ON) and CISS.
Higher resistor value leads to higher current limit accuracy Normally, if the output power is around 20W ~ 30W, the
but using higher resistor value in high current application MOSFET with around 10mΩ of RDS(ON) and lower than
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1000pF of CISS is recommended. If the output power is be monitored. If the dead time is insufficient, adjust dead
increased, the MOSFET with lower RDS(ON) and under time accordingly.
2000pF CISS is recommended. The highest CISS is suggested
not to exceed 3000pF. Q1 Q4
0R 0R
If high CISS MOSFET is selected, the switching on and off HD1 HD2
time become longer, then the dead time should be adjusted
with DT pin to avoid simultaneous turn on for both high side
and low side MOSFETs. NC NC
Q2 Q3
0R 0R
NC NC
9.5 Driver resistor and SWx snubber circuit LD1 LD2
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Packaging Information
QFN32L(0404x0.75-0.40)
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