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    DLD Final_23

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    abdullahwaris005

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    DLD Final_23

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    13 views2 pages

    DLD Final_23

    Uploaded by

    abdullahwaris005

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    University of Engineering and Technology, Taxila

    Computer Engineering Department


    Course Instructor: Dr. Noshina Ishaque
    FinalExam, 2nd Semester 2k23

    Subject: CP-106 Digital Logic Design (3) Time Allowed: 3 hrs.


    Marks: 50

    Question#1: CLO 2 Marks [10+10]

    (a) Derive the state table and the state diagram of the sequential circuit shown in Fig. 1
    By analyzing the state table and the state diagram, explain the function that the circuit performs .

    Fig 1

    (b) Optimize the following state table through state equivalence analysis.
    University of Engineering and Technology, Taxila
    Computer Engineering Department
    Course Instructor: Dr. Noshina Ishaque
    FinalExam, 2nd Semester 2k23

    Subject: CP-106 Digital Logic Design (3) Time Allowed: 3 hrs.


    Marks: 50

    Question#2: CLO 3 Marks [5+5+5+5]

    (a) Design three-bit ring counter by using appropriate flip-flops.


    (b) Design full adder by using following logic devices.
    (i) PLA (ii) Multiplexer (ii) Decoder

    Question3: CLO 1 Marks [4+4+2]

    The memory units are specified by the number of words times the number of bits per word.

    (a) How many address lines and input–output data lines are needed in each case?

    (i) 8K * 16 (ii) 2G * 8 (iii) 16M * 32 (iv) 256K * 64

    (b) Give the number of bytes stored in the memories listed in part a.

    ( c) Word number 64 in the memory of 1k words contains the binary equivalent of 40. List the
    10‐bit address and the 16‐bit memory content of the word.

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