Write the flow of current between source and drain
2. Define gate-to-body capacitance.
Gate-to-body capacitance is a key parasitic capacitance in MOSFETs (Metal- Oxide-Semiconductor Field-Effect Transistors). It represents the capacitance between the gate and the body (or bulk) terminal of the MOSFET.
This capacitance has no fundamental operation on the device but it has some impact on circuit performance. It affects the transistor's switching speed, power dissipation, and frequency response.
3. Outline latch-up. How can it be prevented?
Latch up is a condition in which the parasitic components give raise to the establishment of low resistance conducting paths between Vds and Vss with disastrous results. Prevention methods: An increase in substrate doping levels with a consequent drop. By introducing guard rings.
4. Define the bistability principle.
Static memories use positive feedback to create the bistable circuit – a circuit having two stable states that represents 0 and 1. The points A and B are stable operaion points ans its loop gain is smaller than unity. The cross coupling of two inverters result in a bistable circuit. Bistable circuit has two stable states each corresponding to a logic atate (0 or 1). The circuit can be used as a memory. A trigger is used to change the logic state.
5. Analyze the working of dynamic positive edge triggered register when clk=0. When clk=0, input data is sampled on storage node 1 with capacitance C. During this period the slave is in hold mode and the node 2 is in high impedance state. 6. Mention the properties of the Schmitt trigger.
It responds to a slowly changing input waveform with a fast transition time
at the output. The voltage transfer characteristics of the device displays different switching thresholds.
7. Develop a PRSG logic circuit for BIST.
8. Compare constant field scaling and constant voltage scaling.
Constant field scaling reduces device dimensions while keeping the
electric field constant across the transistor. This approach is also known as full scaling.
Constant voltage scaling, also known as voltage non-scaling, involves
reducing device dimensions while keeping the supply voltage Vdd constant.
9. Define stick diagram. Sketch stick diagram for 3 input NOR gate.
A stick diagram is a simplified representation of a VLSI layout that
shows the relative positioning of circuit components and interconnections without specifying exact dimensions or layer details. 10.Point out the set of design rules for layouts with 2 metal layers. Metal and diffusion have minimum width and spacing of 4λ. Polysilicon uses a width of 2λ. Polysilicon overlaps diffusion by 2λ with spacing of 1λ. Polysilicon and contacts have spacing of 3λ from polysilicon or contacts.
