Scribd Logo
Upload

Welcome to Scribd!

  • 1 views

    ps3_solutions

    Uploaded by

    huaiqian1997

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    ps3_solutions

    Uploaded by

    huaiqian1997
    1 views3 pages

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    1 views3 pages

    ps3_solutions

    Uploaded by

    huaiqian1997

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 3

    Problem Set #3 Solutions

    Brian DeHority
    October 2021

    1
    1a) When approximating the gate capacitance with the method discussed in
    class that matches the delay through several inverter stages with a single output
    capacitance, the value turns out to be around 160 fF. Per unit device width,
    this translates into 160 fF/[8*(16 um + 8um)]=0.83 fF/um.
    1b) Now that the value for the gate capacitance was found in part (a), the
    effective resistance can be found for the NMOS and the PMOS. The calculation
    is based on the simple RC model that was done in class. Each inverter has an
    FO4 delay, which makes the gate capacitance of the third inverter 16(16 um +
    8um)*(0.833fF) = 318 fF. From simulation, tPLH = 31.3 ps, and tPHL = 32.1
    ps. The resistances can be calculated by:
    tplh
    Rpf et = ×W
    Cg
    tphl
    Rnf et = ×W
    Cg
    This gives a PMOS resistance for unit device width of 6.3kΩµm and an NMOS
    resistance for unit device width of 3.2kΩµm
    1c) The simplest method of simulating diffusion capacitance can be found in
    section 5.4.4 in the textbook. The same schematic used for part a can be used
    here, but replacing the ’load’ inverter with a single transistor, and draining or
    charging its diffusion capacitance. However, there are other methods of getting
    the diffusion capacitance as well. Using the textbook method, the final values
    of drain capacitance for unit device width, all given in fF/um, are:

    PLH = 0.484

    NLH = 0.422
    PHL = 0.531
    NHL = 0.406
    And this agrees with the theoretical ratio between gate and drain capaci-
    tances of 1.5-2.

    1
    2
    Vdd = 1.2 V, and C = 100 fF, the expected energy dissipation is 144fJ. For a
    slew rate of 25 ps, the total energy was integrated to be
    Z
    E = i(t)dt × VDD = 163.1f J

    For a slew rate of 500 ps, the total energy was integrated to be 167.2 fJ. So the
    fraction of energy in the crowbar current was found to be
    163.1 − 144f J
    t = 25ps − − > = 11.7%
    163.1f J
    167.2 − 144f J
    t = 500ps − − > = 13.8%
    167.2
    The difference in these two scenarios is somewhat small, but can be ratio-
    nalized by seeing that a longer slew rate will increase the crowbar current, as
    both devices will be on for a longer period of time.

    3
    3a) The normalized inverters for the three stages are proportioned: 1um/0.5um,
    2w2 /W2 , and 2W3 /W 3. So the path effort can be calculated using the same
    method discussed in class: First we find the full path effort:
    500um 3W3 5W2
    F = × × = 555.56
    3W3 3W2 1.5W1
    Taking the nth root of the path effort gives the ideal path effort per stage, where
    n is the number of stages:
    √3
    555.56 = 8.22 = F1 , F2 , F3

    Then recalculating the widths, using this ideal path effort should give ideal
    widths:
    500um
    F3 = = 8.22
    3W3
    W3 = 20.27um
    3 ∗ 20.27
    W2 = = 2.47um
    3 ∗ 8.22
    τinv = Cg × 3Rnf et = 2 × 3 × 4 = 24p
    Delay = τinv × 8.22 × 3 = 591ps
    3b) The delay can be minimized by choosing a total of 7 stages, as

    D = N × F 1/N τinv

    2
    This makes the ideal path effort per stage of 2.46. So using this, we first find
    the sizes of the 4 inverters at the end of the path:
    500
    W7 = = 67.7um
    2.46 × 3
    67.7 × 3
    W6 = = 27.52um
    2.46 × 3
    27.52 × 3
    W5 = = 11.18um
    2.46 × 3
    11.18 × 3
    W4 = = 4.544um
    2.46 × 3
    4.544 × 3
    W3 = = 1.83um
    2.46 × 3
    1.83 × 3
    W2 = = 0.735um
    0.5 × 3
    And to check, the ideal width of the first stage should not have changed, keeping
    the ideal path effort:
    5 × 0.735
    f1 = = 2.46
    3 × 0.5
    And it works out!
    The final delay should be:

    D = 7 × 2.46 ∗ τinv = 414.39ps

    You might also like