VLSI Digital Signal Processing (ELEG5758)

TRAINING 1 MANUAL
Contents

LEARNING OUTCOMES AND OBJECTIVES:............................................................................................... 2

PART 1: FPGA DEVELOPMENT TOOLS AND BOARDS ............................................................................... 3
1.0 Overview: ...................................................................................................................................... 3
1.1 The FPGA Board for this Training and Other Development Boards: ............................................. 3
1.2 Xilinx’s FPGA Development Tools .................................................................................................. 4
1.2.1 Vivado Hardware Development Environment ....................................................................... 5
1.2.2 Vi�s So�ware Pla�orm Development Environment .............................................................. 5
Tasks: ............................................................................................................................................... 5
PART 2: FPGA DEVELOPMENT USING VIVADO/VITIS .............................................................................. 6
2.1 Overview ....................................................................................................................................... 6
2.2 Vivado/Vi�s Download and Installa�on ........................................................................................ 6
2.2.1 Vi�s Download ....................................................................................................................... 7
2.2.2 Vi�s Installa�on (Windows) ................................................................................................... 8
2.3 Crea�ng a New Project................................................................................................................ 11
2.4 Crea�ng/Adding a New Source File ............................................................................................ 15
2.5 Opening and Wri�ng the Hardware Descrip�on (HDL) Source File ............................................ 17
2.6 Simula�on of the Half-Adder Program ........................................................................................ 18
PART 3.0: A 4-BIT CARRY PROPAGATION ADDER (CPA) IMPLEMENTATION .......................................... 22
3.1 Overview ..................................................................................................................................... 22
3.2 The Full Adder Implementa�on .................................................................................................. 22
3.2 The 4-bit Carry Propaga�on Adder Implementa�on .................................................................. 23
3.1.1 Hardware Implementa�on ................................................................................................... 23
3.1.2 Simula�on of the Full Adder ................................................................................................ 27
3.1.3 Implementa�on, Bitstream Genera�on and Tes�ng ............................................................ 28
PART 4.0: ARITHMETIC AND LOGICAL UNIT (ALU) ................................................................................ 31
4.1 Crea�ng the Various Modules/Components: ............................................................................. 31
4.2 Connect the Various Modules/Components:.............................................................................. 35
4.3 Simula�on: .................................................................................................................................. 36
4.3 Implementa�on, Bitstream Genera�on and Tes�ng: .................................................................. 37
4.4 Hardware Implementa�on Results: ............................................................................................ 40

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LEARNING OUTCOMES AND OBJECTIVES:
At the end of this training, students are expected to:
• Know the FPGA development boards and tools.
• Get familiar with Xilinx’s Vivado tool and FPGA systems development.
 Create and implement a project in Vivado.
 Simulate projects using a test bench.
 Familiarise with the Vivado's block design feature.
 Familiarise with the FPGA development flow including the synthesis,
implementation (placement and routing), and bitstream generation.
• Learn how to implement and simulate the basic arithmetic primitives in Vivado.
 Half and full adder
 Fixed-point n-bit carry propagation adder.
 Fixed-point n-bit subtractor
• Learn how to implement and simulate higher arithmetic primitives in Vivado.
 Fixed-point n-bit multiplier
 Fixed-point n-bit divider
 Arithmetic and Logical Unit (ALU)
• Learn hardware implementation using block design features and available IPs
 Create block design, add, and connect the blocks (modules)
 Implement, generate the bitstream, and test the hardware.

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PART 1: FPGA DEVELOPMENT TOOLS AND BOARDS
1.0 Overview:
Field Programmable Gate Arrays (FPGAs) are semiconductor devices (ICs) that are based
around a matrix of configurable logic blocks (CLBs) connected via programmable
interconnects. FPGAs can be reprogrammed to desired application or functionality
requirements after manufacturing.
Figure 1.1 describes the architecture of FPGA consisting of the following:
- Configuration Logic Block: Used to implement the user’s logic and consists of LUT,
multiplexers, and flip-flops.
- Programmable interconnects – connects different CLBs.
- IO Blocks – Gives the input and output interfaces to the user or external devices.
- DSP blocks
- Block RAM

Figure 1.1: Basic FPGA architecture

1.1 The FPGA Board for this Training and Other Development Boards:
In this training, we are going to use Digilent’s Zedboard as shown in Figure 1.2. The board
featured several components such as LEDs, switches, USB UART, USB JTAG, HDMI, VGA,
Gigabit Ethernet port, power, Pmods, OLED, FMC, and soon. The board also contains a Zynq
7000 FPGA and DDR3 memory.
The other FPGA development boards used in various fields include the boards from AMD
Xilinx for example, PYNQ Z1, PYNQ Z2, Virtex 7, Spartan 6, VCU108, Kria (KV260/KR260)

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boards, Zybo boards, ZCU102, ZCU104, Alveo, and versal boards. Figure 1.3 shows the
overview of the FPGA boards produced by the AMD. Other vendors such as Intel also produce
their FPGA boards for example Cyclone V, Arria 10, Stratix, and Agilex V boards.
In this lab, students will be shown some samples of FPGA boards.

Figure 1.2: Digilent Zedboard Development Board

Figure 1.3: Various FPGAs provided by AMD Xilinx

1.2 Xilinx’s FPGA Development Tools

In this section students are going to learn about the several FPGA development tools.

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1.2.1 Vivado Hardware Development Environment
Vivado is the AMD i.e., Xilinx’s FPGA development tool. It is the design software for AMD
adaptive SoCs and FPGAs. It includes Design Entry, Synthesis, Place and Route, and
Verification /Simulation tools. The advanced features in Vivado design software help hardware
designers reduce compile times and design iterations, while more accurately estimating power
for AMD adaptive SoCs and FPGAs. Figure 2.1 shows the FPGA system development
process (flow). Hence, Vivado facilitates the process by providing the necessary
design, simulation/verification, and implementation tools for the hardware developments.

1.2.2 Vitis Software Platform Development Environment

For software development in the SoC type FPGAs (using ARM or Microblaze), Xilinx provides
the Software Development Kit (SDK) later renamed as Vitis. The Vitis Unified Software
Platform integrates all the tools required for both the hardware and the software developments.
This means that installing the Vitis Unified Software Platform will install both Vivado and Vitis
IDEs for you.
The AMD Vitis™ software platform is a development environment for developing designs that
includes FPGA fabric, Arm® processor subsystems, and AI Engines. The Vitis tools work in
conjunction with AMD Vivado™ ML Design Suite to provide a higher level of abstraction for
design development.
The Vitis software platform includes the following tools:
a. Vitis Embedded – For developing C/C++ application code running on embedded Arm
processors.
b. Compiler and simulators – For implementing designs using the AI Engine array.
c. Vitis HLS – For developing C/C++ based IP blocks that target FPGA fabric.
d. Vitis Model Composer – A model-based design tool that enables rapid design
exploration within the MathWorks Simulink® environment.
e. A set of open-source, performance-optimized library functions, such as DSP, Vision,
Solver, Ultrasound, BLAS, and many more, that can be implemented in FPGA fabric
or using AI Engines

Tasks:
Working with the help of the lab supervisor, answer the following questions.
1. Mention any three FPGA manufacturers and vendors you may know.
2. State the FPGA development tool and some of the FPGA boards for each manufacturer.
3. Which FPGA boards are more suitable for DSP and machine learning hardware?
4. Outline the functions of the features in Zedboard, which FPGA is featured in the board.
5. Identify similar features from the other boards provided to you in the lab.
6. Briefly describe the architecture of Zynq Ultrascale. Name any two Zynq Ultrascale
FPGA boards.
7. What is the major difference between Zedboard, Virtex7 evaluation kit, Zybo board,
PYNQ-z2, Kria KV260, and ZCU104 FPGA boards.
8. Briefly describe the architecture of Zynq 7000 SoC FPGA.

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PART 2: FPGA DEVELOPMENT USING VIVADO/VITIS
2.1 Overview
Figure 2.1 outlines the stages of FPGA hardware development (FPGA development flow). In
this lab part, we are going to get familiar with the Vivado environment and get acquainted with
the FPGA development using the Vivado tool. We will learn how to use Vivado to create and
implement an FPGA (hardware) system. We will first create and simulate a half-adder. We will
later implement and realize hardware on the board using the switches and the user LEDs on the
board.

Figure 2.1: Typical FPGA developement flow

2.2 Vivado/Vitis Download and Installation

Vivado and Vitis are downloaded from the AMD Xilinx’s download webpage. Since Vivado
2019 versions, Xilinx integrated Vivado into its Vitis Unified Platform. Hence by installing
Vitis, Vivado will automatically be installed. AMD provides two types of installers to support
your installation requirements for the Vitis software platform.
o AMD Unified Installer for FPGAs & Adaptive SoCs
o AMD Vitis Embedded Installer
The AMD Unified Installer contains almost everything. It includes the full-featured Vitis
software platform, the AMD Vivado™ Design Suite, and PetaLinux. You can choose which
components to install during the installation procedure. On the other hand, the AMD Vitis
Embedded Installer contains the tools for embedded development only. It contains the
embedded software development version of Vitis Unified IDE and the utilities like XSCT and
program_flash. After the installation, a license file needs to be uploaded if available. Students
can use a free (Web pack) Vitis/Vivado license which provides the basic but limited features.
An evaluation license is also provided for a limited duration.

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2.2.1 Vitis Download
• Goto https://www.xilinx.com/support/download.html
• Select Vitis (SW developer) and 2022.2 (the version we will use in this training)

Scroll down and study the various available download options (Web and SFD). For each
installer, AMD might provide different types of packages. The web installer only downloads
essential components according to your installation requirements to speed up the download
process. On the other hand, The Single File Download (SFD) provides a self-contained package
for AMD components.

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 • If you have enough space, download the Xilinx Unified Installer 2022.2 SFD (TAR/GZIP
- 89.4 GB), else download the Xilinx Unified Web Installer depending on your OS.

2.2.2 Vitis Installation (Windows)

1. Extract the download zip file. Open the Vitis Unified extracted folder.
2. Run the installer, xsetup, or xsetup.exe, which opens the Welcome page and extract the
installer package.

3. Click Next to open the Select Install Type page of the Installer.
4. If using web installer, enter your AMD user account credentials, and select Next.

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5. Select Download and Install Now only if using web installer.
6. Click Next to open the Accept License Agreements page of the Installer.
7. Accept the terms and conditions by clicking each I Agree check box.
8. Click Next to open the Select Product to Install page of the Installer.
9. Select Vitis and click Next to open the Vitis Unified Software Platform page of the
Installer.

10. Customize your installation by selecting design tools and devices (optional).
The default Design Tools selections are for standard Vitis Unified Software Platform
installations and include Vitis, Vivado, and Vitis HLS. You do not need to separately
install Vivado tools. You can also install Model Composer and System Generator if
needed.You can enable Vitis IP Cache to install cache files for example designs found
in the release. This is not required, but when selected, the files are installed at
<installdir>/Vitis/<release>/data/cache/xilinx. The default Devices selections are for
devices used on standard acceleration platforms supported by the Vitis tools. You can
disable some devices that might not be of interest in your installation.
11. Click Next to open the Accept License Agreements page of the Installer and accept as
appropriate.
12. Click Next to open the Select Destination Directory page of the Installer.
13. Specify the installation directory, review the location summary, review the disk space
required to ensure there is enough space, and click Next to open the Installation
Summary page of the Installer.

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14. Click Install to begin the installation of the software.
After a successful installation of the full Vitis unified software, a confirmation message
is displayed with a prompt to run the installLibs.sh script (sudo installLibs.sh). The
command installs necessary packages for the Vitis tools based on the OS of your
system. Note that this script is not required on Windows. Hence locate the script
at:<install_dir>/Vitis/<release>/scripts/installLibs.sh
Where <install_dir> is the location of your installation, and <release> is the installation
version.
15. To launch the Vitis software platform from Windows, do one of the following:
a. Launch from a desktop button or Start menu command.
b. From a Windows command shell, use settings64.bat: C:<VITIS_ INSTALL
_DIR>\VITIS\2022.2\settings64.bat, and launch: vitis

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2.3 Creating a New Project
• Create a folder “Vivado_projects” on the Desktop of your computer.
• Open Vivado by clicking its icon on the desktop.
• Click Create Project

• Click Next.
• Choose a location for your project and specify the project name as “Proj1_halfAdder”.
• check the “Create project subdirectory” check box.
• Click Next.

• Choose the “RTL Project” radio button, then click Next.

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• Click Next to create an empty project with no source code or constraint file.
• Click Boards
• Search “Zedboard”. If the board is not found, you may need to click the Refresh button
to update the board repository. Alternatively, you may add the board files directly.

• Check the board Status. If it shows an arrow, the board files are not installed, you
should click the arrow to install the board files. The Status now changes to a minus
sign (-).

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 • Select the board and click Next, the project summary is then displayed.

• Cross-check the summary and click Finish to create the project.

• The new project environment is opened.

Checkpoint:
Observe each of the following items in the Vivado project development environment and find
their functions.
1) Menu bar items 2) Project Manager 3) Sources Window
4) Project Summary 6) Settings 7) IP Catalogue
8) IP Integrator 9) Simulation 10) RTL Analysis
11) Synthesis 12) Implementation 12) Program and Debug

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2.4 Creating/Adding a New Source File
• Click the “+” icon in the source window to add a new source.

• Select “Add or create design sources” and click Next.

• Click “Create File” to create a new source file. If you already have the source file(s)
that you want to add to the project, you should click the “Add Files” to add the file(s)

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• Select “Verilog” as the File type and write “half_adder” as the File name.
• Leave “File location” as default (Local to Project). Click OK

• Enter the Module name and click OK

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 • Click Finish

2.5 Opening and Writing the Hardware Description (HDL) Source File
• In the Vivado environment, open the source Verilog file (half_adder.v). The file now
opens in the Window beside.

• Copy and paste the half-adder source provided.

• Click Save (the second left blue square icon).

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2.6 Simulation of the Half-Adder Program
To simulate the hardware described in the source program (RTL), we need to write a test bench
file and describe the simulation procedure. The simulation is achieved using the XSim
simulator in Vivado.

• From the source window, click “+” to add a simulation file.

• Select “Add or create simulation sources” and click Next.

• Same as you have done for the source file, click “Create File”.

• Name the file as “Half_Adder_tb”, click OK, then Finish

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• A module definition window opens, click OK.

• Click “Yes” on the pop-up menu that will appear. The testbench file will be added to the
project.

• Open the testbench file from “Simulation Sources”.

• Copy and paste the provided half adder test bench source.

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• Click Save tab.

• Click the “Run Behavioral Simulation” tab from the SIMULATION section in the Flow
Navigation. The Simulation Window opens and run for the first few nano seconds.

• To simulate for a specified time, enter the duration e.g., 10us, and click the right triangle.
Click the middle triangle to run the simulation to the completion. Click the left triangle
to refresh the simulation.

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Check point:
Re-run the simulation and validate the result as shown in the message Window. Run Synthesis
and open the synthesized circuit, verify if the generated circuit looks like a half adder circuit.

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PART 3.0: A 4-BIT CARRY PROPAGATION ADDER (CPA)
IMPLEMENTATION
In this part, we are going to implement a full adder circuit and then extend it to a 4-bit carry
propagation adder.

3.1 Overview
An n-bit carry propagation adder consists of n full adders with the carry-out of a full adder
serving as the carry-in of its proceeding full adder. The carry out of the last full adder is the
carry of the n-bit carry propagation adder. Figure 3.1 and Figure 3.2 shows a full adder and a
4-bit carry propagation adder respectively.

Figure 3.1: Full adder circuit

Figure 3.2: 4-bit carry propagation adder.

3.2 The Full Adder Implementation

• Create a new Project “Full Adder”.
• Import/Add the half-adder source from the previous project to the current project.
• Create a new source file and name it “full_adder”.
• Copy and paste the full adder source (full_adder.v) provided.
• Create a full adder simulation file (test bench)
• Simulate the test bench.

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3.2 The 4-bit Carry Propagation Adder Implementation
We are going to extend the created full adder to a 4-bit carry propagation adder. We will also
simulate the adder in the XSim simulator.

3.1.1 Hardware Implementation

• From the Flow Navigator, click Create Block Design
• Name the block design four_bit_CPA.
• Click OK

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• Double-click the created block design.

• Drag the full_adder module to the block design.

• Produce 4 duplicates of the full adder block in the block design by copying and paste.
• Right-click each pin of the block (except the CARRY pin) and select the “Make
External”.

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 • Connect the CARRY of each adder to the C_in of the next adder.
(i.e., Carry_adder0  C_in_adder1, Carry_adder1  C_in_adder2 and so on)

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• Click the circular arrow (No. 1) menu item to regenerate the layout.
• Click the tick box (No. 2) menu item to validate the design.

• Write-click the block design and click the “Create HDL Wrapper”.

• Choose “Let Vivado manage wrapper and auto-update”.

• Click OK

• Write-click the generated wrapper file and select the “Set as Top”.

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 • Double-click the four_bit_CPA wrapper source, read and understand the code.

3.1.2 Simulation of the Full Adder

• Create a simulation test bench “Four_bit_CPA_tb”.
• Copy and paste the test bench file provided to the created test bench source.
• In the simulation window, set the test bench as the top.
• Run the Simulation

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3.1.3 Implementation, Bitstream Generation and Testing
• Before running the implementation, we need to provide the constraint file.
• From the Source window, click the “+” to add and create a constraint file.
• Open the created constraint file.
• Copy and paste the provided constraint.

• Set the fa_C_in_0 pin to zero as shown below.

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• From the Flow Navigator window, click “Run Synthesis” under SYNTHESIS

• Open the synthesized design and observe how the LUTs are used.
• Open and check the utilization also.

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• From the Flow Navigator window, click “Run Implementation” under
IMPLEMENTATION
• Click “Generate Bitstream” under PROGRAM AND DEBUG to generate the
bitstream file.
• The bitstream file is located in “<project folder> \Full_Adder.runs\impl_1”
• Open Target and program the device.
• Use the switches as shown in the constraint file to set the numbers, the LED displays
the addition results.

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PART 4.0: ARITHMETIC AND LOGICAL UNIT (ALU)
In this section, we are going to create an ALU (Arithmetic and Logical Unit) on the Zedboard’s
FPGA. The ALU should be able to add, subtract, multiply, and divide as shown in the figure
below.

4.1 Creating the Various Modules/Components:

• Create a new project named “ALU”.
• Create a new empty source ALU_Control.v (ALU module to be used later)
• Copy and paste the provided ALU source.
• Create a new block design “ALU_bd”.

• Add the Adder IP by clicking the “+” in the block design window.
• Search and double-click the Adder/Subtracter IP to add to the block design.
• Double-click the added IP to configure it.
• Set the parameters in the Basic tab, as shown in the below figure.
• Make sure you select “Add” under the “Add Mode” and set the bit-width correctly (3).

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• Go to the Control tab, unselect the “Clock Enable (CE)
• Select the Carry Out (C_OUT), click OK.

• Select the c_addsub_0 IP (the added IP) in the block design and rename it to “Adder”
from the “Property Window”.

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• For adding a subtractor, copy and paste the adder IP.
• Double-click the pasted IP to configure it.
• Set the parameters in the Basic tab, as shown in the below figure.
• Make sure you select Subtract under the “Add Mode” and set the bit-width correctly.
• Click OK

• Search and add the Multiplier IP by clicking the “+” in the block design.
• Set the parameters in the Basic tab, as shown in the below figure.
• Check “Output and Control”, leave it as it is. Click OK
• Click OK

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• Search and add the Divider Generator by clicking the “+” in the block design.
• Set the parameters in the Basic tab, as shown in the below figure.
• Check “Output and Control”, leave it as it is. Click OK
• Click OK

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4.2 Connect the Various Modules/Components:
• Drag and drop the ALU module (created earlier) from the source to the block design.
• Connect the adder, subtracter, multiplier, and the divider to the dragged ALU module
as shown in the below figure.

[Note: the reset is not active low as indicated in the ALU_Controller IP].

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 • Right-click the rest of pins and click “Make external” to create the ports.\

4.3 Simulation:
• Create a test bench (ALU_tb.v).
• Copy and paste the provided test bench file to the ALU_tb.v created.
• Run the simulation and check the output.

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4.3 Implementation, Bitstream Generation and Testing:
• From Flow Navigator, click Generate Bitstream. The tool is going to go through the
Synthesis, implementation, and the generate bitstream stages automatically.

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• You can open the implemented design to check the utilization report and the device
placement.

• Before programming the FPGA, make sure the boot setting jumpers are set to zero
positions.

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• Click “Open Hardware Manager”, then “Open Target” and Auto Connect.

• Click Program device, then Program.

• Now you can use the switches as the inputs (A_in, B_in, and opcode), the LEDs will
be showing the results and the remainder.

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4.4 Hardware Implementation Results:
1. 7+4 = 11; in binary is 100+111 = 1011

2. 7-4 = 3; in binary is 111-100 = 0011

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3. 7x4 = 28; in binary is 111*100 = 11100

4. 7/4 = 1 remainder 3; in binary is 111/100 = 1 remainder 11

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