Digital Communication Lab Manual (5049B)

(Rev 1)

Diploma - 2021 Revision

Diploma in Electronics Engg / Electronics & Comm Engg

Prepared by:

Arjun P

Lecturer in Electronics Engg

GPTC Kottayam
 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 1

Active first order low pass filter

Aim: To set up an active first order low pass filter and plot its frequency response

Components and Equipments required: 741, 10k Resistor, 15k Resistor (or 20k Pot), 0.01 uF
Capacitor, Dual DC source, Signal Generator, DSO.

Theory:

Active filters are obtained from the basic op amp configurations by using a capacitance as one
of its external components. Due to the high input resistance and low output resistance of op
amps, they eliminate loading issues. LPF will attenuate frequencies > cut off frequency.

Since ZC = 1/sC = 1/jωC, the gain will be frequency-dependent in magnitude and phase. For
LPF , limitω→0 ZC =∞. In words, at low frequencies a capacitance tends to behave as an open
circuit compared with the surrounding elements.

Circuit Diagram:

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Procedure:

1. Wire up the circuit and apply a 2 Vpp Sine wave

2. Vary the frequency of sine wave from 100Hz to 10kHz in steps and note down the
output voltage. Find the gain Vo/Vs in each step
3. Plot the frequecy response in graph sheet, (20log(Vo/Vs) versus log(f))

Vs = 2Vpp

F(Hz) Vo( peak to peak Log(f) 20log(Vo/Vs)

Volts)

Result:

Plotted the Frequency response of Active LPF.

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 3

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 2

Active first order high pass filter

Aim: To set up an active first order high pass filter and plot its frequency response

Components and Equipments required: 741, 10k Resistor, 15k Resistor (or 20k Pot), 0.01 uF
Capacitor, Dual DC source, Signal Generator, DSO.

Theory:

Active filters are obtained from the basic op amp configurations by using a capacitance as one
of its external components. Due to the high input resistance and low output resistance of op
amps, they eliminate loading issues. HPF will attenuate frequencies < cut off frequency.

Since ZC = 1/sC = 1/jωC, the gain will be frequency-dependent in magnitude and phase. For
HPF , limit ω→∞ ZC =0. In words, at high frequencies a capacitance tends to behave as a short
circuit compared with the surrounding elements.

Circuit Diagram:

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 4

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Procedure:

1. Wire up the circuit and apply a 2 Vpp Sine wave

2. Vary the frequency of sine wave from 10 kHz down to 100 Hz in steps and note down
the output voltage. Find the gain Vo/Vs in each step
3. Plot the frequency response in graph sheet (20log(Vo/Vs) versus log(f))

Vs = 2Vpp

F(Hz) Vo( peak to peak Log(f) 20log(Vo/Vs)

Volts)

Result:

Plotted the Frequency response of Active HPF.

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 5

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 3

Active Band Pass Filter

Aim: To set up an active band pass filter and plot its frequency response

Components and Equipments required: 741, 330k Resistor (or 470k Pot), 15k Resistor (or 20k
Pot), 820 Ohm Resistor (or 1k Pot), 0.01 uF Capacitor, Dual DC source, Signal Generator, DSO.

Theory:

Active filters are obtained from the basic op amp configurations by using a capacitance as one
of its external components. Due to the high input resistance and low output resistance of op
amps, they eliminate loading issues.

A Band pass filter passes a particular band of frequencies with zero attenuation and attenuates
all other frequencies below and above this band. Multiple-feedback filters are commonly used
to realize band pass filter. Multiple-feedback filters utilize more than one feedback path. The
circuit is also called the Delyiannis-Friend filter, named after its inventors.

At low frequencies gain will be less, it increases to maximum at around centre frequency fo and
then gain falls off as frequency increases above fo. Lower cut off frequency fL = fo – Bandwidth/2
and upper cut off frequency fH = fo + Bandwidth/2, so that fH - fL = Bandwidth.

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 6

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Circuit Diagram:

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Procedure:

1. Wire up the circuit and apply a 1 Vpp Sine wave

2. Vary the frequency of sine wave from 100 Hz to 2 kHz in steps and note down the
output voltage. Find the gain Vo/Vs in each step.
3. At low frequencies gain will be less, it increases to maximum at around centre frequency
fo and then gain falls off as frequency increases above fo.
4. Plot the frequency response in graph sheet (20log(Vo/Vs) versus log(f))

Vs = 1Vpp

F(Hz) Vo( peak to peak Log(f) 20log(Vo/Vs)

Volts)

Result:

Plotted the Frequency response of Active BPF.

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 8

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 4

Sampling and Reconstruction circuit

Aim: To construct a simple sampling circuit and observe the waveform. Then reconstruct the
sine wave from its samples using a filter circuit.

Components and Equipments required: CD4016, 741, 10k Resistor, 1k Resistor, 1 uF Capacitor,
Dual DC source, Signal Generator, DSO.

Theory:

Sampling circuit is employed to sample an analog signal. Sampling theorem states that
the original signal can be faithfully reconstructed only if the sampling frequency is at least
double that of the highest frequency component in the sampled signal.

Analog switch CD 4016 is used to sample the analog signal which is a sine wave input. A
low frequency sine wave input which is the sampled signal is applied to pin 1 and a high
frequency square wave which is the sampling pulse is applied to pin 13. The sampled output is
obtained at pin 2. The reconstruction circuit consists of a unity gain op amp buffer and an RC
low pass filter having a cut off frequency slightly greater than the frequency of the analog input
signal.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Circuit Diagram:

Design:

Frequency of input sine wave = 100 Hz. To reconstruct the waveform from samples design a low
pass filter with cut off frequency of 150 Hz.

Now fo = 1/(2πR2C1).

And fo = 150 Hz. Select C1 = 1 uF. So R2 = 1.06 kΩ. Select R2 = 1 kΩ std or 1.5 kΩ std

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 10

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Procedure:

1. Wire up the circuit and apply a 2 Vpp 100 Hz Sine wave to pin 1 of CD 4016.
2. Apply a 5 Vpp 1 kHz square wave to pin 13 of CD 4016.
3. Observe sampled output at Pin 2 of CD4016.
4. Observe reconstructed waveform and note down the frequency. It should be same as
the input sine wave frequency.

Observed waveforms:

Sampled output

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Reconstructed sine wave with same frequency (100Hz) as input wavefom.

Result:

Set up a simple sampling and reconstruction circuit and observed the sampled and
reconstructed output waveforms.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 5

Delta Modulator circuit using 1 bit DAC

Aim: To construct a 1 bit delta modulator and observe the input and output waveforms.

Components and Equipments required: LM 324, 7474 D Flip Flop, 741 Op Amp, 10k pot, 10k
Resistor, 0.1 uF Capacitor, Dual DC source, Signal Generator, DSO.

Theory:

Delta modulation (DM) is a differential PCM scheme in which the difference between
the sampled signal and the reconstructed signal is encoded into a single bit. This single bit
indicates whether the present signal value is larger or smaller than the previous sample. The D
Flip flop is used to store the 1 bit value corresponding to previous bit. The LM324 IC is used in
the circuit as a comparator. The output of the comparator is fed to a sample and hold circuit
made by a D flip flop. Pulses at the output of D flip flop are made bipolar by an op-amp
comparator. Bipolar pulses are converted to analog signal before feeding to the comparator
using a RC low-pass filter. The modulating signal m(t) and its quantized approximation m(t) are
applied to the comparator. Comparator provides a high level output when m(t) > m(t) and it
provides low level output when m(t) < m(t).

The LM324 IC is used in the circuit as the comparator. The output of the comparator is
fed to a sample and hold circuit made by a D flip flop. The clock frequency to flip flop is selected
at the sampling rate. Output of D flip flop which varies between 5V for ‘1’ and 0V for ‘0’ are
made bipolar by a comparator made of 741 op-amp. These Bipolar pulses are fed to an RC low-
pass filter to reconstruct the sampled analog signal. 741 op-amp functions as 1 bit DAC which
converts 1 bit digital output of D Flip flop to a bipolar analog voltage. The filter output is fed to
the inverting terminal of LM324 comparator. The Delta Modulator output can be observed
either at the output of D Flip Flop or at the output of 741 op amp.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Circuit Diagram:

Procedure:

1. Wire up the circuit as shown and apply a 5 Vpp 100 Hz Sine wave to non inverting pin of
LM324.
2. Apply a 5 Vpp 10 kHz square wave to clock input of D Flip flop.
3. Observe the Delta modulator output on DSO.
4. Plot the waveforms.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Observed waveforms:

Delta Modulator Output (Blue waveform)

Yellow waveform corresponds to input sine wave

Result:

A Delta modulator circuit has been set up and waveforms observed.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 6

Binary Amplitude Shift Keying (BASK)

Aim: To construct a Binary Amplitude Shift Keying (BASK) modulator and observe the output
waveform.

Components and Equipments required: CD4016, BC107 transistor, 100 Ohm Resistor, 4.7k
Resistor, 10k Resistor, 33k Resistor, Dual DC source, Signal Generators, DSO.

Theory:

In BASK system, two analog signals having different amplitude levels are transmitted
corresponding to a binary input. When the binary input (here CLK signal) is high one signal with
a particular amplitude level is transmitted and when the binary input is low another signal with
a different amplitude level is transmitted.

In the circuit shown CD 4016 IC is used to multiplex two signals. 4 Vpp 1 kHz Sine wave is
applied to Switch B input of CD 4016. The same sine wave amplitude is made half by the
resistive divider circuit consisting of R3-R4, and applied to Switch A input of CD 4016. So that
when CLK signal is at logic high 4Vpp signal appears at the output and when the CLK input is at
logic low 2Vpp signal appears at the output. The CLK signal is the digital message signal and the
two sine waves are the carrier signals. The CLK is inverted using a transistor inverter circuit and
applied to Control pin of Switch A.

The BASK output can be observed across the 10k resistor R2.

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 16

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

BASK Modulator Circuit Diagram:

Procedure:

1. Wire up the circuit as shown and apply a 4 Vpp 1 kHz Sine wave and 100 Hz clock signal.
2. Observe the BASK Modulator output on DSO.
3. Plot the waveform.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Observed waveforms:

BASK Modulator Output

Result:

BASK modulator circuit has been set up and waveforms observed.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 7

Binary Frequency Shift Keying (BFSK)

Aim: To construct a Binary Frequency Shift Keying (BFSK) modulator and observe the output
waveform.

Components and Equipments required: CD4016, BC107 transistor, 4.7k Resistor, 10k Resistor,
33k Resistor, Dual DC source, Signal Generators, DSO.

Theory:

In BFSK system, two analog signals having different frequencies are transmitted
corresponding to a binary input. When the binary input (here CLK signal) is high one signal with
a particular frequency is transmitted and when the binary input is low another signal with a
different frequency is transmitted.

In the circuit shown CD 4016 IC is used to multiplex two signals. 4 Vpp 1 kHz Sine wave is
applied to Switch B input of CD 4016. And a 4Vpp 5 kHz Sine wave is applied to Switch A input
of CD 4016. So that when CLK signal is at logic high 4 Vpp 1 kHz signal appears at the output and
when the CLK input is at logic low 4Vpp 5 kHz signal appears at the output. The CLK signal is the
modulating signal and the two sine waves are the carrier signals. The CLK is inverted using a
transistor inverter circuit and applied to Control pin of Switch A.

The BFSK output can be observed across the 10k resistor R2

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 19

 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

BFSK Modulator Circuit Diagram:

Procedure:

1. Wire up the circuit as shown and apply 4 Vpp 5 kHz Sine wave, 4 Vpp 1 kHz Sine wave
and 100 Hz clock signal.
2. Observe the BFSK Modulator output on DSO.
3. Plot the waveforms.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Observed waveforms:

Result:

BFSK modulator circuit has been set up and waveforms observed.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Exp No: 8

Even parity code generator circuit to detect and correct error.

Aim: To design and construct an even parity code generator circuit and an even parity checker
circuit.

Components and Equipments required: 7486 XOR gate IC, Toggle switches (SPDT- Single pole
double throw), DC source.

Theory:

A Parity bit is an extra bit added to the transmitted binary message (message consisting of 1s
and 0s) to make the total number of 1s either odd or even. This is done to detect errors in the
received message signal. A Parity generator is a logic circuit that generates the parity bit from a
logical function of the input message bits. Parity generator is used in the transmitter side.

Even parity generators are used to produce an even number of 1s at the transmitter side. If the
number of 1’s in the binary message signal is odd, the even parity generator will add a 1 as the
parity bit, otherwise it will add a 0 as the parity bit. Here we have a 3 bit message signal and 1
parity bit.

So the 3 bit message along with the parity bit is transmitted to the destination. Parity checker is
used at the receiver end to detect parity errors in the received 4 bit signal. The output of Parity
checker is denoted as parity Error Check (PEC) bit. If parity error occurs PEC = 1 and if no error
occurs PEC = 0.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Parity Generator Design:

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Parity Generator Circuit:

Procedure:

1. Wire up the circuit as shown

2. Apply the input bit patterns A B C using the switches. When any switch is open a high (1)
is applied and when the switch is closed a low (0) is applied.
3. Observe the parity bit on LED D1. When LED turns ON parity bit is 1, otherwise parity bit
is 0.

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Parity Checker Design:

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 Digital Communication Lab – 5049B Prepared by:
Arjun P, Lr. in Electronics Engg

Parity Checker Circuit:

Procedure:

1. Wire up the circuit as shown

2. Apply the input bit patters A B C Pe using the switches. When any switch is open a high
(1) is applied and when the switch is closed a low (0) is applied.
3. Observe the PEC bit on LED D1. If LED turns ON there is an even parity error, otherwise
there is no even parity error.

Result:

An even parity code generator circuit and an even parity checker circuit have been set up and
outputs observed.

Dept. of Electronics Engg, GPTC Kottayam Rev 1 Page 26