International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169

Volume: 4 Issue: 4 573 - 576

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Implementation of AMBA AHB protocol using verilog HDL

Abhinandan Aggarwal Prof. (Dr.) Neelam Sharma

Dept. of Electronics and communication Engineering Dept. of Electronics and communication Engineering
Maharaja Agrasen Institute of Technology, IPU Maharaja Agrasen Institute of Technology, IPU
New Delhi, India New Delhi, India
abhi2094@gmail.com neelam_sr@yahoo.co.in

Abstract— Advanced Microcontroller Bus Architecture (AMBA) is a series of bus protocols provided by ARM. These include AHB, APB and
ASB. AMBA provides an on-chip communication standard for these buses to be used in high performance microcontrollers. In this paper we
have implemented the AMBA AHB (Advanced High-Performance Bus) which is used for high performance transfers among different modules
of the microcontroller. AHB supports efficient connection of processor, on chip memory, DMA and off chip external memories. AMBA AHB
system bus supports multiple bus masters and slaves. The design is implemented using Verilog HDL and simulated using ModelSim 6.4a.
Synthesis for the design is done using Xilinx ISE 14.4.

Keywords-AMBA;AHB;Arbitration;Burst; HDL ; Simulation;Synthsis;SOC; Verilog;

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I. INTRODUCTION II. BUS INTERCONNECTIONS

In an SOC multiple blocks of IPs have to communicate and An AHB system consists of multiple masters from which
this is achieved by well-defined communication protocols. address and data signals are selected. The AMBA AHB bus
They are of great importance as they can have a great impact protocol is designed to be used with a central multiplexer
on the systems performance. Some of the popular protocols interconnection scheme. In this all bus masters drive out the
used in the industry include PCI, I2C, SPI, AMBA etc. address and control signals indicating the transfer they wish to
perform and the arbiter determines which master has its
In this paper we have implemented a widely used industrial address and control signals routed to all of the slaves. A
protocol AMBA AHB. ARM’s AMBA specification defines an central decoder is also required to control the read data and
on chip communication standard for high performance systems.
response signal multiplexor, which selects the appropriate
AMBA is today the de facto standard for processors as it is
signals from the slave that is involved in the transfer.
well documented and can be used without any royalties. It is
widely used in RAM controllers, DMA controllers and SOCs. Figure 2 shows the interconnections between 3 masters and 4
slaves.
AHB sits above APB and implements the features required for
high performance which are:
 Burst Transactions
 Split Transactions
 Single clock edge operation
 Non – tristate bus implementation.
 Pipelined operation

AHB consists of multiple masters from which one is selected at

a time using the arbiter. Decoder is used to select one among
the multiple slaves that can be addressed.
Figure 1. Shows how a typical AMBA based system looks like.

Figure 1 AMBA based system

Figure 2 Interconnections

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IJRITCC | April 2016, Available @ http://www.ijritcc.org
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 4 573 - 576
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 HSIZE[2:0]: Indicates the size of transfer.
 HBURST[2:0]: Indicates the kind of burst transfer.
III. AHB OPERATION  HPROT[2:0] : It is a protection control signal. In this
paper it is considered to have a constant value.
As seen in figure 2 AHB consists of multiple masters and In burst transfers the subsequent addresses are calculated by
the master according to the size of transfer, also the addresses
slaves, which are selected using arbiter and decoder
are required to be size aligned. Bursts should be such that they
respectively. An AHB transfer starts when a master sends a do not cross 1kB address boundaries.
request to the arbiter for the bus. The arbiter uses a predefined Apart from these signals a few auxiliary signals required by
priority algorithm to arbitrate among the requests from the master to get information about address, control and data to
different masters. After selecting a particular master it then be sent are given to it.
grants the bus to that master.
The master which is granted the bus can now initiate
the transfer. It starts the transfer by driving the address and B. AHB Arbiter
control signals. These provide various information about the Arbiter is used to select a particular master among the
address and the kind of operation (these will be discussed in a different masters that are currently requesting for the bus. A
following section). The master can also perform burst fixed priority algorithm is used here to arbitrate among the
transfers. There are two kinds of burst transfers that it can different requesting masters. In this algorithm the master are
perform incremental or wrapping burst transfers. given a fixed priority and the master having the highest
priority among the currently requesting masters is given the
Each transfer consists of the following two cycles: grant to the bus. It also asserts the corresponding HMASTER
 One address and control cycle signal for the granted master in the next cycle, which is used
 One or more data cycles by the multiplexer to select the signals of the selected master
as shown in figure 2. HSPLITx signal is used by the arbiter
Slaves can insert wait states for sampling data but address give back grant to a master which had been previously
should be sampled at the same cycle. This can be done using removed due to a split response by a split capable slave.
the HREADY signal by the slave. When low this signal During a burst transfer the master need not hold the
indicates the insertion of wait states by the slave. Slave can HBUSREQx signal as the arbiter will arbitrate again only after
also reflect the status of the transfer using the HRESP[1:0] the current burst transfer has completed or if the slave has
signal. Using this slave can provide OKAY, ERROR, RETRY issued a split response.
AND SPLIT responses. A master can also assert the HLOCKx signal along with
the HBUSREQx signal which would indicate the arbiter to
perform a locked transfer and prevent it from granting the bus
IV. AHB COMPONENTS to any other master. The arbiter indicates this by asserting the
HMASTLOCK signal.
AMBA AHB consists of the following two global signals
which are same for all the components: C. AHB Slave
 HCLK: this is the clock signal. All operations are
Slave responds to the transfers that are initiated by the
performed at the positive edge of this clock.
master. As multiple slaves are possible they are selected by
 HRESETn: this is an active low reset. It is asserted
using the HSELx signal from the decoder. They are selected
asynchronously and de-asserted synchronously.
on the basis of HADDR by the decoder. A slave has to be
The components of an AHB system are:
allocated for a minimum of 1kB addresses so that address
A. AHB Master boundaries are not crossed during a burst transfer.
Master is the component that initiates the transfer. It sends Slave also provides the response for a transfer, it uses
the request to the arbiter using the HBUSREQx singal and then HREADY signal to indicate wait states. A transfer can also be
starts the transfer after receiving the grant from the arbiter this aborted by slave but a master can never cancel a transfer once
is done by using the HGRANTx signal. it has started.
The transfer is performed in two phases the address phase HRESP [1:0] signal is used by the slave to provide OKAY,
and the data phase. The address phase is a one cycle long phase ERROR, RETRY or SPLIT responses. OKAY can be
in which the address and the control signals are sent this is provided in a single cycle but the others are two cycle
performed at the start of the transaction after this the data phase responses where in the first cycle HREADY is kept low with
is started. In each cycle of the data phase the address of the the corresponding response on HRESP and in the second cycle
next data to be transferred is sent, this provides the pipelined HREADY is made high keeping the HRESP same. This helps
operation in AHB which makes it a high performance protocol. the master to flush the pipeline.
The control information sent with the address includes:
 HTRANS[1:0]: Provides the transfer type which can
be IDLE , BUSY , SEQ , NON-SEQ . The first D. AHB Decoder
transfer in all burst transfers is NON-SEQ and the Decoder is used to select the slave which is to be used in
remaining are SEQ. the transfer. It uses HADDR to select the slave using HSELx
 HWRITE: High for write transfer and low for read signal. This is also used to control the read data mux.
transfer.
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IJRITCC | April 2016, Available @ http://www.ijritcc.org
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 4 573 - 576
______________________________________________________________________________________
E. AHB Multiplexers incremented by 4, for a halfword incremented by 2 and by 1 for
In AHB address and control, write data and read data a byte transfer.
multiplexers are used. Address and control mux and write data Figure 5 shows the operation for a burst 4 operation for a
word transfer followed by a burst 8 operation for a halfword
mux are controlled by HMASTER signal from the arbiter and
transfer.
read data mux is controlled by HSELx from the decoder.

V. SIMULATIONS

A. Single master operation

Figure 3 shows the operation of AHB for a single master
and slave. The first transaction is an incremental burst 4 write
followed by an incremental burst 8 write operation, which is
then followed by an incremental burst 8 read operation. The
response to this is given as an error response at the 7th cycle.

Figure 5 Incremental burst 4 and 8

Wrapping bursts are special kinds of burst in which the

address is wrapped around the address boundaries. These are
used in cache line fills where the cache line is filled by the
master. The address boundary in a wrapping burst can be
calculated as:
(No. of Beats) * (size of transfer)
Where beats is the wrapping length (i.e. 4, 8 or 16) and size
is given by the no. of bytes in the transfer.
So, for a wrap 8 of word sized transfer the address
Figure 3 Single master operation boundary would be at 8 * 4 = 32 byte boundary.
B. Multi master simple write operation The expected waveform for such a transfer is shown in figure
6. As seen in the figure the address is wrapped after 0x3C i.e. at
Figure 4 shows the simulation for a single master simple the 32 byte boundary to 0x20.
write operation. As shown in the figure master 1 being at the
highest priority gets the grant through the arbiter. An
undefined length incremental burst is used as the operation in
this simulation.

Figure 6 Wrap 8 operation

The waveform for such a transfer is shown in the figure 7

which shows the same result.

Figure 4 Multi master incremental write operation

C. Burst operations
AHB has the capability of performing different kinds of
burst operations. The burst operations available are:
 Single burst
 Undefined length incremental burst (as shown in
figure 4)
 Incremental burst of lengths 4, 8, and 16.
Figure 7 Wrap 8 waveform
 Wrapping burst of lengths 4, 8 and 16.
These are selected using the HBURST[2:0] signals. In any
burst transfer the subsequent addresses are calculated using the
HSIZE by the master. For a word transfer address is
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IJRITCC | April 2016, Available @ http://www.ijritcc.org
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International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 4 Issue: 4 573 - 576
______________________________________________________________________________________
VI. SYNTHESIS ARM processor and among the different components
The complete design with 3 masters, 4 slaves, arbiter, connected to it.
decoder, address mux, write and read data mux was REFERENCES
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Further this design can be extended to be used in a
complete system where it can be modified to be used with an

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