Max 96724

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MAX96724/F/R Quad Tunneling GMSL2/1 to CSI-2 Deserializer
General Description Benefits and Features

The MAX96724/F/R deserializer converts four GMSL™2/1 ● Automotive Grade High Speed Link
inputs to 1, 2, or 4 MIPI D-PHY or C-PHY outputs. The de- • -21.0dB at 3.0GHz (6Gbps) Max Insertion Loss
vice allows simultaneous transmit bidirectional transmis- • -19.5dB at 1.5GHz (3Gbps) Max Insertion Loss
sions over 50Ω coax or 100Ω STP cables that meet the • Auto Adapt for Changes in Channel Conditions
GMSL channel specification. Contact the factory for the • Operates at -40°C to +105°C Ambient
GMSL supporting collateral. ● Quad Independently Configurable GMSL Inputs
Up to four remotely located sensors can be supported • 6/3Gbps GMSL2 and 3.12Gbps GMSL1 Link-Rates
using industry-standard coax or STP interconnects. Each • 187.5Mbps/1Mbps (GMSL2/1) Reverse Link-Rates
GMSL2 serial link operates at a fixed rate of 3Gbps or • Support for Mixed GMSL2/1 Pixel and Tunnel
6Gbps in the forward direction and 187.5Mbps in the re- Inputs
verse direction. The MAX96724/F/R supports both ag- ● 2x4 or 4x2 Lane MIPI CSI-2 v1.3 Outputs
gregation and replication of video data, enabling streams • MIPI D-PHY v1.2 Rated at 2.5Gbps/Lane
from multiple remotely located sensors to be combined • C-PHY v1.0 Rated at 5.7Gbps/Lane
and routed to one or more of the available CSI-2 outputs. • Aggregation and Replication Functions
Table 1. Typical Maximum Cable Length • 16/32 Virtual channel support for D-PHY/C-PHY
3.2mm Ø 2.7mm Ø 100Ω ● Auto D-PHY (Imager) to C-PHY (SoC) Conversion
50Ω 50Ω Shielded ● Reference over Reverse (RoR) Clocking
Coax, Coax, Twisted ● Bidirectional Reverse Channel Supports
Foam Solid Pair, • 9 x Configurable GPIOs
Dielectric Dielectric AWG26
• 2 x I2C Ports, up to 1Mbps
Attenuation at 3GHz
0.9dB/m 1.6dB/m 1.8dB/m ● ASIL-B Compliant (MAX96724/F)
(Typ, Room Temp)
● Ease of Use Features
Attenuation at 3GHz
1.1dB/m 2.0dB/m 2.2dB/m ● Reduce BOM and Space Savings
(Max, Aged, +105°C)
• Small 8x8mm TQFN Standard and Side-Wettable
GMSL Fwd/Rev Data Typical Maximum Cable Length at • Industry's Smallest Power-over-Coax (PoC)
Rate +105°C (m)
3Gbps/187.5Mbps 20 10 11
6Gbps/187.5Mbps 15 9 8
Applications
● High-Resolution Camera Systems
● Advanced Driver Assistance Systems (ADAS)
Ordering Information appears at end of datasheet. 19-101575; Rev 4; 1/23
© 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2023 Analog Devices, Inc. All rights reserved.
Simplified Block Diagram
GMSL2 – TUNNEL MODE MIPI CSI-2 v1.3

MAX96717F COAX OR STP (3Gbps)
SIOA
Serializer
D-PHY v1.2
PORT A OR
GMSL2 – PIXEL MODE C-PHY v1.0
MAX96717R COAX (3Gbps)
Serializer SIOB
System on a Chip
MAX96724/F/R
MIPI CSI-2 v1.3 (SOC)
GMSL1 – PIXEL MODE
COAX OR STP
MAX96705
Serializer SIOC
D-PHY v1.2
PORT B OR
GMSL2 – TUNNEL MODE C-PHY v1.0
COAX OR STP (6Gbps)
MAX96717/K
SIOD
Serializer
DESERIALIZER
I2Cx2 and GPIO
www.analog.com Analog Devices | 2

TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
56-pin TQFN-SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
56-pin TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAX96724 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Control Channel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Host-to-Peripheral Main I2C and Pass-Through I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C Write Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Read Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Advanced GMSL User Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
GMSL2 Reverse Channel Serial Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
GMSL1 Serial Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
C-PHY Possible ∆VCPTX and ∆VOD Distortions of Single-Ended HS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
C-PHY Ideal Single-Ended and Resulting Differential High-Speed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
GMSL2 Video Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GMSL2 GPI-to-GPO Delay and Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GMSL1 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GMSL1 Power-up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GMSL1 Video Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GMSL1 GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cabling Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GMSL2 Bandwidth Information and Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

TABLE OF CONTENTS (CONTINUED)

GMSL2 Minimum Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AEQ (Automatic Adaptive Equalization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GMSL2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Tunneling vs. Pixel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Video Pipes, Aggregation, and Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Vertical and Data Enable or Data Valid Sync Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
D-PHY to C-PHY Packet Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Control Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General Purpose Inputs and Outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Link Error Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
GMSL1 Backwards Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Video PRBS Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RoR (Reference over Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CFG Latch at Power-up Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Multifunction Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power-Up and Link Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Link and Video Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
GMSL2 Link Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Video Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Error and Fault Condition Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
GPIO Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
EMB8 — ERRB Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Functional Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MAX96724/F/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

LIST OF FIGURES
Figure 1. I2C Write Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 2. I2C Read Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3. GMSL2 Serial Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. GMSL1 Serial Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. C-PHY Possible ∆VCPTX and ∆VOD Distortions of Single-Ended HS Signals . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6. C-PHY Ideal Single-Ended and Resulting Differential High-Speed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. GMSL2 Video Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. GMSL2 GPI-to-GPO Delay and Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. GMSL1 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. GMSL1 Power-up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. GMSL1 Video Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. GMSL1 GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. Video Frame Format for Bandwidth Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. Pixel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. Tunneling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Video Pipes and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. MAX96724/F/R Video Pipe Example with Partial FCFS Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. GMSL2 Memory Reading and Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. I2C Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Configuration Pin Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. GMSL2 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LIST OF TABLES
Table 1. Typical Maximum Cable Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5. Forward- and Reverse-Link Bandwidth Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6. Control Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. CFG0 Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. CFG1/MFP6 Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. MFP Pin Function Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Absolute Maximum Ratings

(All voltages with respect to ground.) ........................................... DA/B_P/N, CKA/B/C/FP/N (Note b) ....... -0.3V to (VTERM + 0.1V)
VDDIO .................................................................... -0.3V to +3.9V DA_P/N, CKA/CP/N (Note b) ................. -0.3V to (VTERM + 0.1V)
VDD18 .................................................................... -0.3V to +2.0V XRES, X2 ................................................ -0.3V to (VDD18 + 0.3V)
VDD........................................................................ -0.3V to +2.0V All Other Pins (Note c) ............................ -0.3V to (VDDIO + 0.3V)
VTERM ................................................................. -0.3V to +1.32V Continuous Power Dissipation, Multilayer Board (Note
CAP_VDD ............................................................. -0.3V to +1.2V d) .....................................................................................2619mW
SIO_ (Active State) (Note a) .................. (VDD18 - 1.1V) to VDD18 Storage Temperature Range ..............................-40°C to +150°C
SIO_ (Inactive State) (Note a) ............................... -0.3V to +1.1V Soldering Temperature (reflow) ........................................ +260°C
Note a: Active state means the device is powered-up and not power-down mode. Inactive means the device is not in power-down
mode.
Note b: Specified maximum voltage or 1.36V, whichever is lower
Note c: Specified maximum voltage or 3.9V, whichever is lower.
Note d: Derate 47.6mW/°C above TA = +70°C. Maximum dissipation is determined using specified θJA and assuming maximum
acceptable die temperature of +125°C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
56-pin TQFN-SW
Package Code T5688Y+6C
Outline Number 21-100046
Land Pattern Number 90-100048
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 25
Junction to Case (θJC) 4
56-pin TQFN
Package Code T5688+6C
Outline Number 21-0135
Land Pattern Number 90-100041
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 25
Junction to Case (θJC) 4
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(VTERM = 1.14V to 1.26V, VDD18 = 1.7V to 1.9V, VDD = 0.95V to 1.05V or VDD = 1.14V to 1.26V, VDDIO = 1.7V to 3.6V, TA = -40°C to
+105°C, EP connected to PCB ground, typical values are at VTERM = 1.2V, VDD18 = VDDIO = 1.8V, VDD = 1.0V, TA = +25°C, unless
otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ELECTRICAL CHARACTERISTICS / GMSL2 REVERSE CHANNEL SERIAL OUTPUTS — (Figure 3)
Output Voltage Swing
VO RL = 100Ω ±1% 190 250 310 mV
(Single-ended)
Output Voltage Swing RL = 100Ω ±1%
VODT 380 500 620 mV
(Differential) peak-to-peak differential voltage
Change in VOD between
Complementary Output
States
ΔVOD |
RL = 100Ω ±1%, VOD(H) − VOD(L) | 25 mV
Differential Output RL = 100Ω ±1% VDD18 - VDD18 - VDD18 -

VOS V
Offset Voltage offset voltage in each output state 0.45 0.3 0.15
Change in VOS between
Complementary Output
States
ΔVOS |
RL = 100Ω ±1% VOS(H) − VOS(L) | 25 mV
Termination Resistance
RT Any Pin to VDD18 50 55 60 Ω
(Internal)
DC ELECTRICAL CHARACTERISTICS / GMSL1 REVERSE CHANNEL SERIAL OUTPUTS — (Figure 4)
Forward channel HIM disabled 30 70
Differential High Output
disabled
Peak Voltage V(SIO_P) - VRODH mV
STP mode HIM enabled 50 110
V(SIO_N)
RL=100Ω
Forward channel HIM disabled -70 -30
Differential Low Output
disabled
Peak Voltage V(SIO_P) - VRODL mV
STP mode HIM enabled -110 -50
V(SIO_N)
RL=100Ω
Forward channel HIM disabled 30 70
Single-Ended High disabled
VROSH mV
Output Peak Voltage coax mode HIM enabled 50 110
RL=100Ω
Forward channel HIM disabled -70 -30
Single-Ended Low disabled
VROSL mV
Output Peak Voltage coax mode HIM enabled -110 -50
RL=100Ω
Differential Output
VDD18 -
Offset Voltage (V(SIO_P) VOS STP mode VDD18 V
0.3
+ V(SIO_N))/2
Termination Resistance
RT Any Pin to VDD18 50 55 60 Ω
(Internal)
DC ELECTRICAL CHARACTERISTICS / C-PHY and D-PHY LP TRANSMITTER
Thevenin High-Level
VOH 0.95 1.2 1.3 V
Output Voltage
Thevenin Low-Level
VOL -50 50 mV
Output Voltage
Output Impedance ZOLP 110 Ω

Electrical Characteristics (continued)

DC ELECTRICAL CHARACTERISTICS / D-PHY HS TRANSMITTER
HS Transmit Static
VCMTX 150 200 250 mV
Common-Mode Voltage
VCMTX Mismatch when
Output is Differential-1
or Differential-0
|ΔVCMTX(1, 0)| ∆VCMTX(1,0) = (VCMTX(1) - VCMTX(0)) / 2 5 mV
HS Transmit Differential
Voltage |VOD| 140 200 270 mV
VOD Mismatch when

Output is Differential-1
or Differential-0
|ΔVOD| 14 mV
HS Output High Voltage VOHHS 360 mV

Single-Ended Output
ZOS 40 50 62.5 Ω
Impedance
Single-Ended Output
∆ZOS 10 %
Impedance Mismatch
DC ELECTRICAL CHARACTERISTICS / C-PHY HS TRANSMITTER
HS Transmit Static
VCPTX ZID = 100Ω 175 310 mV
Common-Point Voltage
VCPTX Mismatch when
Output is in any of the
Six High-Speed States
|ΔVCPTX(HS)| (Figure 5) 9 mV
Voltage of the
Differential Strong 1 and |VOD| strong ZID = 100Ω (Figure 6) 300 mV
Strong 0
Voltage of the
Differential Weak 1 and |VOD| weak ZID = 100Ω (Figure 6) 97 mV
Weak 0
VOD Mismatch Between
the Absolute Values of
the Differential Strong 1
and Strong 0 Output
Voltages in any of the
|ΔVOD| (Figure 5) 17 mV
Six Possible High-

Speed States
HS Output High Voltage VOHHS ZID =100Ω 425 mV
Single-Ended Output
ZOS 40 50 60 Ω
Impedance
Single-Ended Output
ΔZOS 10 %
Impedance Mismatch
DC ELECTRICAL CHARACTERISTICS / I/O PINS
0.7 x
High-Level Input Voltage VIH V
VDDIO


0.3 x
Low-Level Input Voltage VIL V
VDDIO
High-Level Output VDDIO -
VOH IOH = -4mA V
Voltage 0.4
Low-Level Output
VOL IOL = 4mA 0.4 V
Voltage
All pullup/pulldown devices disabled.
Input Current IIN 1 μA
VIN = 0V to VDDIO
Input Capacitance CIN 3 pF
Internal Pullup/Pulldown 40kΩ enabled 40 kΩ
RIN
Resistance 1MΩ enabled 1 MΩ
DC ELECTRICAL CHARACTERISTICS / OPEN-DRAIN PINS
0.7 x
VDDIO
0.3 x
VDDIO
Low-Level Open-Drain
VOL IOL = 4mA 0.4 V
Output Voltage
All pullup/pulldown devices disabled.
Input Current IIN 1 μA
VIN = 0V to VDDIO
Internal Pullup 40kΩ enabled 40 kΩ
RPU
Resistance 1MΩ enabled 1 MΩ
DC ELECTRICAL CHARACTERISTICS / PWDNB INPUT
0.7 x
VDDIO
0.3 x
VDDIO
Input Current IIN VIN = 0V to VDDIO 6 μA
Internal Pulldown
RPD 1 MΩ
Resistance
DC ELECTRICAL CHARACTERISTICS / PUSH-PULL OUTPUTS
High-Level Output VDDIO -
VOH IOH = -4mA V
Voltage 0.4
Low-Level Output
VOL IOL = 4mA 0.4 V
Voltage
DC ELECTRICAL CHARACTERISTICS / LINE FAULT DETECTION INPUTS
VO0 LMN0, LMN2 1.25
Open Pin Voltage V
VO1 LMN1, LMN3 0.75
DC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK INPUT (CRYSTAL) (X1/OSC, X2)
X1 Input Capacitance CIN_X1 3 pF


Internal X2 Limit
RLIM 1.2 kΩ
Resistor
Internal Feedback
RFB 10 kΩ
Resistor
Transconductance gm 28 mA/V
DC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK INPUT (EXTERNAL INPUT ON X1/OSC, X2 UNCONNECTED)
High-Level Input Voltage VIH 0.9 V
Low-Level Input Voltage VIL 0.4 V
Input Impedance RIN 10 kΩ
DC ELECTRICAL CHARACTERISTICS / POWER SUPPLY CURRENT — GMSL2 MODE
4x 3Gbps input, VTERM = 1.26V 17 25
4x 2.45Gbps VDD18 = 1.9V 280 325
payload input,
PRBS24, VDD = 1.05V 197 625
1x 4-lane D-PHY,
2500Mbps/lane VDD = 1.26V 191 600
IDD1 4x 6Gbps input, VTERM = 1.26V 19 35
4x 5.2Gbps VDD18 = 1.9V 280 325
payload input,
PRBS24, VDD = 1.05V 244 675
1x 4-lane C-PHY,
5700Mbps/lane VDD = 1.26V 228 650
(MAX96724)
Supply Current Replicate Mode, VTERM = 1.26V 34 50 mA
4x 3Gbps input, VDD18 = 1.9V 280 325
4x 2.45Gbps
payload input, VDD = 1.05V 224 675
PRBS24,
2x 4-lane D-PHY, VDD = 1.26V 218 650
2500Mbps/lane
IDD2 Replicate Mode, VTERM = 1.26V 37 70
4x 6Gbps input, VDD18 = 1.9V 280 325
4x 5.2Gbps
payload input, VDD = 1.05V 272 725
PRBS24,
2x 4-lane C-PHY,
5700Mbps/lane VDD = 1.26V 265 700
(MAX96724)
VDDIO Supply Current Per toggling GPIO, VDDIO = 1.8V 44
IDDIO μA/MHz
(Note 3) CL = 20pF VDDIO = 3.3V 81


DC ELECTRICAL CHARACTERISTICS / POWER SUPPLY CURRENT — GMSL1 MODE
4x 3.12Gbps input, VTERM = 1.2V 16 25
4x 2.45Gbps VDD18 = 1.8V 155 200
payload input,
IDD1 VDD = 1.05V 113 550
PRBS24,
1x 4-lane D-PHY,
2500Mbps/lane VDD = 1.26V 107 525
Supply Current Replicate Mode, VTERM = 1.2V 29 50 mA
4x 3.12Gbps input, VDD18 = 1.8V 155 200
4x 2.45Gbps
IDD2 payload input, VDD = 1.05V 138 575
PRBS24,
2x 4-lane D-PHY, VDD = 1.26V 132 550
2500Mbps/lane
VDDIO Supply Current Per toggling GPIO, VDDIO = 1.8V 44
IDDIO μA/MHz
(Note 3) CL = 20pF VDDIO = 3.3V 81
DC ELECTRICAL CHARACTERISTICS / POWER-DOWN CURRENT
TA = +25°C <1
VTERM = 1.26V
TA = +105°C <1
TA = +25°C <1
VDD18 = 1.9V
TA = +105°C 14
Power-Down Current IDD μA
TA = +25°C <1
VDD = 1.26V
TA = +105°C <1
TA = +25°C 7
VDDIO = 3.6V
TA = +105°C 7
AC ELECTRICAL CHARACTERISTICS / GMSL2 FORWARD CHANNEL
From power-up, one-shot reset, or rising
edge of PWDNB to rising edge of LOCK.
Lock Time tLOCK2 45 60 ms
(Note 9, Note 10)
(Figure 22)
Time from GMSL2 video packets at SIO_
0.1ms +
Maximum Video to valid packets at the CSI-2 output
tVIDEOSTART (6600 x ms
Initialization Time (assumes link locked and registers
tPCLK)
configured).
1 video
Time from the first pixel in SIO_ to CSI-2 line +
Maximum Video Latency tVL s
output. (Figure 7) (128 x
tPCLK)
PWDNB Hold Time tHOLD_PWDNB Minimum time to reset the device. 1 μs
AC ELECTRICAL CHARACTERISTICS / GMSL2 REVERSE CHANNEL
GMSL Reverse Channel
Transmitter Rise/Fall t R, t F 20% to 80%, VO = 250mV, RL = 100Ω 2300 ps
Time


Total Serial Output p-p PRBS7, single-ended or differential
tTSOJ 0.15 UI
Jitter output
Deterministic Serial PRBS7, single-ended or differential
tDSOJ 0.1 UI
Output p-p Jitter output
Delay-Compensated Mode (Figure 8) 15
GPI-GPO Delay
tGPDR Non-Delay-Compensated Mode (Figure μs
Reverse Path 6
8)
GPI-GPO Skew
tSKEW Delay-compensated Mode (Figure 8) 7 ns
Reverse Path
AC ELECTRICAL CHARACTERISTICS / GMSL1
Lock Time tLOCK1 (Figure 9) 4 ms
Power-up Time tPU (Figure 10) 8.5 ms
1 video
Time from the first pixel in a video line at
line +
Video Latency tVL SIO_ to the first pixel in the CSI-2 output s
(128 x
packet. (Figure 11)
tPCLK)
The minimum duration PWDNB must be
PWDNB Hold Time tHOLD_PWDNB 1 μs
held LOW to reset the device
Reverse Control-
No forward channel data transmission
Channel Output Rise tR 100 400 ns
(Figure 4) (Note 2)
Time
Reverse Control-
No forward channel data transmission
Channel Output Fall tF 100 400 ns
(Figure 4) (Note 2)
Time
Deserializer GPI to serializer GPO
GPI-to-GPO Delay tGPIO (cable delay not included) 350 μs
(Figure 12) (Note 2)
AC ELECTRICAL CHARACTERISTICS / C-PHY and D-PHY LP TRANSMITTER (Note 2)
15%-85% Rise Time
TRLP/TFLP (Note 4) 25 ns
and Fall Time
30%-85% Rise Time TREOT (Note 5) 35 ns
Load Capacitance CLOAD (Note 4) 0 70 pF
AC ELECTRICAL CHARACTERISTICS / D-PHY HS TRANSMITTER (Note 2)
Common-Level
∆VCMTX(HF) > 450MHz 15 mVRMS
Variations, HF
Common-Level
∆VCMTX(LF) 50 to 450MHz 25 mVPEAK
Variations, LF
20%-80% Rise Time 0.4 UI
tR and tF
and Fall Time 50 ps
Differential-Mode fhMAX = 1.25GHz -4.5
Reflection Coefficient SddTX dB
(Note 6) fMAX = 1.875GHz -2.5


Common-Mode
Reflection Coefficient SccTX fMAX = 1.875GHz -2.5 dB
(Note 6)
Data Lane Bit Rate DLBR 80 2500 Mbps
Clock Lane Frequency CLFREQ 40 1250 MHz
CSI-2 Output Inter- 300ns +
tSPACE ns
packet Spacing 370UI
AC ELECTRICAL CHARACTERISTICS / D-PHY DATA-CLOCK TIMING (Note 2)
UI Instantaneous UIINST 0.4 12.5 ns
UI ≥ 1ns within a single burst -10% 10%
UI Variation ∆UI UI
0.667ns ≤ UI ≤ 1ns within a single burst -5% 5%
0.08 to 1.0Gbps -0.15 0.15
Data to Clock Skew TSKEW UIINST
> 1.0 to 1.5Gbps -0.2 0.2
Static Data to Clock
TSKEW Static > 1.5Gbps -0.2 0.2 UIINST
Skew
Dynamic Data to Clock TSKEW
> 1.5Gbps -0.15 0.15 UIINST
Skew Dynamic
AC ELECTRICAL CHARACTERISTICS / D-PHY GLOBAL OPERATION TIMING (Note 2)
Transition from LP to HS
TCLK-PRE 8 UI
Mode
State Before the HS-0
TCLK-
Line State Starting the 38 95 ns
HS Transmission PREPARE
TCLK-PREPARE + Time TCLK-

Prior to Starting the PREPARE + 300 ns
Clock TCLK-ZERO
THS-TRAIL or TCLK- 105 +
TEOT ns
TRAIL, to LP-11 12xUI
LP-11 Following a HS
THS-EXIT 100 ns
Burst
Data Lane LP-00 Before 40 + 85 +
THS-PREPARE ns
HS-0 4xUI 6xUI
THS-PREPARE + HS-0 THS-PREPARE 145 +
ns
State Prior to Sync + THS-ZERO 10xUI
State After Last HS 60 +
THS-TRAIL ns
Burst 4xUI
Initialization Time TINIT 100 μs
Length of any LP Period TLPX 50 ns
Skew-Calibration Sync TSKEWCAL_
16 UI
Pattern, 0xFFFF SYNC
Skew-Calibration Initial 100 μs
TSKEWCAL
Time 215 UI


Skew-Calibration 10 μs
TSKEWCAL
Periodic Time 210 UI
AC ELECTRICAL CHARACTERISTICS / C-PHY HS TRANSMITTER (Note 2)
Common-Level ΔVCPTX(HF) > 450MHz 15 mVRMS
Variations ΔVCPTX(LF) 50 to 450MHz 25 mVPEAK
Strong 0 to weak 1 transition, -58mV to
Rise Time tR 0.285 UI
+58mV, ZID = 100Ω
Strong 1 to weak 0 transition, +58mV to
Fall Time tF 0.285 UI
-58mV, ZID = 100Ω
tRISE-FALL-
Rise Time and Fall Time -58mV to +58mV, ZID = 100Ω. (Note 8) 360 ps
MAX
Differential-Mode fhMAX = 1.25GHz -5
Reflection Coefficient SddTX dB
(Note 7) fMAX = 1.875GHz -3
Common-Mode
Reflection Coefficient SccTX fMAX = 1.875GHz -3 dB
(Note 7)
C-PHY Lane Bit Rate CBR 182 5700 Mbps
CSI-2 Output Inter- 300ns +
tSPACE ns
packet Spacing 370UI
UI Instantaneous UIINST 0.4 12.5 ns
AC ELECTRICAL CHARACTERISTICS / C-PHY GLOBAL OPERATION TIMING (Note 2)
Time that the
Transmitter Drives the
3-Wire LP-000 Line
State Immediately t3-PREPARE 38 95 ns
Before the HS_+x Line
State Starting the HS
Transmission
Time that the
Transmitter Drives
t3-HS-EXIT 100 ns
LP-111 Following a HS
Burst
Transmitted Length of
any Low-Power State tLPX 50 ns
Period
Initialization Time tINIT 100 μs
AC ELECTRICAL CHARACTERISTICS / I2C TIMING
20 x
70% to 30%, CL = 20pF to 100pF, 1kΩ
Output Fall Time tF VDDIO/5. 150 ns
pullup to VDDIO (Note 2)
5V
From power-up or rising edge of PWDNB
to local register access. For remote
I2C Wake Time tWAKEUP 2.25 ms
register access, I2C Wake Time is the
same as Lock Time (tLOCK1, tLOCK2).


AC ELECTRICAL CHARACTERISTICS / I2C TIMING
Low fSCL range: (I2C_MST_BT = 010,
9.6 100
I2C_SLV_SH = 10)
Mid fSCL range: (I2C_MST_BT = 101,
SCL Clock Frequency fSCL 100 400 kHz
I2C_SLV_SH = 01)
High fSCL range: (I2C_MST_BT = 111,
400 1000
I2C_SLV_SH = 00)
fSCL range, low 4
Start Condition Hold
tHD:STA fSCL range, mid 0.6 µs
Time
fSCL range, high 0.26
fSCL range, low 4.7
Low Period of SCL
tLOW fSCL range, mid 1.3 µs
Clock
fSCL range, low 4
High Period of SCL
tHIGH fSCL range, mid 0.6 µs
Clock
fSCL range, low 4.7
Repeated Start
tSU:STA fSCL range, mid 0.6 µs
Condition Setup Time
fSCL range, low 0
Data Hold Time tHD:DAT fSCL range, mid 0 ns
fSCL range, high 0
fSCL range, low 250
Data Setup Time tSU:DAT fSCL range, mid 100 ns
fSCL range, high 50
fSCL range, low 4
Setup Time for Stop
tSU:STO fSCL range, mid 0.6 μs
Condition
fSCL range, low 4.7
Bus Free Time tBUF fSCL range, mid 1.3 μs
fSCL range, low 3.45
Data Valid Time tVD:DAT fSCL range, mid 0.9 μs
fSCL range, low 3.45
Data Valid Acknowledge
tVD:ACK fSCL range, mid 0.9 μs
Time


fSCL range, low 50
Pulse Width of Spikes
tSP fSCL range, mid 50 ns
Suppressed
fSCL range, high 50
Capacitive Load On
CB (Note 2) 100 pF
Each Bus Line
AC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK REQUIREMENTS (CRYSTAL) (X1/OSC, X2) (Note 2)
Frequency fXTAL 25 MHz
Frequency Stability +
fTN ±200 ppm
Frequency Tolerance
AC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK REQUIREMENTS (EXTERNAL INPUT ON X1/OSC, X2
UNCONNECTED) (Note 2)
Frequency FREF 25 MHz
Frequency Stability +
fTN -200 +200 ppm
Frequency Tolerance
Duty Cycle DC 40 50 60 %
Input Jitter tJIN Sinusoidal jitter < 1MHz (rising edge) 150 ps (p-p)
Input Rise Time tR 10% to 90% 5 ns
Input Fall Time tF 90% to 10% 5 ns
Note 1: Limits are 100% tested at TA = +105°C unless otherwise noted. Limits within the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization.
Note 2: Not production tested. Guaranteed by design and characterization.
Note 3: MFP pin speed programmed to fastest setting (TTS = 00). See Multifunction Pin Configuration for details regarding MFP speed
programming.
Note 4: CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to
always be < 10pF. The distributed line capacitance can be up to 50pF for a transmission line with 2ns delay.
Note 5: Additional capacitance up to 60pF (D-PHY) or 90pF (C-PHY) at RX termination center tap.
Note 6: Differential-mode and common-mode reflection coefficient are compliant with MIPI D-PHY V1.2 requirements over all specified
operating frequencies.
Note 7: Differential-mode and common-mode reflection coefficient are compliant with MIPI C-PHY V1.0 requirements over all specified
operating frequencies.
Note 8: For rates ≤ 1.5Gbps, tR and tF shall be ≤ min (0.4UI, tRISE-FALL-MAX).
Note 9: From power-up, release of RESET_LINK, or rising edge of the PWDNB pin, to rising edge of the LOCK pin. tRD must be
<90ms if serializer powers up or is released from link reset before deserializer. For more information, see the GMSL2 Link
Lock section.
Note 10: Production tested using ECS ECS-250-18-33Q-DS crystal.

Pin Configurations
TOP VIEW TOP VIEW
VTERM
VTERM
CKCN
CKAN
CKCP
CKCN
CKAP
CKAN
CKCP
DA3N
DA2N
DA1N
DA0N
CKAP
DA3P
DA2P
DA1P
DA0P
DA3N
DA2N
DA1N
DA0N
DA3P
DA2P
DA1P
DA0P
SCL
SCL
42 41 40 39 38 37 36 35 34 33 32 31 30 29 42 41 40 39 38 37 36 35 34 33 32 31 30 29
DB0P 43 28 SDA N.C. 43 28 SDA
DB0N 44 27 SCL1/MFP8 N.C. 44 27 SCL1/MFP8
CKBP 45 26 SDA1/MFP7 N.C. 45 26 SDA1/MFP7
CKBN 46 25 CFG1/MFP6 N.C. 46 25 CFG1/MFP6
N.C.
DB1P 47 24 VDDIO 47 24 VDDIO
N.C.
DB1N 48 23 SIOAP 48 23 SIOAP
N.C.
DB2P 49 MAX96724/F 22 SIOAN 49 MAX96724R 22 SIOAN
N.C.
DB2N 50 21 VDD18 50 21 VDD18
N.C.
CKFP 51 20 CAP_VDD N.C. 51 20 CAP_VDD
CKFN 52 19 SIOBN N.C. 52 19 SIOBN
DB3P 53 18 SIOBP N.C. 53 18 SIOBP
DB3N 54 17 XRES N.C. 54 17 XRES
VDD 55 EP 16 X2 VDD 55 EP 16 X2
+ +
VDD 56 15 X1/OSC VDD 56 15 X1/OSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1
MFP0 2 3 4 5 6 7 8 9 10 11 12 13 14
MFP1
MFP2
CFG0
SIODP
SIODN
VDD18
SIOCN
SIOCP
MFP3
MFP4
MFP5
CAP_VDD
PWDNB
MFP0
MFP1
MFP2
CFG0
SIODP
SIODN
VDD18
SIOCN
SIOCP
MFP3
MFP4
MFP5
CAP_VDD
PWDNB
Pin Description
FUNCTION MODE
PIN NAME FUNCTION
GMSL2 GMSL1 MAX96724R
GMSL2/GMSL1 SERIAL LINK
5 SIODP SIODP SIODP SIODP Noninverted Serial-Data I/O D.
6 SIODN SIODN SIODN SIODN Inverted Serial-Data I/O D.
10 SIOCP SIOCP SIOCP SIOCP Noninverted Serial-Data I/O C.
9 SIOCN SIOCN SIOCN SIOCN Inverted Serial-Data I/O C.
18 SIOBP SIOBP SIOBP SIOBP Noninverted Serial-Data I/O B.
19 SIOBN SIOBN SIOBN SIOBN Inverted Serial-Data I/O B.
23 SIOAP SIOAP SIOAP SIOAP Noninverted Serial-Data I/O A.
22 SIOAN SIOAN SIOAN SIOAN Inverted Serial-Data I/O A.
CSI-2 INTERFACE — PORT A/C/D (* denotes default state after power-up)
DA0P* DA0P* DA0P* DA0P: D-PHY Port A Data Lane 0 (4-lane)
DC0P DC0P DC0P DC0P: D-PHY Port C Data Lane 0 (2-lane)
31 DA0P
A0A A0A A0A A0A: C-PHY Port A Lane 0 Output A (4-lane)
C0A C0A C0A C0A: C-PHY Port C Lane 0 Output A (2-lane)
DA0N* DA0N* DA0N* DA0N: D-PHY Port A Data Lane 0 (4-lane)
DC0N DC0N DC0N DC0N: D-PHY Port C Data Lane 0 (2-lane)
32 DA0N
A0B A0B A0B A0B: C-PHY Port A Lane 0 Output B (4-lane)
C0B C0B C0B C0B: C-PHY Port C Lane 0 Output B (2-lane)

FUNCTION MODE
PIN NAME FUNCTION
DISABLED* DISABLED* DISABLED* DISABLED: CKCP is Disabled in 4-Lane Mode
CKCP CKCP CKCP CKCP: D-PHY Port C Clock Lane (2-lane)
33 CKCP CKAP(alt) CKAP(alt) CKAP(alt) CKAP(alt): D-PHY Port A CLK ALT (4-lane)
A0C A0C A0C A0C: C-PHY Port A Lane 0 Output C (4-lane)
C0C C0C C0C C0C: C-PHY Port C Lane 0 Output C (2-lane)
DISABLED* DISABLED* DISABLED* DISABLED: CKCN is Disabled in 4-Lane Mode
CKCN CKCN CKCN CKCN: D-PHY Port C Clock Lane (2-lane)
34 CKCN CKAN(alt) CKAN(alt) CKAN(alt) CKAN(alt): D-PHY Port A CLK ALT (4-lane)
C1A C1A C1A C1A: C-PHY Port C Lane 1 Output A (2-lane)
DC1P DC1P DC1P DC1P: D-PHY Port C Data Lane 1 (2-lane)
35 DA1P
C1B C1B C1B C1B: C-PHY Port C Lane 1 Output B (2-lane)
DC1N DC1N DC1N DC1N: D-PHY Port C Data Lane 1 (2-lane)
36 DA1N
C1C C1C C1C C1C: C-PHY Port C Lane 1 Output C (2-lane)
DD0P DD0P DD0P DD0P: D-PHY Port D Data Lane 0 (2-lane)
37 DA2P
D0A D0A D0A D0A: C-PHY Port D Lane 0 Output A (2-lane)
DD0N DD0N DD0N DD0N: D-PHY Port D Data Lane 0 (2-lane)
38 DA2N
D0B D0B D0B D0B: C-PHY Port D Lane 0 Output B (2-lane)
CKAP* CKAP* CKAP* CKAP: D-PHY Port A Clock Lane (4-lane)
CKDP CKDP CKDP CKDP: D-PHY Port D Clock Lane (2-lane)
39 CKAP DISABLED DISABLED DISABLED DISABLED: When CKAP/N(alt) is Enabled
D0C D0C D0C D0C: C-PHY Port D Lane 0 Output C (2-lane)
CKAN* CKAN* CKAN* CKAN: D-PHY Port A Clock Lane (4-lane)
CKDN CKDN CKDN CKDN: D-PHY Port D Clock Lane (2-lane)
40 CKAN DISABLED DISABLED DISABLED DISABLED: When CKAP/N(alt) is Enabled
D1A D1A D1A D1A: C-PHY Port D Lane 1 Output A (2-lane)
DD1P DD1P DD1P DD1P: D-PHY Port D Data Lane 1 (2-lane)
41 DA3P
D1B D1B D1B D1B: C-PHY Port D Lane 1 Output B (2-lane)
DD1N DD1N DD1N DD1N: D-PHY Port D Data Lane 1 (2-lane)
42 DA3N
D1C D1C D1C D1C: C-PHY Port D Lane 1 Output C (2-lane)
CSI-2 INTERFACE — PORT B/E/F (* denotes default state after power-up)
DB0P: D-PHY Port B Data Lane 0 (4-lane)
DB0P* DB0P*
DE0P: D-PHY Port E Data Lane 0 (2-lane)
DE0P DE0P
43 DB0P N.C. B0A: C-PHY Port B Lane 0 Output A (4-lane)
B0A B0A
E0A: C-PHY Port E Lane 0 Output A (2-lane)
E0A E0A
N.C.: No Connect

FUNCTION MODE
PIN NAME FUNCTION
DB0N: D-PHY Port B Data Lane 0 (4-lane)
DB0N* DB0N*
DE0N: D-PHY Port E Data Lane 0 (2-lane)
DE0N DE0N
44 DB0N N.C. B0B: C-PHY Port B Lane 0 Output B (4-lane)
B0B B0B
E0B: C-PHY Port E Lane 0 Output B (2-lane)
E0B E0B
N.C.: No Connect
CKBP: D-PHY Port B Clock Lane (4-lane)
CKBP* CKBP*
CKEP: D-PHY Port E Clock Lane (2-lane)
CKEP CKEP
DISABLED: When CKBP/N(alt) is Enabled
45 CKBP DISABLED DISABLED N.C.
B0C: C-PHY Port B Lane 0 Output C (4-lane)
B0C B0C
E0C: C-PHY Port E Lane 0 Output C (2-lane)
E0C E0C
N.C.: No Connect
CKBN: D-PHY Port B Clock Lane (4-lane)
CKBN* CKBN*
CKEN: D-PHY Port E Clock Lane (2-lane)
CKEN CKEN
DISABLED: When CKBP/N(alt) is Enabled
46 CKBN DISABLED DISABLED N.C.
B1A: C-PHY Port B Lane 1 Output A (4-lane)
B1A B1A
E1A: C-PHY Port E Lane 1 Output A (2-lane)
E1A E1A
N.C.: No Connect
DB1P* DB1P*
DE1P: D-PHY Port E Data Lane 1 (2-lane)
DE1P DE1P
47 DB1P N.C. B1B: C-PHY Port B Lane 1 Output B (4-lane)
B1B B1B
E1B: C-PHY Port E Lane 1 Output B (2-lane)
E1B E1B
N.C.: No Connect
DB1N* DB1N*
DE1N: D-PHY Port E Data Lane 1 (2-lane)
DE1N DE1N
48 DB1N N.C. B1C: C-PHY Port B Lane 1 Output C (4-lane)
B1C B1C
E1C: C-PHY Port E Lane 1 Output C (2-lane)
E1C E1C
N.C.: No Connect
DB2P* DB2P*
DF0P: D-PHY Port F Data Lane 0 (2-lane)
DF0P DF0P
49 DB2P N.C. B2A: C-PHY Port B Lane 2 Output A (4-lane)
B2A B2A
F0A: C-PHY Port F Lane 0 Output A (2-lane)
F0A F0A
N.C.: No Connect
DB2N* DB2N*
DF0N: D-PHY Port F Data Lane 0 (2-lane)
DF0N DF0N
50 DB2N N.C. B2B: C-PHY Port B Lane 2 Output B (4-lane)
B2B B2B
F0B: C-PHY Port F Lane 0 Output B (2-lane)
F0B F0B
N.C.: No Connect
DISABLED: CKFP Output is Disabled in 4-Lane
DISABLED* DISABLED*
CKFP: D-PHY Port F Clock Lane (2-lane)
CKFP CKFP
CKBP(alt): D-PHY Port B Clock Lane (4-lane)
51 CKFP CKBP(alt) CKBP(alt) N.C.
B2C: C-PHY Port B Lane 2 Output C (4-lane)
B2C B2C
F0C: C-PHY Port F Lane 0 Output C (2-lane)
F0C F0C
N.C.: No Connect
DISABLED: CKFN is Disabled in 4-Lane
DISABLED* DISABLED*
CKFN: D-PHY Port F Clock Lane (2-lane)
CKFN CKFN
CKBN(alt): D-PHY Port B CLK ALT (4-lane)
52 CKFN CKBN(alt) CKBN(alt) N.C.
B3A: C-PHY Port B Lane 3 Output A (4-lane)
B3A B3A
F1A: C-PHY Port F Lane 1 Output A (2-lane)
F1A F1A
N.C.: No Connect

FUNCTION MODE
PIN NAME FUNCTION
DB3P* DB3P*
DF1P: D-PHY Port F Data Lane 1 (2-lane)
DF1P DF1P
53 DB3P N.C. B3B: C-PHY Port B Lane 3 Output B (4-lane)
B3B B3B
F1B: C-PHY Port F Lane 1 Output B (2-lane)
F1B F1B
N.C.: No Connect
DB3N* DB3N*
DF1N: D-PHY Port F Data Lane 1 (2-lane)
DF1N DF1N
54 DB3N N.C. B3C: C-PHY Port B Lane 3 Output C (4-lane)
B3C B3C
F1C: C-PHY Port F Lane 1 Output C (2-lane)
F1C F1C
N.C.: No Connect
MULTIFUNCTION PINS — (* denotes default state after power-up) (** GMSL1 has limited GPIO tunneling capability)
FSYNC: FSync Output (Master) or Input (Slave)
FSYNC
FSYNC FSYNC LMN0: Line Fault Monitor Input
LMN0
LMN0 LMN0 GPI0: GPI-GPO Sync Signal
1 MFP0 GPI0
GPIO0 GPIO0 GPIO0: General Purpose I/O. Disabled with
GPIO0**
DISABLED* DISABLED* 1MΩ pulldown.
DISABLED*
DISABLED: Disabled at Power-Up and is Hi-Z
VSYNC0 VSYNC0: Vertical Sync Push-Pull Output
DE0 DE0: Data Enable Push-Pull Output
VSYNC0 VSYNC0
HSYNC0 HSYNC0: Horizontal Sync Push-Pull Output
DE0 DE0
CNTL0 CNTL0: Control 0 with Push-Pull Driver
HSYNC0 HSYNC0
2 MFP1 CNTL1 CNTL2: Control 2 with Push-Pull Driver
LMN1 LMN1
LMN1 LMN1: Line Fault Monitor Input
GPIO1 GPIO1
GPI1 GPI1: Input GPI-GPO Sync
DISABLED* DISABLED*
GPIO1** GPIO1: 1MΩ pulldown
DISABLED* DISABLED: Pin is Disabled and is Hi-Z
LMN2 LMN2
LMN2 LMN2: Line Fault Monitor Input
3 MFP2 GPIO2 GPIO2
GPI2 GPI2: Input GPI-GPO Sync
DISABLED* DSIABLED*
GPIO2** GPIO2: 1MΩ pulldown
VSYNC1 VSYNC1: Vertical Sync Push-Pull Output
VSYNC1 DE1 VSYNC1 DE1: Data Enable Push-Pull Output
DE1 HSYNC1 DE1 HSYNC1: Horizontal Sync Push-Pull Output
HSYNC1 CNTL4 HSYNC1 CNTL4: Control Output 4 with Push-Pull Driver
12 MFP3
LMN3 LMN3 LMN3 LMN3: Line Fault Monitor Input
GPIO3 GPI3 GPIO3 GPI3: Input for GPI-GPO Sync
DISABLED* GPIO3** DISABLED* GPIO3: 1MΩ pulldown
LOCK* LOCK* LOCK* LOCK: Open-Drain with 40kΩ Pullup to VDDIO
13 MFP4
GPIO4 GPIO4** GPIO4 GPIO4: General Purpose I/O
ERRB: Open-Drain with 40kΩ Pullup to VDDIO
ERRB* ERRB* ERRB*
ERRB/LOCK: Open-Drain with 40kΩ Pullup to
14 MFP5 ERRB/LOCK ERRB/LOCK ERRB/LOCK
VDDIO
GPIO5 GPIO5** GPIO5
GPIO5: General Purpose I/O
CFG1 CFG1 CFG1 CFG1: Latched at Power-Up. See Table 8.
GPIO_Aggregat GPIO_Aggregat GPIO_Aggregat GPIO_Aggregation: See User Guide.
25 CFG1/MFP6 ion ion ion GPO6: General-Purpose Output.
GPO6 GPO6** GPO6 DISABLED: After Latching CFG1 at Power-Up,
DISABLED* DISABLED* DISABLED* Pin is disabled and goes to Hi-Z.

FUNCTION MODE
PIN NAME FUNCTION
SDA1: Open-Drain with 40kΩ Pullup to VDDIO
SDA1* SDA1*
FSYNC(ALT) FSYNC (ALT): ALT. Output (Master) or Input
FSYNC(ALT) FSYNC(ALT)
VSYNC2 (Slave)
VSYNC2 VSYNC2
26 SDA1/MFP7 DE2 VSYNC2: Vertical Sync Push-Pull Output
DE2 DE2
HSYNC2 DE2: Data Enable Push-Pull Output
HSYNC2 HSYNC2
GPIO7** HSYNC2: Horizontal Sync Push-Pull Output
GPIO7 GPIO7
SCL1: Open-Drain Output with 40kΩ Pullup to
SCL1* SCL1*
VSYNC3 VDDIO
VSYNC3 VSYNC3
DE3 VSYNC3: Vertical Sync Push-Pull Output
27 SCL1/MFP8 DE3 DE3
HSYNC3 DE3: Data Enable Push-Pull Output
HSYNC3 HSYNC3
GPIO8** HSYNC3: Horizontal Sync Push-Pull Output
GPIO8 GPIO8
MISCELLANEOUS — (Table 3)
4 CFG0 CFG0 CFG0 CFG0 Latched at Power-Up (Table 7)
8, 20 CAP_VDD CAP_VDD CAP_VDD CAP_VDD Decoupling for VDD Core Supply.
PWDNB: Active-low, Input with a 1MΩ
Pulldown to Ground. Set low to enter Power-
11 PWDNB PWDNB PWDNB PWDNB Down mode.
Attach pullup resistor to VDDIO for normal
operation.
28 SDA SDA SDA SDA Open-Drain with 40kΩ Pullup to VDDIO.
29 SCL SCL SCL SCL Open-Drain with 40kΩ Pullup to VDDIO.
15 X1/OSC X1/OSC X1/OSC X1/OSC 25MHz Crystal/Clock Source.
Connect to 25MHz. OSC requires X2 to be
16 X2 X2 X2 X2
floating.
17 XRES XRES XRES XRES Connect 402Ω 1% resistor to ground.
POWER SUPPLIES — (Table 3)
7, 21 VDD18 VDD18 VDD18 VDD18 1.8V Analog Supply.
24 VDDIO VDDIO VDDIO VDDIO 3.3V or 1.8V I/O Power Supply.
30 VTERM VTERM VTERM VTERM 1.2V CSI C/D-PHY Supply.
1.2/1.0V core supply. 1.2V uses an internal
55, 56 VDD VDD VDD VDD
regulator. 1.0V will bypass the regulator.
EP EP EP EP EP Exposed Pad connect to ground.

Functional Diagrams
MAX96724
PORT A
SERIAL TO DECODE & C-PHY C-PHY
SIOA AEQ LINE TUNNEL & PORT A D-PHY D-PHY 4-LANE 2-LANE
PARALLEL DESCRAMBLE
BUFFER PIXEL 4-LANE 2-LANE TRIO TRIO
ENCODING & CONTROLLER 31/32 DA0P/N DC0P/N A0A/B C0A/B
REV CTRL A
SCRAMBLE MIPI 33/34 CKA ALT CKCP/N A0C/A1A C0B/C1A
CONTROLLER 1&2 35/36 DA1P/N DC1P/N A1B/C C1B/C
SIOB SERIAL TO DECODE &
AEQ TUNNEL & 37/38 DA2P/N DD0P/N A2A/B D0A/B
PARALLEL DESCRAMBLE LINE
PIXEL 39/40 CKAP/N CKDP/N A2C/A3A D0C/D1A
SPLIT BUFFER
ENCODING & CONTROLLER 41/42 DA3P/N DD1P/N A3B/C D1B/C
REV CTRL B VIDEO
SCRAMBLE AND VIDEO
FORWARD AGGREGATOR TUNNEL & PORT B
PIXEL PORT B C-PHY C-PHY
SERIAL TO DECODE & CONTROL D-PHY D-PHY
SIOC AEQ CONTROLLER 4-LANE 2-LANE
PARALLEL DESCRAMBLE DATA LINE 4-LANE 2-LANE
ONLY MIPI TRIO TRIO
BUFFER
43/44 DB0P/N DE0P/N B0A/B E0A/B
ENCODING & MAX96724/F CONTROLLER 3&4
REV CTRL C 45/46 CKBP/N CKEP/N B0C/B1A E0C/E1A
SCRAMBLE
TUNNEL & ONLY 47/48 DB1P/N DE1P/N B1B/B1C E1B/E1C
SERIAL TO DECODE & PIXEL MAX96724/F 49/50 DB2P/N DF0P/N B2B/B2C F0A/F0B
SIOD AEQ
PARALLEL DESCRAMBLE LINE CONTROLLER 51/52 CKB ALT CKFP/N B2C/B3A F0C/F1A
BUFFER ONLY 53/54 DB3P/N DF1P/N B3B/C F1B/C
ENCODING & MAX96724/F
REV CTRL D
SCRAMBLE
REV CTRL A
CONTROL
REV CTRL B
CHANNEL
REV CTRL C
ROUTER
REV CTRL D
ERRB/
2 X I 2C 9 X GPIO
LINE-FAULT LOCK
DETECTORS
DEVICE CONFIG
PLL MAP TO MULTIFUNCTION PINS
AND CONTROL
X1/OSC X2 XRES PWDNB CFG[0:1] MFP[0:8]

Detailed Description
Descriptions
Thermal Management
Power consumption of the MAX96724/F/R varies based on the use case. Care must be taken by the user to provide
sufficient heat dissipation with proper board design and cooling techniques. The package's exposed pad must be
connected to the PCB ground plane by an array of vias. This approach simultaneously provides the lowest electrical and
thermal impedances.
System thermal management must keep the operating junction temperature below +125°C to meet electrical
specifications and avoid impacting device reliability.
Refer to Tutorial 4083 (www.maximintegrated.com/thermal-tutorial) for further guidance.
Control Channel Programming

MAX96724/F/R internal registers can be accessed locally via any of the two available I2C ports. Lower indexed ports
have a higher priority in the case of simultaneous queries. By default, remote GMSL serializer register access is available
via I2C port 0 only. However, the internal I2C crossover enables any of the two ports to connect to the control channel,
which thereby provides access to remote serializer registers. Only one of the two ports can access the control channel
at a given time, and the other I2C port then functions essentially as remote pass-throughs from the perspective of
the serializer. See I2C for further details regarding the routing of I2C ports in the MAX96724/F/R. For multi-master
configurations with microcontrollers connected to both the serializer and deserializer, bus contention can be avoided by
using register settings to disable the remote control channel.
Host-to-Peripheral Main I2C and Pass-Through I2C Communication

When communicating between a host and peripheral, main and pass-through I2C operation is the same. An I2C tunnel
across the GMSL2 link connects the host’s I2C master to the remote I2C slave. This logically connects separated I2C
buses, enabling I2C transactions across the serial link to occur (with some delay) as if performed on the same physical
I2C bus. The GMSL2 serializer and deserializer are intermediary devices; the host I2C master connects to a GMSL2
device I2C slave, and the peripheral I2C slave connects to a GMSL2 device I2C master.
For example, when the host I2C master transacts on one side of the link (local-side), the I2C slave of the local-side
GMSL2 device forwards data to the other side (remote-side). Data is then received by the I2C master of the remote-side
GMSL2 device, which in turn generates the same I2C transaction with the peripheral slave I2C. The remote-side GMSL2
device sends back any I2C data expected by the local-side.
The I2C interface uses clock stretching (holding SCL low) to account for timing differences between master and slave
and to allow time for data to be forwarded and received across the serial link. The host I2C master and peripheral I2C
slave must support clock stretching by the GMSL2 device.
SDA and SCL lines operate as both an input and an open-drain output. External pullup resistors are required on SDA
and SCL.
Each transmission consists of a START condition sent by a master, followed by the device’s 7-bit slave address plus a
R/W bit, register address bytes, one or more data bytes, and finally a STOP condition.
Register addresses are 16-bits wide. Single or multiple data bytes can be written or read (by address autoincrements).

I2C Write Packet Format
1 7 1 1 8 1 8 1 8 1 8 1 8 1 1
S DEV ADDR W A REG ADDR (MSB) A REG ADDR (LSB) A DATA 0 A DATA 1 A DATA N NA P
Figure 1. I2C Write Packet Format
I2C Read Packet Format
1 7 1 1 8 1 8 1 1 7 1 1 8 1 8 1 8 1 1
S DEV ADDR W A REG ADDR (MSB) A REG ADDR (LSB) A S DEV ADDR R A DATA 0 A DATA 1 A DATA N NA P
Figure 2. I2C Read Packet Format
Device Address
Each device on the I2C control channel must have a unique address. This includes both peripherals and GMSL devices.
The GMSL2 device address is set to one of several 7-bit addresses according to the voltage level of the CFG0 pin at
power-up. See CFG Latch at Power-up Pins for further details. Note that the device address can be changed after power-
up by writing to the DEV_ADDR register.
Advanced GMSL User Documentation

This data sheet contains electrical specifications, pin and functional descriptions, feature overviews and register
definitions. Designers must also have the following information to correctly design using this device:
● The GMSL2 Channel Specification contains physical layer requirements for the PCB traces, cables and connectors
that constitute the GMSL2 link.
● The GMSL2 Hardware Design Guide contains recommendations for PCB design, applications circuits, selection of
external components and guidelines for use of GMSL2 signal integrity tools.
● The GMSL2 User Guide contains detailed programming guidelines for GMSL2 device features.
● Errata sheets contain deviations from published device specifications and are specific to part number and revision
ID.
Contact the factory for the above documents and for additional guidance on MAX96724/F/R features.
Recommended Operating Conditions

Table 2. Recommended Operating Conditions
PARAMETER PIN NOMINAL VOLTAGE MIN TYP MAX UNIT
VTERM 1.14 1.2 1.26
VDD18 1.7 1.8 1.9
Supply Range VDD 1.0V 0.95 1.0 1.05 V
1.2V 1.14 1.2 1.26
VDDIO 1.7 3.6
Operating Junction Temperature (TJ) -40 125 ºC
External Component Requirements

Critical components that must be connected to the specified pins for correct functionality.

Table 3. External Component Requirements

COMPONENT SYMBOL CONDITION VALUE UNIT
402
XRES RXRES Connect the resistor to XRES and ground. Ω
±1%
GMSL2, GMSL1 - HIM
0.1
Place in close proximity to the Enabled
Link Isolation Capacitors CLINK μF
SIO pins. GMSL2, GMSL1 - HIM
0.22
Enabled
49.9
Termination for Coax mode RTERM Place near associated SIO_N pin. Ω
±1%
25MHz
Crystal Place as close as possible to pins X1 and X2.
±200ppm
VDDIO Decoupling Capacitors* Place as close as possible to pin VDDIO. 0.01μF + 10μF
2 x 0.01μF +
VDD18 Decoupling Capacitors* Place as close as possible to each VDD18 pin.
10μF
2 x 0.1μF +
VDD Decoupling Capacitors* Place as possible to each VDD pin.
10μF
VTERM Decoupling Capacitors* Place as close as possible to pin VTERM. 0.01μF + 10μF
2 x 0.1μF +
CAP_VDD Decoupling Capacitors Place as close as possible to each CAP_VDD pin.
10μF
Configuration Pins (CFG0, CFG1/ R1, R2 See Table 7.
MFP6) R1, R2 See Table 8.
Power-over-Coax (PoC) Contact the factory, PoC cannot be used with line-fault.
User
Line Fault Refer to GMSL User Guide for proper line-fault setup.
Guide
* Power supply decoupling capacitor values are recommendations only. It is the responsibility of the board designer to
determine what decoupling is necessary for the specific application.
ESD Protection
Table 4. ESD Protection
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Human Body Model (HBM), RD = 1.5kΩ, CS = 100pF ±8
ISO10605, RD = 330Ω, CS = 150pF, Contact Discharge, Coax
±6
Configuration
VESD kV
SIO_ ISO10605, RD = 330Ω, CS = 150pF, Contact Discharge, STP
±4
Configuration
ISO10605, RD = 330Ω, CS = 150pF, Air Discharge ±8
AEC-Q100-011 Rev-C1, Charged Device Model (CDM) 750 V
Human Body Model (HBM), RD = 1.5kΩ, CS = 100pF ±3 kV
All Other Pins VESD
AEC-Q100-011 Rev-C1, Charged Device Model (CDM) 750 V
Figures

GMSL2 Reverse Channel Serial Outputs
RL/2
OUT+
VOD
OUT- VOS
RL/2
GND
((OUT+) + (OUT-))/2
OUT-
VOS(-) VOS(+) VOS(-)
OUT+
ΔVOS = |VOS(+) - VOS(-)|
VODT = VOD(+) + VOD(-) VOD(+)
VOD = 0V
VOD(-) ΔVOD = |VOD(+) + VOD(-)|
(OUT+) – (OUT-)
Figure 3. GMSL2 Serial Output Parameters

GMSL1 Serial Output Parameters
VROS
SIOP
RL/2
VROD
VOS
SION RL/2
VROS
GMSL1 REVERSE
CONTROL-CHANNEL
TRANSMITTER
SIOP SION
VROS
VOS VROD
SION SIOP
VRODH
0.9 x VRODH
0.1 x VRODH tF
SIOP – SION
(STP MODE) tR 0.1 x VRODL
0.9 x VRODL
VRODL
VROSH
0.9 x VROSH
0.1 x VROSH tF
SIOP/SION VOS
(COAX MODE) tR 0.1 x VROSL
0.9 x VROSL
VROSL
Figure 4. GMSL1 Serial Output Parameters

C-PHY Possible ∆VCPTX and ∆VOD Distortions of Single-Ended HS Signals
LARGE AMPLITUDE VA (SINGLE-ENDED HIGH-SPEED SIGNALS)

+X -Y -Z ΔVOD +Z +Y -X
VA
VOHHS
VC
VCPTX
VB
VOLHS
FIXED OFFSET VA (SINGLE-ENDED HIGH-SPEED SIGNALS)

VA
VOHHS
VC ΔVOD/2
VCPTX
VB
VOLHS
SLOW RISE/FALL TIME VA (SINGLE-ENDED HIGH-SPEED SIGNALS)

VA
VOHHS
VC
VCPTX
VB
VOLHS
Figure 5. C-PHY Possible ∆VCPTX and ∆VOD Distortions of Single-Ended HS Signals
Copyright © 2013-2014 MIPI Alliance, Inc. All rights reserved.
C-PHY Ideal Single-Ended and Resulting Differential High-Speed Signals
+X -Y -Z +Z +Y -X
VA
VOHHS
VC |VOD|weak
VCPTX |VOD|strong
VB
VOLHS
STRONG 1
VA - VB WEAK 1
VB - VC
VC - VA WEAK 0
STRONG 0
ZERO CROSSING
Figure 6. C-PHY Ideal Single-Ended and Resulting Differential High-Speed Signals
Copyright © 2013-2014 MIPI Alliance, Inc. All rights reserved.

GMSL2 Video Latency
GMSL2 VIDEO PACKET WITH 1ST PIXEL DATA
GMSL2 VIDEO PACKETS IN LINE N - 1 GMSL2 VIDEO PACKETS IN LINE N GMSL2 VIDEO PACKETS IN LINE N + 1
SERIAL INPUT
(SIO_)
LINE PIXEL DATA LINE PIXEL DATA LINE PIXEL DATA

BLANK BLANK BLANK
tVL 1ST PIXEL

CSI-2 PACKET N - 2 CSI-2 PACKET N - 1 CSI-2 PACKET N
CSI-2 OUTPUT PACKET PACKET PACKET PACKET

PIXEL DATA PIXEL DATA PIXEL DATA
FOOTER HEADER FOOTER HEADER
Figure 7. GMSL2 Video Latency
GMSL2 GPI-to-GPO Delay and Skew
DESERIALIZER VIH,MIN
GPI VIL,MAX
tGPDR
tGPDR
SERIALIZER VOH,MIN
GPO VOL,MAX
tSKEW tSKEW
INDICATES TYPICAL GPO

VARIATION WHEN MULTIPLE
SERIALIZERS ARE USED
Figure 8. GMSL2 GPI-to-GPO Delay and Skew
GMSL1 Lock Time
SIOP
SION
tLOCK1
VOH
LOCK
PWDNB MUST BE HIGH
Figure 9. GMSL1 Lock Time

GMSL1 Power-up Delay
SIOP
SION
VIH
PWDNB
tPU
VOH
LOCK
Figure 10. GMSL1 Power-up Delay
GMSL1 Video Latency
GMSL1 SERIAL WORD WITH 1ST PIXEL DATA
GMSL1 SERIAL WORDS IN GMSL1 SERIAL WORDS IN

VIDEO LINE N - 1 GMSL1 SERIAL WORD IN VIDEO LINE N VIDEO LINE N + 1
SERIAL INPUT
(SIO_)
LINE PIXEL DATA LINE PIXEL DATA LINE PIXEL DATA

BLANK BLANK BLANK
tVL 1ST PIXEL

CSI-2 PACKET N - 2 CSI-2 PACKET N - 1 CSI-2 PACKET N
CSI-2 OUTPUT PACKET PACKET PACKET PACKET

PIXEL DATA PIXEL DATA PIXEL DATA
FOOTER HEADER FOOTER HEADER
Figure 11. GMSL1 Video Latency
GMSL1 GPI-to-GPO Delay
DESERIALIZER VIH(MIN)
VIL(MAX)
GPI
tGPIO
tGPIO
SERIALIZER VOH(MIN)
GPO VOL(MAX)
Figure 12. GMSL1 GPI-to-GPO Delay
Product Overview
The MAX96724/F/R deserializer converts four GMSL2 or GMSL1 inputs to up to four independent MIPI CSI-2 C/D-PHY
outputs containing a combined total of up to four lanes. It also sends and receives control channel data, enabling full-
duplex transmission of forwarding path video and bidirectional control data over low-cost 50Ω coax or 100Ω STP cables

that meet the GMSL2 channel specification. In GMSL1 mode, the MAX96724/F/R can be paired with first-generation
GMSL1 serializers or GMSL2 serializers in GMSL1 mode, operating up to 3.12Gbps.
The MAX96724/F/R has 4-lane or dual 2-lane CSI-2 v1.3 output ports that support data rates of 80Mbps to 2.5Gbps per
lane in D-PHY mode or 182Mbps to 5.7Gbps per lane in C-PHY mode. The number of active data lanes in each CSI-2
port is programmable with 4-lane ports providing one, two, three, or four lanes and 2-lane ports providing one or two
lanes.
The MAX96724/F/R is intended to be paired with GMSL2 serializers or previous generation GMSL1 serializers. Several
common multi-sensor use cases are supported with the MAX96724/F/R being particularly well suited to surround-view
sensor systems that include four physically separate cameras or other sensors. The simplest conceptual system following
this topology includes four independent sensors, each with a serializer routed to the MAX96724/F/R's four GMSL inputs.
The resulting CSI-2 streams from each sensor are then routed to two independent CSI-2 C/D-PHY outputs in 2x2-lane
mode, providing a system with four independent inputs and two outputs where data from two sensors are aggregated
and routed to a dedicated output.
MAX96724/F/R has built-in ease of use functionality:
● Use Case Profiles
● MIPI Controller Mapping
● D-PHY to C-PHY conversion
● Automatic Detection of Pixel or Tunnel Mode per Input
Cabling Options
GMSL1/2 supports operation with either 50Ω coaxial or 100Ω shielded twisted pair (STP) cabling. Contact the factory for
GMSL Channel Specifications. Coax or STP operation is determined by the level of CFG pins at power-up as detailed in
the CFG Latch at Power-up Pins section. In coax mode, use only the noninverted SIO pin. In STP configurations, both
the noninverted and inverted SIO pins are enabled by default. Any unused SIO pins should be AC terminated with 50Ω
to ground.
GMSL2 Bandwidth Information and Calculation

Forward links have a fixed link rate of 3Gbps or 6Gbps for the MAX96724/F/R. The reverse-link rate is fixed at
187.5Mbps. The GMSL2 protocol and channel coding overhead is roughly 14%. This leaves approximately 2.6Gbps or
5.2Gbps of data throughput in the forward direction and 162Mbps in the reverse direction. Ensure that the worst-case
use cases do not exceed the available throughput of the forward and reverse links. The GMSL SerDes GUI includes a
bandwidth (BW) calculator that can be used for initial bandwidth requirements estimates. It is recommended to consult
the factory for high-bandwidth use cases to ensure error-free performance.
Table 5 provides rough estimates of the bandwidth utilization for each communication channel.
Table 5. Forward- and Reverse-Link Bandwidth Utilization
DATA APPROXIMATE BANDWIDTH UTILIZATION
H x V x fps x bpp x (1+ (% horizontal blanking)/100 + (% vertical blanking)/100) x 1.14
Maximum bandwidth is limited by pixel clock rate PCLK.
Pixel mode: GMSL PCLK = Received MIPI data rate/bpp
Video (Forward Path Only) Pixel mode (double pixel mode): PCLK = MIPI data rate/(2*bpp)
Tunneling mode: GMSL PCLK = Received MIPI data rate/24
Maximum GMSL PCLK: 300MHz for 3Gbps link rate
Maximum GMSL PCLK = 600MHz for 6Gbps link rate
I 2C 18 to 60 x I2C clock rate, depending on available link bandwidth
60 x GPIO transition rate without delay compensation
GPIO
80 x GPIO transition rate with delay compensation enabled
Definitions:
H = Horizontal resolution (active pixels)
V = Vertical resolution (active video lines)
fps = Frames per second

bpp = Bits per pixel

MIPI data rate = Aggregate data rate of all lanes in the MIPI interface
HB1 HORIZONTAL BLANKING = HB1+HB2 HB2

(% OF H)
VB1
VERTICAL
V LINES BLANKING
PIXEL AREA
= VB1+VB2
(% OF V)
VB2
H PIXELS
Figure 13. Video Frame Format for Bandwidth Calculation
GMSL2 Minimum Blanking

The minimum horizontal blanking period needed by the CSI-2 serializers and deserializers is the maximum of either 40
pixels or 300ns + 370UI (where UI is defined as the period of CSI-2 lane rate). For most cases, 40 pixels is the larger
number. The minimum vertical blanking period is one video line. The minimum vertical front porch is one video line.
Recommended vertical back porch is one video line.
Minimum vertical back porch in pixel mode is the maximum of:
● 40 pixels
● 300ns + 370UI
Minimum vertical back porch in tunneling mode is the maximum of:
● 40 pixels
● 200 PCLK periods + 233ns, where PCLK = total MIPI data rate/24
● 300ns + 370UI
TOTAL FRAME WIDTH
VERTICAL BACK PORCH

HORIZONTAL FRONT PORCH
HORIZONTAL BACK PORCH
TOTAL FRAME HEIGHT
H PIXELS
HORIZONTAL SYNC
PIXEL AREA
V
LINES
VERTICAL FRONT PORCH
VERTICAL SYNC
Figure 14. Video Timing
AEQ (Automatic Adaptive Equalization)

The GMSL2 devices automatically adapt the forward path receiver characteristics to compensate for insertion loss and

return loss characteristics of the channel, which consist of the cables, connectors, temperature, and PCBs. This approach
optimizes performance on any channel that meets the GMSL2 channel specifications. Initial adaptation is performed
during link lock and then is invoked at every second to track temperature and voltage variations. This is critical for a
changing automotive safety application.
GMSL2 Overview
GMSL2 uses a packet-based protocol to seamlessly share the link bandwidth between communication channels in a
flexible way. Bandwidth allocation is dynamic so that if a certain channel is not active, it does not consume any link
bandwidth, and all the remaining active channels can share the full link bandwidth. Maximum packet size is limited to
prevent a single channel from utilizing the link bandwidth for an extended time. The same data protocol is used on forward
and reverse channels and for both video and control-channel data.
GMSL2 provides extensive data integrity and safety features. Some of these features include CRC error detection that
enables identification of errors in the video or control-data streams. In the case of control-channel CRC errors, automatic
retransmission of the flagged packet maximizes control-channel speed and reliability.
GMSL2 devices incorporate numerous link-margin optimization and monitoring functions that ensure high link margin
and robust functionality. Continuous adaptive equalization occurs every second to optimize link margin to adapt to
environmental changes and cable aging. An eye-opening monitor function provides continuous link-margin diagnosis.
Tunneling vs. Pixel Modes

The MAX96724/F/R is specifically designed for Advanced Driver Assistance Systems (ADAS), where data integrity is a
key safety requirement. Prior GMSL2 solutions supported only Pixel mode for transporting received data from a MIPI
CSI-2 interface over the GMSL link. In Pixel mode, the CSI-2 data is depacketized at the serializer's CSI-2 input interface.
The received CSI-2 packet header includes an error correction code (ECC), which is checked and removed at the
serializer input. The received CSI-2 packet footer contains the CSI-2 cyclic redundancy check (CRC), which is also
checked and removed.
Video line pixel data and video routing information, such as data type and virtual channel, are received and extracted at
the CSI-2 interface. Both video pixel data, control channel data, and routing information are input into a scheduler in the
serializer. The scheduler packetizes and encapsulates the data using GMSL protocol and sequences data transmission
across the GMSL link. Video data transport across the GMSL link is protected by line CRCs that are part of the GMSL
protocol.
The deserializer receives the GMSL packets and verifies the GMSL2 line CRCs. A CSI-2 interface at the deserializer
output encapsulates each video line using CSI-2 protocol and outputs it in CSI-2 format across a CSI-2 interface to the
SoC. See Figure 15.
CSI-2 CRC GMSL CRC CSI-2 CRC
SENSOR MIPI SERIALIZER PIXEL DATA PACKETS DESERIALIZER MIPI SOC
CHECK AND REMOVE CALCULATE CHECK AND CALCULATE CHECK AND REMOVE
CSI-2 CRC GMSL CRC REMOVE GMSL CSI-2 CRC CSI-2 CRC
CRC
Figure 15. Pixel Mode
In Tunneling mode, the received CSI-2 ECC byte and CRC bytes are checked at the serializer input. These, as well as
routing and pixel data, are received as a byte stream. The byte stream is split into smaller packets that are encapsulated
using GMSL2 protocol.
The serializer adds a line CRC, protecting transmission across the GMSL channel. This CRC covers the entire GMSL2
packetized byte stream for a video line. See Figure 16. The deserializer receives the transmitted GMSL2 packets

and control channel packets, checks and removes the GMSL CRC, separates the video data from control data, and
reconstructs each received CSI-2 packet that is the output to the SoC on a CSI-2 interface. A CRC is calculated on the
video data output on the CSI-2 interface. This CRC is compared by the deserializer to the original CRC received from the
video source. This comparison guarantees that the entire data packet output on the standard MIPI interface is identical
to that received at the serializer input. Tunneling mode is more bandwidth-efficient if multiple data types are being sent.
Because data received at the serializer input and data output from the deserializer are verified to be identical, Tunneling
mode does not allow for the processing of video data, such as watermarking or lossy data compression. Different data
rate and different lane count on serializer and deserializer are still possible. See Figure 16.
CSI-2 CRC
GMSL CRC
SENSOR MIPI SERIALIZER MIPI CSI-2 PACKETS DESERIALIZER MIPI SOC
CHECK CSI-2 CALCULATE CHECK AND CHECK AND REMOVE

CRC GMSL CRC REMOVE GMSL CSI-2 CRC
CRC
Figure 16. Tunneling Mode
Video Pipes, Aggregation, and Replication

In GMSL2 mode, the transmission of video data is based on the concept of video pipes. Carrying data in pipes allows
GMSL2 to bridge different digital video interfaces.
A pipe carries a video stream (or streams) and video synchronization data. Each pipe operates in one of three modes.
In all modes, a pipe can carry multiple concurrent video streams, with each stream having different virtual channels and
data types.
Mode 1: Streams with constant bits per pixel (bpp) of up to 24bpp. The bpp of the streams must be the same.
Mode 2: Streams with 16, 14, 12, 10 or 8bpp. Streams less than 16bpp are padded with zeros.
Mode 3: Streams with two different bpp. The bpp of one stream must be twice the bpp of the other stream. The
higher bpp stream maximum is 24bpp.
Modes 1 and 3 carry data at full bandwidth but put more restrictions on bpp than mode 2. Mode 2 allows streams with
different bpp, but streams of less than 16bpp are carried using more bandwidth than necessary on the GMSL2 link
because of zero padding. Mode 1 or 3 are sufficient for most applications. Mode 2 requires less programming and is
more convenient if the application does not require maximum link bandwidth.
The MAX96724/F/R has four GMSL input ports, each accommodating up to four independent pipes in GMSL2 mode.
In GMSL1 mode, only a single, dedicated video pipe is available per link. Each pipe can be mapped to any one of the
incoming GMSL video streams; as a result, up to four pipes can be mapped to a single GMSL2 output port. In GMSL1
mode, a total of four video pipes is available with a fixed mapping between each GMSL1 input and a single internal pipe
as shown in Figure 17. In mixed GMSL1/GMSL2 systems, the GMSL1 input streams are routed to the dedicated GMSL1
pipe associated with each active GMSL1 input. Incoming GMSL2 streams can be routed to any of the available pipes
that are not dedicated to an active GMSL1 input. The pipes are available sources for synchronous aggregation.

GMSL1 Fixed Pipe Routing
SIOA GMSL1 GMSL1 - PIPE X - SIOA

CSI-2 D-PHY
CONTROLLER 0
SIOB GMSL1 GMSL1 - PIPE Y - SIOB C
AGGREGRATOR A A
SIOC GMSL1 GMSL1 - PIPE Z - SIOC D
CSI-2
CONTROLLER 1
SIOD GMSL1 GMSL1 - PIPE U - SIOD
AGGREGRATOR B
EACH AGGREGATOR CAN

4X GMSL INPUTS EACH PIPE INCLUDES FEED ANY CSI CONTOLLER
VPG, VTG, PRBS, LINE MEMORY+CRC, VC/DT
Figure 17. Video Pipes and Routing
A single camera requires either one or two pipes for Pixel mode depending on whether it supports high dynamic range
(HDR) imaging. Tunnel mode uses only one pipe, even if there are multiple data types and VC's on the incoming GMSL
input. A Pixel mode example is shown in Figure 18 illustrates an application in which one link interfaces to an HDR
camera (two dedicated pipes) while the other two links stream video from standard cameras (one dedicated pipe).
4X INTERNAL DATA PIPES

SHARED BY 4X GMSL INPUTS
CAM (A) – HDR + 2 DTs MAX INCOMING PIPES IS 4 EACH AGGREGATOR CAN
D-PHY
FEED ANY CSI CONTOLLER
IM1 HB 256kb
SIOA PIPE X DT/VC REMAP C
PORT D
SRAM CSI-2
VB A
256kb CONTROLLER 0
CAM (B) – RAW 16 DT/VC REMAP D
PIPE Y SRAM
IM2 HB AGGREGRATOR A D-PHY
SIOB 256kb
PIPE Z DT/VC REMAP
VB SRAM C
PORT C
CSI-2
CAM (C) – RAW 12 CONTROLLER 1 A
256kb
PIPE U DT/VC REMAP D
IM3 HB SRAM
AGGREGRATOR B
SIOC
VB EACH PIPE CAN CSI PORT C AND OUTPUT
ONE DATA ROUTE TO ANY FIRST-COME-FIRST-SERVE (FCFS)
TYPE AGGREGATOR
LP LINE IM1 LP LINE IM2 LP LINE IM3 LP
Figure 18. MAX96724/F/R Video Pipe Example with Partial FCFS Aggregation
When video data is received by one of the MAX96724/F/R's GMSL inputs, it is immediately forwarded to one of the
internal video pipes. Note that a single pipe can carry many separate streams, provided that they comply with certain
mode-dependent format limitations. The channel ID of each incoming CSI stream can be reassigned if desired. Video
data then fills the dedicated line buffer associated with each pipe as controlled by the sync data. Each line buffer can be
routed to any one of the four aggregators, which can be used to combine data from multiple video pipes and/or virtual

channels within a single CSI-2 stream. Only one aggregator can read data out of a given buffer. Up to four pipes can be
aggregated by one aggregator. Video data can be routed according to DT or VC based on the source CSI-2 packet’s DT/
VC, or it can be routed by a DT/VC assigned in the MAX96724/F/R.
Aggregated data is typically read out from line memory on a first come first served (FCFS) basis. In this case, data from
all four video pipes are visible to the aggregators. The order in which the line memories reach filled status is the order
in which they are read out. In this case, the outgoing CSI data streams can be viewed as independent parallel streams
that may have independent timing, although they may be effectively synchronized depending on the nature of the video
sources used. Alternatively, data can be aggregated in specific sequences corresponding to side-by-side (4WxH) or line-
interleaved (Wx4H) output formats. All data sources must use the same resolution and virtual channel assignment, and
they must be precisely synchronized. The resulting output is a single stream consisting of a superframe that holds video
data from all aggregated streams. Synchronous aggregation can effectively provide a single combined image output from
multiple sensors, such as a single image surround-view stream. Side-by-side aggregation combines incoming streams
from up to four sensors, resulting in a frame that has equal height and up to 4x the width of single sensor output. Pixel
mode supports both 4WxH and Wx4H modes. Tunnel mode only supports Wx4H mode.
The MAX96724/F/R includes features that minimize the disruption resulting from one of the links failing in multi-link
systems that use aggregation. With systems using synchronous aggregation, the MAX96724/F/R masks the failed link's
video data with 0's. This allows overall timing to continue as expected, enabling the remaining video streams to proceed
uninterrupted. Similarly, with systems using FCFS aggregation, the video stream associated with a link that has failed will
be terminated at the end of a line to avoid a sudden disruption that may impact other streams using the same physical
interface.
The MAX96724/F/R supports a new feature called "cut-through" in the Tunnel mode that allows the controller to start
reading from the memory sooner. Register PKT_START_ADDR can adjust when to start reading from memory after
written to. This allows an extension to the video line memory for lines longer than 4096 pixels and can also reduce latency
by allowing the ability to read the memory quicker. Once data is read out, it cannot be read out a second time. Figure 19
shows the MAX96724/F/R memory operation.
DE
MEMORY WRITE MEMORY WRITE
Read Pixel Mode Read Pixel Mode
Read Tunnel Mode – TUN_PKT_START_ADDR Read Tunnel Mode – TUN_PKT_START_ADDR
Figure 19. GMSL2 Memory Reading and Writing
To prevent buffer overflow, the CSI-2 port data rate must be programmed to an equal to or greater rate than the incoming
data rate. Programming the output rate to be faster than the bandwidth of the incoming video or data increases packet
spacing (LP time between packets). The video memory has built-in overflow detection - BACKTOP11. This occurs when
the video bandwidth is higher than the data going out on the MIPI port, not giving a chance for the memory to empty. No
reformatting of the data occurs in Tunnel mode. It is a requirement for functional safety that the video data is unchanged,
such that it can be compared against the tunneled CSI-2 CRC by the host. After data exits a retiming buffer, it goes
through a data type (DT) and virtual channel (VC) reassignment stage. If the video source has a CSI-2 output, packets
DT and VC can each be left as-is or reassigned by register programming.
The MAX96724/F/R GMSL2 protocols allocate 24 bits of each packet for video content to effectively use the GMSL2
forward channel bandwidth. The serializer and MAX96724/F/R contain the double Pixel mode, which place x2 8bpp/

10bpp/12bpp into the same packet. See bpp8dbl / bpp10dbl / bpp12dbl bitfields in the register map for more information.
Frame Sync
In some camera applications, a frame-sync signal is required by the sensors to synchronize the output of a frame with
the other cameras in the system. The MAX96724/F/R can generate FSYNC signal internally or receive an FSYNC signal
from external SoC and send it over to the sensor through the GMSL reverse channel. MFP0 or MFP7 is programmed to
receive the external FSYNC signal and MAX96724/F/R are programmed as slaves. To generate the internal FSYNC, the
MAX96724/F/R are programmed as masters. Refer to the MAX96724/F/R User Guide for more information.
Vertical and Data Enable or Data Valid Sync Outputs

The MAX96724/F/R can output the vertical sync (VS) and data enable/data valid (DE/DV) of a video stream to monitor
the video timing by a processor. This feature provides access to VS and DE/DV signals not available directly at the CSI-2
output. Refer to the MAX96724/F/R User Guide for how to use this feature.
D-PHY to C-PHY Packet Conversion

MAX96724/F/R has the ability to convert Imager sensor D-PHY packets to C-PHY packets while still maintaining ASIL
functionality. This is done automatically when C-PHY is selected.
Control Channel Latency

All control channels exhibit finite latency. Typical latency for each function is given in Table 6. For I2C, which requires
an immediate ACK from the receiver following each byte, clock stretching is used to temporarily pause communication
as the ACK propagates through the control channel. All I2C devices that communicate over the link must support clock
stretching.
Table 6. Control Channel Latency
FUNCTION FORWARD REVERSE
I 2C < 10μs < 10μs
I 2C
The MAX96724/F/R includes two independent I2C interfaces. These interfaces are the only means by which local or
remote (serializer) registers can be accessed. The master μC is typically located on the MAX96724/F/R side of the link,
although this is not strictly required, and communication can be initiated by a device on either side of the link. For correct
operation, the control channel of each of the MAX96724/F/R's links must be configured in the same mode as the serializer
connected to that link. I2C outputs are open drain and require appropriately-sized external pullup resistors for proper
operation.
In general, each of the I2C ports can be used to access internal MAX96724/F/R registers, remote serializer registers, and
remote peripheral registers. Both ports provide concurrent local register access. Each GMSL2 link provides a dedicated
control channel through which any one of the ports can communicate with either a remote serializer connected to that
link or with any remote peripherals connected to the serializer's control channel port. Routing of the I2C ports to each
control channel is independent, enabling different combinations of local ports to access the control channel and the
tunneled channels of each GMSL link. Regarding local (deserializer) register access, both ports provide simultaneous
local access with lower indexed ports having the highest priority. In I2C mode, a local port's local register access cannot
be disconnected unless the port is disabled. Therefore, all active I2C ports have local register access at all times.
Remote serializer registers are visible only by means of the dedicated GMSL2 link control channel, which supports only
a single port. Therefore, only one port at a time can access remote registers over a given link. By default, port 0 is routed
to the control channel of each link. With appropriate configuration, port 1 can also be routed to the control channel to
support remote serializer register access. Any links operated in GMSL1 mode provide only a single control channel with
both serializer and peripheral register access.

GMSL LOCAL
LOCAL PORT A REGISTERS
REGISTERS
GMSL CONTROL CHANNEL
MAIN CONTROL CONTROL I2C PORT 0
PERIPHERALS
I 2C CHANNEL GMSL LINK CHANNEL XOVER I2C PORT 1

TUNNEL (2X) PASS-THRU
PASS- TUNNELS (2X)
CONTROL
THROUGH ALL I2C PORTS
GMSL CHANNEL XOVER
I2C (2X) PROVIDE LOCAL
PORT B PASS-THRU
REGISTER ACCESS
GMSL SERIALZER CONTROL CHANNEL CONTROL
PROVIDES REMOTE GMSL CHANNEL XOVER EACH I2C PORT CAN
SERIALIZER AND PORT C PASS-THRU BE ROUTED TO ANY/
PERIPHERAL ACCESS ALL GMSL LINKS
CONTROL
TUNNELED CHANNELS GMSL CHANNEL
PROVIDES REMOTE XOVER
PORT D
PERIPHERAL ACCESS PASS-THRU
GMSL1 LINKS DO NOT

MAX96724
INCLUDE TUNNELED
CHANNELS
Figure 20. I2C Routing

General Purpose Inputs and Outputs (GPIO)

Multifunction pins can be programmed as GPI (input), GPO (push-pull output or open-drain output, although some MFP
pins only support open-drain output), or GPIO (bidirectional input/output). Most GPIOs can also be programmed for 1MΩ
or 40kΩ pullup or pulldown (or none). The state of each GPIO can be read or written by register either locally, using any of
the two I2C ports, or remotely via the I2C interface that is routed to the GMSL2 control channel. Refer to the MAX96724/
F/R User Guide for proper GPIO setup.
Link Error Generator

Each of the GMSL links includes a configurable error generator that injects errors into the outgoing data stream
immediately prior to transmission. The deserializer injects errors into the reverse channel; the serializer injects errors into
the forward channel. The receiving device detects, counts, and flags the errors, enabling a thorough validation of the
system's response to error conditions of varying severity.
GMSL1 Backwards Compatibility

The MAX96724/F/R is designed to pair with any GMSL1 serializer with high immunity mode (HIM). However, the device
does not support the entire range of features available across all GMSL1 serializers. GMSL1 backward compatibility is
only supported with forward link rates from 500Mbps to 3.12Gbps and a reverse link rate of 1Mbps. When paired with
a GMSL2 serializer for GMSL1 operation, both devices must be configured to use GMSL1 compatibility mode. When
the MAX96724/F/R is paired with a legacy GMSL1 only serializer, the MAX96724/F/R must be configured for GMSL1
compatibility mode, and the available forward link rate is reduced to the rate limitations of the specified GMSL1 serializer.
Refer to the MAX96724/F/R User Guide for more information.
Video PRBS Generator/Checker

GMSL2 devices include built-in video PRBS generators/checkers for video link testing for pixel mode operation. For
example, a serializer's PRBS generator can be used in conjunction with a deserializer's PRBS checker to test the GMSL2
video channel that connects the two devices. Here, the MAX96724/F/R's PRBS checker functionality compares the
received PRBS stream with the predicted PRBS data to establish any errors. To run the video PRBS test, refer to the
MAX96724/F/R GMSL2 User Guide for more information.
RoR (Reference over Reverse)

Reference clock over reverse channel (RoR) is a GMSL clock operating mode where the serializer receives its reference
clock from the deserializer over the GMSL link. RoR eliminates the need for a crystal oscillator on the serializer side of
the link.
In RoR mode, the serializer’s timing reference is extracted from the signal sent on the reverse channel. The recovered
clock coming from the deserializer is used by the serializer on-chip phase-locked loop (PLL) to synthesize the serializer
output reference clock RCLKOUT.
RoR mode is automatically supported when the serializer is configured in RoR mode.
The removal of the crystal oscillator in RoR provides several advantages:
● Reduced system cost
● Increased reliability
● Reduced board area
● Simplified board layout
CFG Latch at Power-up Pins

At power-up or after reset, the voltages at the CFG0 and CFG1/MFP6 pins are sampled. The sampled level is used to
set the initial value of certain registers.

VDDIO VDDIO
R1 MAX96724/F/R
CFG1/
CFG0
MFP6
R2
Figure 21. Configuration Pin Connection
The voltage level at each pin is set by an external precision resistor divider connected between VDDIO and ground. Figure
21, Table 7, and Table 8 show the recommended resistor values to select each configuration. The voltage level at the
CFG pins is typically latched 11ms after supplies reach the minimum levels required. CFG pins must not be loaded with
more than 10pF at power-up to ensure the proper voltage level.
Table 7. CFG0 Input Map
SPECIFICATION SUGGESTED RESISTOR VALUES
MAPPED CONFIGURATION
(NOTE a) (NOTES b, c)
(PERCENTAGE OF VDDIO) (1% TOLERANCE)
I2CSEL I2CSEL
MIN TYP MAX R1 (Ω) R2 (Ω) DEVICE ADDRESS
MAX96724/F MAX96724R
0.0% 0.0% 11.7% OPEN 10k 0x4E
16.9% 20.2% 23.6% 80.6k 20.5k 0x5C
I 2C I 2C
28.8% 31.2% 35.5% 68.1k 32.4k 0x9C
40.7% 44.0% 47.4% 56.2k 44.2k 0x9E
All other voltage levels are reserved or not applicable.
Table 8. CFG1/MFP6 Input Map

CFG1/MFP6 INPUT SUGGESTED RESISTOR
VOLTAGE VALUES MAPPED CONFIGURATION
(PERCENTAGE of VDDIO) (±1% TOLERANCE) (NOTE d)
(NOTES a, b) (NOTE c)
CX/ GMSL1/
MIN TYP MAX R1 (Ω) R2 (Ω) MAX96724 MAX96724F/R
STP GMSL2
0.0% 0.0% 11.7% OPEN 10000 6Gbps
GMSL2 3Gbps
16.9% 20.2% 23.6% 80600 20500 3Gbps
COAX
HIM
28.8% 32.1% 35.5% 68100 32400 GMSL1 HIM Disabled
Disabled
40.7% 44.0% 47.9% 56200 44200 6Gbps
GMSL2 3Gbps
52.6% 56.0% 59.3% 44200 56200 STP 3Gbps
64.5% 67.9% 71.2% 32400 68100 GMSL1 HIM Enabled HIM Enabled

Table 8. CFG1/MFP6 Input Map (continued)

CFG1/MFP6 INPUT SUGGESTED RESISTOR
VOLTAGE VALUES MAPPED CONFIGURATION
(PERCENTAGE of VDDIO) (±1% TOLERANCE) (NOTE d)
(NOTES a, b) (NOTE c)
HIM
76.4% 79.8% 83.1% 20500 80600 HIM Disabled
Disabled
88.3% 100% 100% 10000 OPEN COAX GMSL1 HIM Enabled HIM Enabled
Notes:
a. CFG0 or CFG1/MFP6 input voltage to exceed the maximum or minimum limits.
b. Until the input voltage is latched, any load on CFG0 or CFG1/MFP6 (other than R1 and R2) must be ≥ 25 x (R1 +
R2). Load capacitance (including R1 and R2) must be lumped load ≤ 10pF.
c. Each resistor in the voltage divider must be ≤ 100kΩ.
d. GMSL1 default BWS = 0 (24 bit).
Multifunction Pin Configuration

MAX96724/F/R has several possible MFP states, but only one can be used at a time.
The Pin Descriptions section shows default and alternate functions for each MFP, listed in order of priority (highest priority
listed first). [[MFP Pin Function Map]] also shows priority, with highest priority on the left. A higher priority function must
be disabled when a lower-priority function is enabled, both by register writes.
Table 9. MFP Pin Function Map
HIGHEST LOWEST
PIN DECREASING PRIORITY FROM LEFT TO RIGHT DEFAULT
PRIORITY PRIORITY
Line GPI0
MFP0 FSYNC GPIO0 Disabled*
Fault 0 (GMSL1)
CNTL0 CNTL2 Line GPI1
MFP1 VS0/DE0/HS0 GPIO1 Disabled*
(GMSL1) (GMSL1) Fault 1 (GMSL1)
CNTL1 CNTL3 Line GP12
MFP2 GPIO2 Disabled*
(GMSL1) (GMSL1) Fault 2 (GMSL1)
CNTL4 Line GP13
MFP3 VS1/DE1/HS1 GPIO3 Disabled*
(GMSL1) Fault 3 (GMSL1)
MFP4 LOCK GPIO4 LOCK
MFP5 ERRB ERRB/LOCK GPIO5 ERRB
CFG1 GPIO
MFP6 GPO6 CFG1
(Startup Only) Aggregation
FSYNC VS2/DE2/
MFP7 SDA1 GPIO7 SDA1
(Alternate) HS2
VS3/DE3/
MFP8 SCL1 GPIO8 SCL1
HS3
*Disabled represents a high impedance state where the MFP pin receiver is disabled and the 1MΩ internal pull-down
resistor enabled.
Power-Up and Link Start-Up

GMSL2 ICs are in power-down mode when the PWDNB pin is low or when any of the power supplies are disabled. When
in power-down mode, the device configuration is reset to the default power-up state.
The serializer and deserializer can power up in any order. After PWDNB is released and all power supplies have settled,
each device starts its power-up sequence and performs the following operations:

1. Latch CFG pin states and set internal registers accordingly. See Table 7 and Table 8.
2. Main control channel I2C is functional on local side. Local device registers are writable and readable. Perform local
configuration as needed to establish links.
3. Links are established based on default configuration specified by CFG[1:0] pin power-up state, which specifies the
global configuration for all links.
4. Perform link calibration, equalizer adaptation, and data channel locking. LOCK pin is driven high when all enabled
links are locked and ready. The status of individual links can be monitored by reading individual link lock status bits.
5. Control channel is available from/to the remote side.
Device Reset
There are three general reset options available through register writes:
1. RESET_ALL resets all blocks, including all registers and digital and analog blocks. This bit is auto cleared.
2. Setting RESET_LINK_x resets all GMSL PHY related logic as well as the data pipeline for the specified link (where x
is A, B, C, or D). After this bit is set, all local control registers are still accessible. The link remains in RESET until the
bit is cleared.
3. Setting RESET_ONESHOT_x resets all GMSL PHY related logic and the data pipeline for the associated link (where
x is A, B, C, or D). This bit is auto cleared.
When configuring a GMSL link, program registers that control operation of the desired GMSL link first, then issue a
RESET_LINK_x or RESET_ONESHOT_x bits.
Link and Video Lock

GMSL2 Link Lock
ALL SUPPLIES WITHIN LIMITS

DEVICE A
POWER
DEVICE A PWDNB PIN VIH

OR
RESET_LINK BIT
ALL SUPPLIES WITHIN LIMITS

DEVICE B
POWER
tRD
DEVICE B PWDNB PIN VIH

OR
RESET_LINK BIT tLOCK2
VOH
LOCK
Figure 22. GMSL2 Lock Time
Figure 22 illustrates the sequence that is used to characterize GMSL2 link lock time. Device A is the first device (serializer
or deserializer) to power-up or resume operation from a RESET_LINK state. Device B is the device (deserializer or
serializer) at the other end of the GMSL link.
Link lock indicates that the data receive paths are locked (forward channel in the deserializer, reverse channel in the
serializer). Video and control channel functions (I2C, GPIO) can be used immediately after link lock is asserted.
The device will establish single link GMSL2 connectivity and link lock automatically following power-up. This is an
indication that the cable is plugged in and the system is up and running. Lock is obtained with no interaction between

the μC and GMSL devices. Both serializers and deserializers have an open-drain LOCK output pin and a related status
register.
The GMSL2 link uses the crystal as the reference clock for GMSL2 links, so a valid video input (PCLK) is not needed for
the GMSL2 link to lock.
Notes:
1. The lock sequence is initiated by the release of the PWDNB pin or the RESET_LINK bit in either the serializer or the
deserializer.
2. Lock time is measured from the later of PWDNB or RESET_LINK release in either the serializer or deserializer to
LOCK being asserted.
3. The PWDNB/RESET_LINK states on the two sides of the link must have overlap when both devices are in PWDNB/
RESET_LINK mode prior to the lock process starting.
4. If RESET_LINK is used to initiate lock, PWDNB is assumed to be high after power-up (normal operation).
5. If PWDNB is used to initiate the lock, RESET_LINK is assumed to be low after power-up (normal operation).
6. To achieve the specified lock time, time delay tRD (delay between release of the PWDNB/RESET_LINK on the two
devices) must be less than the threshold specified in Note 9. Contact the factory for guidance if this timing cannot be
guaranteed.
7. Lock time and maximum allowed tRD vary between different families of GMSL devices. They depend on the
characteristics of both the serializer and the deserializer. The typical lock time of a specific link can be best estimated
as the longer of the lock times specified in each device data sheet. Similarly, the maximum permissible tRD for a
specific link can be estimated as the smaller of the values specified in each device data sheet. For further guidance,
contact the factory.
8. If there is an instantaneous interruption to link lock, a period of 100ms following loss of lock should be provided
to enable the link to automatically recover prior to any ECU initiated resets being issued. This will minimize any
disruptions caused by a transient loss in connectivity.
Video Lock
Video lock indicates that the deserializer is receiving valid video data. After the GMSL2 link is locked, the deserializer
video output PLL starts its locking sequence. The deserializer normally starts outputting video data several milliseconds
after it asserts line lock, provided that it is receiving video packets from the serializer. Video lock status is typically read
from a register.
Spread-Spectrum Clocking
MAX96724/F/R can accept forward channel 6/3Gbps spread spectrum which can be used to mitigate electromagnetic
interference emitted from the device. Narrow frequency peaks are reduced by modulating the internal 6GHz clock at
a rate of 25kHz with a saw-tooth profile. To enable this functionality, refer to the GMSL2 User Guide and contact the
factory. Registers are not visible to customers for this feature.
Error and Fault Condition Monitoring

The MAX96724/F/R includes an open-drain, multipurpose error reporting, and interrupt status output. The active-low
ERRB pin is driven by the logical OR of a wide variety of error and event status indicators. Errors can be automatically
forwarded across the link from the serializer so certain serializer side errors, such as CSI-2 input CRC errors, can
automatically be flagged by the MAX96724/F/R's LOCK output. The ability of each error condition to drive ERRB is
maskable by register settings. Each error and event that can drive ERRB has a status flag within a sub-block of registers,
so the reason for assertion of ERRB can be determined by reading the register status.
GPIO Aggregation
MFP6 has the ability to aggregate the error signals from the serializer, image sensor, and other peripherals connected
to the same quad deserializer. Aggregation allows for a single pin on the quad deserializer to be the error-reporting
mechanism for everything connected upstream. This reduces the number of connections between deserializer MFPs and
SoC inputs.
More information on this feature can be found in the MAX96724/F/R User Guide.

EMB8 — ERRB Forwarding

MAX96724/F has the ability to capture any ERRB information and forward this information to an EMB8 packet on the
MIPI data. The EMB8 packet can be inserted at the start of frame/end of frame. More information on this feature can be
found in the MAX96724/F/R User Guide.
Functional Safety Features

The MAX96724/F integrates a number of safety features. For more information on these safety features, contact the
factory for the MAX96724/F Safety Items and Implementation Guide.

Ordering Information
PART NUMBER TEMP RANGE PIN-PACKAGE SPEED
MAX96724GTN/VY+ -40°C to +105°C 56 TQFN-SW-EP 6Gbps
MAX96724GTN/VY+T -40°C to +105°C 56 TQFN-SW-EP 6Gbps
MAX96724FGTN/V+ -40°C to +105°C 56 TQFN-EP 3Gbps
MAX96724FGTN/V+T -40°C to +105°C 56 TQFN-EP 3Gbps
MAX96724FGTN/VY+ -40°C to +105°C 56 TQFN-SW-EP 3Gbps
MAX96724FGTN/VY+T -40°C to +105°C 56 TQFN-SW-EP 3Gbps
MAX96724RGTN/V+ -40°C to +105°C 56 TQFN-EP 3Gbps
MAX96724RGTN/V+T -40°C to +105°C 56 TQFN-EP 3Gbps
/V Denotes an Automotive Qualified Product.
Y Denotes Wettable Flank.
+ Denotes a lead(Pb)-free/RoHS-compliant Package.
T Denotes tape-and-reel.
EP Denotes Exposed Pad.

Register Map
MAX96724/F/R
ADDRESS RESET NAME MSB LSB
DEV
CFG_BL
0x00 0x4E REG0[7:0] DEV_ADDR[6:0]
OCK
0x01 0xC0 REG1[7:0] RSVD[1:0] DIS_LOC_CC[1:0] – – – –
DIS_REM_CC_D[1: DIS_REM_CC_C[1: DIS_REM_CC_B[1:0 DIS_REM_CC_A[1:0
0x03 0xAA REG3[7:0]
0] 0] ] ]
VID_EN_ VID_EN_ VID_EN_ VID_EN_
0x04 0x0F REG4[7:0] – – – –
3 2 1 0
ERRB_L
LOCK_E ERRB_E LOCK_C ERRB_M
0x05 0xC0 REG5[7:0] OCK_OE – – RSVD
N N FG ST_RST
N
GMSL2_ GMSL2_ GMSL2_ GMSL2_ LINK_EN LINK_EN LINK_EN LINK_EN
0x06 0xFF REG6[7:0]
D C B A _D _C _B _A
0x07 0x00 REG7[7:0] CC_CROSSOVER_SEL[3:0] RSVD[3:0]
LOCKED
0x0A 0x00 CTRL12[7:0] RSVD RSVD – – – – –
_B
LOCKED
0x0B 0x00 CTRL13[7:0] RSVD RSVD – – – – –
_C
LOCKED
0x0C 0x00 CTRL14[7:0] RSVD RSVD – – – – –
_D
0x0D 0xA2 REG13[7:0] DEV_ID[7:0]
TX_RATE_PHYB[1: RX_RATE_PHYB[1: TX_RATE_PHYA[1: RX_RATE_PHYA[1:
0x10 0x22 REG26[7:0]
0] 0] 0] 0]
TX_RATE_PHYD[1: RX_RATE_PHYD[1: TX_RATE_PHYC[1: RX_RATE_PHYC[1:
0x11 0x22 REG27[7:0]
0] 0] 0] 0]
TOP_CTRL
0x12 0x00 PWR0[7:0] VDDBAD_STATUS[2:0] CMP_STATUS[4:0]
RESET_
0x13 0x00 PWR1[7:0] RSVD RSVD[5:0]
ALL
RESET_ RESET_ RESET_ RESET_
RESET_ RESET_ RESET_ RESET_
0x18 0x00 CTRL1[7:0] ONESH ONESH ONESH ONESH
LINK_D LINK_C LINK_B LINK_A
OT_D OT_C OT_B OT_A
LOCKED CMU_LO LOCK_P
0x1A 0x10 CTRL3[7:0] RSVD RSVD RSVD[1:0] ERROR
_A CKED IN
0x22 0xFF CTRL11[7:0] RSVD CXTP_D RSVD CXTP_C RSVD CXTP_B RSVD CXTP_A
DEC_ER DEC_ER DEC_ER DEC_ER
0x25 0x0F INTR2[7:0] RSVD RSVD RSVD RSVD R_OEN_ R_OEN_ R_OEN_ R_OEN_
D C B A
DEC_ER DEC_ER DEC_ER DEC_ER
0x26 0x00 INTR3[7:0] RSVD RSVD RSVD RSVD R_FLAG R_FLAG R_FLAG R_FLAG
_D _C _B _A
EOM_E EOM_E EOM_E EOM_E
LFLT_IN
0x27 0xF4 INTR4[7:0] RR_OEN RR_OEN RR_OEN RR_OEN RSVD – –
T_OEN
_D _C _B _A


EOM_E EOM_E EOM_E EOM_E
LFLT_IN
0x28 0x00 INTR5[7:0] RR_FLA RR_FLA RR_FLA RR_FLA RSVD – –
T
G_D G_C G_B G_A
VPRBS_ FSYNC_
G1_D_E G1_C_E G1_B_E G1_A_E LCRC_E REM_ER
0x29 0xFF INTR6[7:0] ERR_OE ERR_OE
RR_OEN RR_OEN RR_OEN RR_OEN RR_OEN R_OEN
N N
G1_D_E G1_C_E G1_B_E G1_A_E LCRC_E VPRBS_ FSYNC_
REM_ER
0x2A 0x00 INTR7[7:0] RR_FLA RR_FLA RR_FLA RR_FLA RR_FLA ERR_FL ERR_FL
R_FLAG
G G G G G AG AG
IDLE_ER IDLE_ER IDLE_ER IDLE_ER
0x2B 0x00 INTR8[7:0] RSVD RSVD RSVD RSVD R_OEN_ R_OEN_ R_OEN_ R_OEN_
D C B A
IDLE_ER IDLE_ER IDLE_ER IDLE_ER
0x2C 0x00 INTR9[7:0] RSVD RSVD RSVD RSVD R_FLAG R_FLAG R_FLAG R_FLAG
_D _C _B _A
RT_CNT RT_CNT RT_CNT RT_CNT MAX_RT MAX_RT MAX_RT MAX_RT
0x2D 0x0F INTR10[7:0]
_OEN_D _OEN_C _OEN_B _OEN_A _OEN_D _OEN_C _OEN_B _OEN_A
RT_CNT RT_CNT RT_CNT RT_CNT MAX_RT MAX_RT MAX_RT MAX_RT
0x2E 0x00 INTR11[7:0] _FLAG_ _FLAG_ _FLAG_ _FLAG_ _FLAG_ _FLAG_ _FLAG_ _FLAG_
D C B A D C B A
ERR_TX
0x2F 0x9F INTR12[7:0] – – ERR_TX_ID[4:0]
_EN
ERR_RX
ERR_RX
0x30 0xDF INTR13[7:0] _RECVE – ERR_RX_ID_A[4:0]
_EN_A
D_A
ERR_RX
ERR_RX
0x31 0xDF INTR14[7:0] _RECVE – ERR_RX_ID_B[4:0]
_EN_B
D_B
ERR_RX
ERR_RX
0x32 0xDF INTR15[7:0] _RECVE – ERR_RX_ID_C[4:0]
_EN_C
D_C
ERR_RX
ERR_RX
0x33 0xDF INTR16[7:0] _RECVE – ERR_RX_ID_D[4:0]
_EN_D
D_D
0x35 0x00 CNT0[7:0] DEC_ERR_A[7:0]
0x36 0x00 CNT1[7:0] DEC_ERR_B[7:0]
0x37 0x00 CNT2[7:0] DEC_ERR_C[7:0]
0x38 0x00 CNT3[7:0] DEC_ERR_D[7:0]
0x39 0x00 CNT4[7:0] IDLE_ERR_A[7:0]
0x3A 0x00 CNT5[7:0] IDLE_ERR_B[7:0]
0x3B 0x00 CNT6[7:0] IDLE_ERR_C[7:0]
0x3C 0x00 CNT7[7:0] IDLE_ERR_D[7:0]
VID_PXL_CR VIDEO_ VIDEO_ VIDEO_ VIDEO_ VID_PXL VID_PXL VID_PXL VID_PXL
C_ERR_VIDE MASKE MASKE MASKE MASKE _CRC_E _CRC_E _CRC_E _CRC_E
0x44 0xFF
OMASK_OEN D_3_OE D_2_OE D_1_OE D_0_OE RR_OEN RR_OEN RR_OEN RR_OEN
[7:0] N N N N _D _C _B _A
VID_PXL_CR VIDEO_ VIDEO_ VIDEO_ VIDEO_
VID_PXL VID_PXL VID_PXL VID_PXL
C_VIDEOMA MASKE MASKE MASKE MASKE
0x45 0x00 _CRC_E _CRC_E _CRC_E _CRC_E
SK_INT_FLA D_3_FL D_2_FL D_1_FL D_0_FL
RR_D RR_C RR_B RR_A
G[7:0] AG AG AG AG


VDDBAD
PWR_STATU
0x48 0xC1 _INT_OE RSVD – RSVD – – RSVD[1:0]
S_OEN[7:0]
N
CMP_ST CMP_ST
PWR_STATU VDDBAD CMP_ST CMP_ST
ATUS_V ATUS_V
0x49 0x00 S_OV_FLAG[ _INT_FL RSVD RSVD RSVD ATUS_V ATUS_v
DD12_O DD18_O
7:0] AG DD_OV ddio_ov
V V
VDDCM CMP_VT
VDDCMP_MA
0x4A 0xA7 P_INT_O – ERM_M VDDCMP_MASK[4:0]
SK[7:0]
EN ASK
VDDCMP_ST VDDCM CMP_VT
0x4B 0x00 ATUS_FLAG[ P_INT_F – ERM_ST – – – – –
7:0] LAG ATUS
DEV_REV[7:0
0x4C 0x01 – – – – DEV_REV[3:0]
]
EFUSE_
EFUSE_ EFUSE_
EFUSE_CTR CRC_ER
0x4D 0x10 – CRC_ER CRC_ER – – – –
L[7:0] R_RST_
R_RST R_OEN
OS
EFUSE_
EFUSE_CRC
0x4E 0x00 – – – CRC_ER – – – –
_ERR[7:0]
R
CFGH_VIDEO_CRC
CFGH_VIDE
0x60 0x00 RX_CRC_EN_A_B[7:0]
O_CRC0[7:0]
CFGH_VIDE
0x61 0x00 RX_CRC_EN_C_D[7:0]
O_CRC1[7:0]
CFGI_A INFOFR
TX_CRC RX_CRC
0x70 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL[1:0] RSVD[1:0]
_EN _EN
0x71 0xB0 TR1[7:0] BW_MULT[1:0] BW_VAL[5:0]
0x72 0x00 TR2[7:0] – – – – – TX_SRC_ID[2:0]
0x73 0xFF TR3[7:0] RX_SRC_SEL[7:0]
CFGI_B INFOFR
TX_CRC RX_CRC
0x74 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_B[1:0] RSVD[1:0]
_EN_B _EN_B
0x75 0xB0 TR1[7:0] BW_MULT_B[1:0] BW_VAL_B[5:0]
0x76 0x00 TR2[7:0] – – – – – TX_SRC_ID_B[2:0]
0x77 0xFF TR3[7:0] RX_SRC_SEL_B[7:0]
CFGI_C INFOFR
TX_CRC RX_CRC
0x78 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_C[1:0] RSVD[1:0]
_EN_C _EN_C
0x79 0xB0 TR1[7:0] BW_MULT_C[1:0] BW_VAL_C[5:0]
0x7A 0x00 TR2[7:0] – – – – – TX_SRC_ID_C[2:0]
0x7B 0xFF TR3[7:0] RX_SRC_SEL_C[7:0]
CFGI_D INFOFR
TX_CRC RX_CRC
0x7C 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_D[1:0] RSVD[1:0]
_EN_D _EN_D


0x7D 0xB0 TR1[7:0] BW_MULT_D[1:0] BW_VAL_D[5:0]
0x7E 0x00 TR2[7:0] – – – – – TX_SRC_ID_D[2:0]
0x7F 0xFF TR3[7:0] RX_SRC_SEL_D[7:0]
CFGL_A GPIO
TX_CRC RX_CRC
0xA0 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL[1:0] RSVD[1:0]
_EN _EN
0xA1 0xB0 TR1[7:0] BW_MULT[1:0] BW_VAL[5:0]
0xA3 0x00 TR3[7:0] – – – – – TX_SRC_ID[2:0]
0xA4 0xFF TR4[7:0] RX_SRC_SEL[7:0]
MAX_RT
RT_CNT
0xA6 0x72 ARQ1[7:0] – MAX_RT[2:0] RSVD RSVD _ERR_O
_OEN
EN
MAX_RT
0xA7 0x00 ARQ2[7:0] RT_CNT[6:0]
_ERR
CFGL_B GPIO
TX_CRC RX_CRC
0xA8 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_B[1:0] RSVD[1:0]
_EN_B _EN_B
0xA9 0xB0 TR1[7:0] BW_MULT_B[1:0] BW_VAL_B[5:0]
0xAB 0x00 TR3[7:0] – – – – – TX_SRC_ID_B[2:0]
0xAC 0xFF TR4[7:0] RX_SRC_SEL_B[7:0]
MAX_RT
RT_CNT
0xAE 0x72 ARQ1[7:0] – MAX_RT_B[2:0] RSVD RSVD _ERR_O
_OEN_B
EN_B
MAX_RT
0xAF 0x00 ARQ2[7:0] RT_CNT_B[6:0]
_ERR_B
CFGL_C GPIO
TX_CRC RX_CRC
0xB0 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_C[1:0] RSVD[1:0]
_EN_C _EN_C
0xB1 0xB0 TR1[7:0] BW_MULT_C[1:0] BW_VAL_C[5:0]
0xB3 0x00 TR3[7:0] – – – – – TX_SRC_ID_C[2:0]
0xB4 0xFF TR4[7:0] RX_SRC_SEL_C[7:0]
MAX_RT
RT_CNT
0xB6 0x72 ARQ1[7:0] – MAX_RT_C[2:0] RSVD RSVD _ERR_O
_OEN_C
EN_C
MAX_RT
0xB7 0x00 ARQ2[7:0] RT_CNT_C[6:0]
_ERR_C
CFGL_D GPIO
TX_CRC RX_CRC
0xB8 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_D[1:0] RSVD[1:0]
_EN_D _EN_D
0xB9 0xB0 TR1[7:0] BW_MULT_D[1:0] BW_VAL_D[5:0]
0xBB 0x00 TR3[7:0] – – – – – TX_SRC_ID_D[2:0]
0xBC 0xFF TR4[7:0] RX_SRC_SEL_D[7:0]
MAX_RT
RT_CNT
0xBE 0x72 ARQ1[7:0] – MAX_RT_D[2:0] RSVD RSVD _ERR_O
_OEN_D
EN_D
MAX_RT
0xBF 0x00 ARQ2[7:0] RT_CNT_D[6:0]
_ERR_D


CC
I2C_RE I2C_RE
GSLV_1 GSLV_0
0xC7 0x66 I2C_7[7:0] I2C_INTREG_SLV_1_TO[2:0] I2C_INTREG_SLV_0_TO[2:0]
_TIMED _TIMED
_OUT _OUT
LINE_FAULT
0xE0 0x00 REG0[7:0] – – – – PU_LF3 PU_LF2 PU_LF1 PU_LF0
0xE1 0x22 REG1[7:0] – LF_1[2:0] – LF_0[2:0]
0xE2 0x22 REG2[7:0] – LF_3[2:0] – LF_2[2:0]
0xE5 0x00 REG5[7:0] – – – – LFLT_INT_FLAG[3:0]
MASK_L MASK_L MASK_L MASK_L
0xE6 0x00 REG6[7:0] – – – –
F3 F2 F1 F0
VIDEO_PIPE_SEL
VIDEO_PIPE
0xF0 0x62 VIDEO_PIPE_SEL_1[3:0] VIDEO_PIPE_SEL_0[3:0]
_SEL_0[7:0]
VIDEO_PIPE
0xF1 0xEA VIDEO_PIPE_SEL_3[3:0] VIDEO_PIPE_SEL_2[3:0]
_SEL_1[7:0]
STREAM
VIDEO_PIPE
0xF4 0x1F – – – _SEL_A VIDEO_PIPE_EN[3:0]
_EN[7:0]
LL
HVD_GPIO_CTRL
HVD_GPIO_
0xFA 0x00 CTRL_EN[7:0 – – – – HVD_OUT_EN[3:0]
]
HVD_GPIO_
0xFB 0x00 CTRL_HS[7:0 HVD_HS_SEL3[1:0] HVD_HS_SEL2[1:0] HVD_HS_SEL1[1:0] HVD_HS_SEL0[1:0]
]
HVD_GPIO_
0xFC 0x00 CTRL_VS[7:0 HVD_VS_SEL3[1:0] HVD_VS_SEL2[1:0] HVD_VS_SEL1[1:0] HVD_VS_SEL0[1:0]
]
HVD_GPIO_
0xFD 0x00 CTRL_DE[7:0 HVD_DE_SEL3[1:0] HVD_DE_SEL2[1:0] HVD_DE_SEL1[1:0] HVD_DE_SEL0[1:0]
]
HVD_GPIO_
HVD_OUT_SEL3[1: HVD_OUT_SEL2[1: HVD_OUT_SEL1[1: HVD_OUT_SEL0[1:
0xFE 0x00 CTRL_SEL[7:
0] 0] 0] 0]
0]
HVD_GPIO_
0xFF 0x00 HVD_ST_SEL3[1:0] HVD_ST_SEL2[1:0] HVD_ST_SEL1[1:0] HVD_ST_SEL0[1:0]
CTRL_ST[7:0]
VID_RX 0
VIDEO_RX0[ LCRC_E SEQ_MI LINE_C DIS_PKT
0x100 0x32 RSVD RSVD RSVD RSVD
7:0] RR SS_EN RC_EN _DET
VID_SE
VIDEO_RX6[ LIM_HE
0x106 0x12 RSVD[2:0] Q_ERR_ – RSVD RSVD
7:0] ART
OEN
VIDEO_RX8[ VID_LO VID_PKT VID_SE
0x108 0x02 RSVD RSVD[3:0]
7:0] CK _DET Q_ERR
VID_RX 1


VID_SE
VIDEO_RX6[ LIM_HE
0x118 0x12 RSVD[2:0] Q_ERR_ – RSVD RSVD
7:0] ART
OEN
0x11A 0x02 RSVD RSVD[3:0]
7:0] CK _DET Q_ERR
VID_RX 2
VID_SE
VIDEO_RX6[ LIM_HE
0x12A 0x12 RSVD[2:0] Q_ERR_ – RSVD RSVD
7:0] ART
OEN
0x12C 0x02 RSVD RSVD[3:0]
7:0] CK _DET Q_ERR
VID_RX 3
VID_SE
VIDEO_RX6[ LIM_HE
0x13C 0x12 RSVD[2:0] Q_ERR_ – RSVD RSVD
7:0] ART
OEN
0x13E 0x02 RSVD RSVD[3:0]
7:0] CK _DET Q_ERR
VID_RX_PKT_DET
LIM_HEART_
0x160 0x0A TIMEOUT_0[ – LIM_HEART_TIMEOUT_0[6:0]
7:0]
LIM_HEART_
7:0]
LIM_HEART_
7:0]
LIM_HEART_
7:0]
VRX__0 0
CROSS_HS[7 CROSS_ CROSS_
0x1D8 0x18 – CROSS_HS[4:0]
:0] HS_I HS_F
CROSS_VS[7 CROSS_ CROSS_
0x1D9 0x19 – CROSS_VS[4:0]
:0] VS_I VS_F
CROSS_DE[7 CROSS_ CROSS_
0x1DA 0x1A – CROSS_DE[4:0]
:0] DE_I DE_F
PRBS_ERR[7
0x1DB 0x00 VPRBS_ERR[7:0]
:0]
PATGEN VPRBS2 VPRBS7 VPRBS9 DIS_GLI
VPRBS_ VPRBS_ VIDEO_
0x1DC 0x80 VPRBS[7:0] _CLK_S 4_GENC _GENCH _GENCH TCH_FIL
CHECK FAIL LOCK
RC HK_EN K_EN K_EN T
VRX__0 1
0x1F8 0x18 – CROSS_HS[4:0]
:0] HS_I HS_F


0x1F9 0x19 – CROSS_VS[4:0]
:0] VS_I VS_F
0x1FA 0x1A – CROSS_DE[4:0]
:0] DE_I DE_F
PRBS_ERR[7
0x1FB 0x00 VPRBS_ERR[7:0]
:0]
0x1FC 0x80 VPRBS[7:0] _CLK_S 4_GENC _GENCH _GENCH TCH_FIL
CHECK FAIL LOCK
VRX__0 2
0x218 0x18 – CROSS_HS[4:0]
:0] HS_I HS_F
0x219 0x19 – CROSS_VS[4:0]
:0] VS_I VS_F
0x21A 0x1A – CROSS_DE[4:0]
:0] DE_I DE_F
PRBS_ERR[7
0x21B 0x00 VPRBS_ERR[7:0]
:0]
0x21C 0x80 VPRBS[7:0] _CLK_S 4_GENC _GENCH _GENCH TCH_FIL
CHECK FAIL LOCK
VRX__0 3
0x238 0x18 – CROSS_HS[4:0]
:0] HS_I HS_F
0x239 0x19 – CROSS_VS[4:0]
:0] VS_I VS_F
0x23A 0x1A – CROSS_DE[4:0]
:0] DE_I DE_F
PRBS_ERR[7
0x23B 0x00 VPRBS_ERR[7:0]
:0]
0x23C 0x80 VPRBS[7:0] _CLK_S 4_GENC _GENCH _GENCH TCH_FIL
CHECK FAIL LOCK
GPIO_AGGR0
POLARITY_A
0x2E0 0x00 POLARITY_A_L[7:0]
_L[7:0]
POLARITY_B
0x2E1 0x00 POLARITY_B_L[7:0]
_L[7:0]
POLARITY_C
0x2E2 0x00 POLARITY_C_L[7:0]
_L[7:0]
POLARITY_D
0x2E3 0x00 POLARITY_D_L[7:0]
_L[7:0]
POLARITY_A
0x2E4 0x00 – POLARITY_B_H[2:0] – POLARITY_A_H[2:0]
B_H[7:0]
POLARITY_C
0x2E5 0x00 – POLARITY_D_H[2:0] – POLARITY_C_H[2:0]
D_H[7:0]
ENABLE_A_L
0x2E6 0x00 ENABLE_A_L[7:0]
[7:0]
ENABLE_B_L
0x2E7 0x00 ENABLE_B_L[7:0]
[7:0]


ENABLE_C_L
0x2E8 0x00 ENABLE_C_L[7:0]
[7:0]
ENABLE_D_L
0x2E9 0x00 ENABLE_D_L[7:0]
[7:0]
ENABLE_AB_
0x2EA 0x00 – ENABLE_B_H[2:0] – ENABLE_A_H[2:0]
H[7:0]
ENABLE_CD
0x2EB 0x00 – ENABLE_D_H[2:0] – ENABLE_C_H[2:0]
_H[7:0]
READ_A_L[7:
0x2EC 0x00 READ_A_L[7:0]
0]
READ_B_L[7:
0x2ED 0x00 READ_B_L[7:0]
0]
READ_C_L[7:
0x2EE 0x00 READ_C_L[7:0]
0]
READ_D_L[7:
0x2EF 0x00 READ_D_L[7:0]
0]
READ_AB_H[
0x2F0 0x00 – READ_B_H[2:0] – READ_A_H[2:0]
7:0]
READ_CD_H[
0x2F1 0x00 – READ_D_H[2:0] – READ_C_H[2:0]
7:0]
OUTPUT OUTPUT
DESTIN READ_F
0x2F2 0x00 OUTPUT[7:0] – – – – _INVER _ENABL
ATION LAG
T E
GPIO0 0
RES_CF TX_COM GPIO_O GPIO_R GPIO_T GPIO_O
0x300 0x81 GPIO_A[7:0] RSVD GPIO_IN
G P_EN UT X_EN X_EN UT_DIS
PULL_UPDN_SEL[1 OUT_TY
0x301 0xA0 GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE
OVR_RE GPIO_R
0x302 0x40 GPIO_C[7:0] RSVD GPIO_RX_ID[4:0]
S_CFG ECVED
GPIO1 1
:0] PE
OVR_RE GPIO_R
S_CFG ECVED
GPIO2 2
:0] PE
OVR_RE GPIO_R
S_CFG ECVED
GPIO3 3
0x30A 0xA3 GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE


OVR_RE GPIO_R
0x30B 0x43 GPIO_C[7:0] RSVD GPIO_RX_ID[4:0]
S_CFG ECVED
GPIO4 4
0x30C 0x81 GPIO_A[7:0] RSVD GPIO_IN
0x30D 0xA4 GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE
OVR_RE GPIO_R
0x30E 0x44 GPIO_C[7:0] RSVD GPIO_RX_ID[4:0]
S_CFG ECVED
GPIO5 5
:0] PE
OVR_RE GPIO_R
S_CFG ECVED
GPIO6 6
0x314 0x26 GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE
OVR_RE GPIO_R
S_CFG ECVED
GPIO7 7
:0] PE
OVR_RE GPIO_R
S_CFG ECVED
GPIO8 8
0x31A 0xA8 GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE
OVR_RE GPIO_R
0x31B 0x48 GPIO_C[7:0] RSVD GPIO_RX_ID[4:0]
S_CFG ECVED
GPIO9 9
0x31C 0x81 GPIO_A[7:0] RSVD GPIO_IN
0x31D 0xA9 GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE
OVR_RE GPIO_R
0x31E 0x49 GPIO_C[7:0] RSVD GPIO_RX_ID[4:0]
S_CFG ECVED
GPIO10 10


0x321 0xAA GPIO_B[7:0] GPIO_TX_ID[4:0]
:0] PE
OVR_RE GPIO_R
0x322 0x4A GPIO_C[7:0] RSVD GPIO_RX_ID[4:0]
S_CFG ECVED
GPIO0_B 0
TX_COM GPIO_T
0x337 0x00 GPIO_B[7:0] RSVD GPIO_TX_ID_B[4:0]
P_EN_B X_EN_B
GPIO_R
GPIO_R
0x338 0x40 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_B[4:0]
X_EN_B
B
GPIO0_B 1
TX_COM GPIO_T
0x33A 0x01 GPIO_B[7:0] RSVD GPIO_TX_ID_B[4:0]
P_EN_B X_EN_B
GPIO_R
GPIO_R
0x33B 0x41 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_B[4:0]
X_EN_B
B
GPIO0_B 2
TX_COM GPIO_T
0x33D 0x02 GPIO_B[7:0] RSVD GPIO_TX_ID_B[4:0]
P_EN_B X_EN_B
GPIO_R
GPIO_R
0x33E 0x42 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_B[4:0]
X_EN_B
B
GPIO0_B 3
TX_COM GPIO_T
P_EN_B X_EN_B
GPIO_R
GPIO_R
X_EN_B
B
GPIO0_B 4
TX_COM GPIO_T
P_EN_B X_EN_B
GPIO_R
GPIO_R
X_EN_B
B
GPIO0_B 5
TX_COM GPIO_T
P_EN_B X_EN_B
GPIO_R
GPIO_R
X_EN_B
B
GPIO0_B 6
TX_COM GPIO_T
0x34A 0x06 GPIO_B[7:0] RSVD GPIO_TX_ID_B[4:0]
P_EN_B X_EN_B
GPIO_R
GPIO_R
0x34B 0x46 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_B[4:0]
X_EN_B
B
GPIO0_B 7
TX_COM GPIO_T
0x34D 0x07 GPIO_B[7:0] RSVD GPIO_TX_ID_B[4:0]
P_EN_B X_EN_B


GPIO_R
GPIO_R
0x34E 0x47 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_B[4:0]
X_EN_B
B
GPIO0_B 8
TX_COM GPIO_T
P_EN_B X_EN_B
GPIO_R
GPIO_R
X_EN_B
B
GPIO0_B 9
TX_COM GPIO_T
P_EN_B X_EN_B
GPIO_R
GPIO_R
X_EN_B
B
GPIO0_B 10
TX_COM GPIO_T
0x357 0x0A GPIO_B[7:0] RSVD GPIO_TX_ID_B[4:0]
P_EN_B X_EN_B
GPIO_R
GPIO_R
0x358 0x4A GPIO_C[7:0] – ECVED_ GPIO_RX_ID_B[4:0]
X_EN_B
B
GPIO0_C 0
TX_COM GPIO_T
0x36D 0x00 GPIO_B[7:0] RSVD GPIO_TX_ID_C[4:0]
P_EN_C X_EN_C
GPIO_R
GPIO_R
0x36E 0x40 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_C[4:0]
X_EN_C
C
GPIO0_C 1
TX_COM GPIO_T
0x371 0x01 GPIO_B[7:0] RSVD GPIO_TX_ID_C[4:0]
P_EN_C X_EN_C
GPIO_R
GPIO_R
0x372 0x41 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_C[4:0]
X_EN_C
C
GPIO0_C 2
TX_COM GPIO_T
P_EN_C X_EN_C
GPIO_R
GPIO_R
X_EN_C
C
GPIO0_C 3
TX_COM GPIO_T
P_EN_C X_EN_C
GPIO_R
GPIO_R
X_EN_C
C
GPIO0_C 4
TX_COM GPIO_T
0x37A 0x04 GPIO_B[7:0] RSVD GPIO_TX_ID_C[4:0]
P_EN_C X_EN_C


GPIO_R
GPIO_R
0x37B 0x44 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_C[4:0]
X_EN_C
C
GPIO0_C 5
TX_COM GPIO_T
0x37D 0x05 GPIO_B[7:0] RSVD GPIO_TX_ID_C[4:0]
P_EN_C X_EN_C
GPIO_R
GPIO_R
0x37E 0x45 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_C[4:0]
X_EN_C
C
GPIO0_C 6
TX_COM GPIO_T
P_EN_C X_EN_C
GPIO_R
GPIO_R
X_EN_C
C
GPIO0_C 7
TX_COM GPIO_T
P_EN_C X_EN_C
GPIO_R
GPIO_R
X_EN_C
C
GPIO0_C 8
TX_COM GPIO_T
P_EN_C X_EN_C
GPIO_R
GPIO_R
X_EN_C
C
GPIO0_C 9
TX_COM GPIO_T
0x38A 0x09 GPIO_B[7:0] RSVD GPIO_TX_ID_C[4:0]
P_EN_C X_EN_C
GPIO_R
GPIO_R
0x38B 0x49 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_C[4:0]
X_EN_C
C
GPIO0_C 10
TX_COM GPIO_T
0x38D 0x0A GPIO_B[7:0] RSVD GPIO_TX_ID_C[4:0]
P_EN_C X_EN_C
GPIO_R
GPIO_R
0x38E 0x4A GPIO_C[7:0] – ECVED_ GPIO_RX_ID_C[4:0]
X_EN_C
C
GPIO0_D 0
TX_COM GPIO_T
0x3A4 0x00 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3A5 0x40 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 1
TX_COM GPIO_T
0x3A7 0x01 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D


GPIO_R
GPIO_R
0x3A8 0x41 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 2
TX_COM GPIO_T
0x3AA 0x02 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3AB 0x42 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 3
TX_COM GPIO_T
0x3AD 0x03 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3AE 0x43 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 4
TX_COM GPIO_T
0x3B1 0x04 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
0x3B2 0x44 GPIO_C[7:0] – RSVD GPIO_RX_ID_D[4:0]
X_EN_D
GPIO0_D 5
TX_COM GPIO_T
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3B5 0x45 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 6
TX_COM GPIO_T
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3B8 0x46 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 7
TX_COM GPIO_T
0x3BA 0x07 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3BB 0x47 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 8
TX_COM GPIO_T
0x3BD 0x08 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3BE 0x48 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
GPIO0_D 9
TX_COM GPIO_T
0x3C1 0x09 GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3C2 0x49 GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D


GPIO0_D 10
TX_COM GPIO_T
0x3C4 0x0A GPIO_B[7:0] RSVD GPIO_TX_ID_D[4:0]
P_EN_D X_EN_D
GPIO_R
GPIO_R
0x3C5 0x4A GPIO_C[7:0] – ECVED_ GPIO_RX_ID_D[4:0]
X_EN_D
D
BACKTOP
BACKTOP1[7 CSIPLL3 CSIPLL2 CSIPLL1 CSIPLL0
:0] _LOCK _LOCK _LOCK _LOCK
BACKTOP2[7
0x401 0x00 VS_VC0_L[7:0]
:0]
BACKTOP3[7
0x402 0x00 VS_VC0_H[7:0]
:0]
BACKTOP4[7
0x403 0x00 VS_VC1_L[7:0]
:0]
BACKTOP5[7
0x404 0x00 VS_VC1_H[7:0]
:0]
BACKTOP6[7
0x405 0x00 VS_VC2_L[7:0]
:0]
BACKTOP7[7
0x406 0x00 VS_VC2_H[7:0]
:0]
BACKTOP8[7
0x407 0x00 VS_VC3_L[7:0]
:0]
BACKTOP9[7
0x408 0x00 VS_VC3_H[7:0]
:0]
BACKTOP10[ DE_SEL DE_SEL DE_SEL DE_SEL
7:0] 3 2 1 0
BACKTOP11[ cmd_ove cmd_ove cmd_ove cmd_ove
0x40A 0x00 LMO_3 LMO_2 LMO_1 LMO_0
7:0] rflow3 rflow2 rflow1 rflow0
BACKTOP12[ CSI_OU
0x40B 0x02 soft_bpp_0[4:0] – RSVD
7:0] T_EN
BACKTOP13[
0x40C 0x00 soft_vc_1[3:0] soft_vc_0[3:0]
7:0]
BACKTOP14[
0x40D 0x00 soft_vc_3[3:0] soft_vc_2[3:0]
7:0]
BACKTOP15[
0x40E 0x00 soft_dt_1_h[1:0] soft_dt_0[5:0]
7:0]
BACKTOP16[
0x40F 0x00 soft_dt_2_h[3:0] soft_dt_1_l[3:0]
7:0]
BACKTOP17[
0x410 0x00 soft_dt_3[5:0] soft_dt_2_l[1:0]
7:0]
BACKTOP18[
0x411 0x00 soft_bpp_2_h[2:0] soft_bpp_1[4:0]
7:0]
BACKTOP19[
0x412 0x00 – soft_bpp_3[4:0] soft_bpp_2_l[1:0]
7:0]
BACKTOP20[
0x413 0x00 phy0_csi_tx_dpll_fb_fraction_in_l[7:0]
7:0]
BACKTOP21[
0x414 0x00 bpp8dbl3 bpp8dbl2 bpp8dbl1 bpp8dbl0 phy0_csi_tx_dpll_fb_fraction_in_h[3:0]
7:0]


phy0_csi
override_ override_ _tx_dpll_
BACKTOP22[
0x415 0x2F bpp_vc_ bpp_vc_ fb_fractio phy0_csi_tx_dpll_predef_freq[4:0]
7:0]
dt_1 dt_0 n_predef
_en
BACKTOP23[
7:0]
BACKTOP24[ bpp8dbl3 bpp8dbl2 bpp8dbl1 bpp8dbl0
0x417 0x00 phy1_csi_tx_dpll_fb_fraction_in_h[3:0]
7:0] _mode _mode _mode _mode
phy1_csi
override_ override_ _tx_dpll_
BACKTOP25[
0x418 0x2F bpp_vc_ bpp_vc_ fb_fractio phy1_csi_tx_dpll_predef_freq[4:0]
7:0]
dt_3 dt_2 n_predef
_en
BACKTOP26[
7:0]
yuv_8_1 yuv_8_1 yuv_8_1 yuv_8_1
BACKTOP27[
0x41A 0x00 0_mux_ 0_mux_ 0_mux_ 0_mux_ phy2_csi_tx_dpll_fb_fraction_in_h[3:0]
7:0]
mode3 mode2 mode1 mode0
phy2_csi
_tx_dpll_
BACKTOP28[
0x41B 0x2F – – fb_fractio phy2_csi_tx_dpll_predef_freq[4:0]
7:0]
n_predef
_en
BACKTOP29[
0x41C 0x00 phy3_csi_tx_dpll_fb_fraction_in_l[7:0]
7:0]
BACKTOP30[ bpp10dbl bpp10dbl
0x41D 0x00 – – phy3_csi_tx_dpll_fb_fraction_in_h[3:0]
7:0] 3_mode 3
phy3_csi
_tx_dpll_
BACKTOP31[ bpp10dbl bpp10dbl
0x41E 0x2F fb_fractio phy3_csi_tx_dpll_predef_freq[4:0]
7:0] 2_mode 2
n_predef
_en
BACKTOP32[ bpp10dbl bpp10dbl bpp10dbl bpp10dbl bpp12dbl bpp12dbl bpp12dbl bpp12dbl
0x41F 0x00
7:0] 1_mode 1 0_mode 0 3 2 1 0
BACKTOP_1
BACKTOP1[7
0x420 0x01 ERRB_PKT_EN[3:0] – – RSVD[1:0]
:0]
BACKTOP2[7 ERRB_PKT_Insert_ ERRB_PKT_Insert_ ERRB_PKT_Insert_ ERRB_PKT_Insert_
0x421 0x55
:0] Mode_4[1:0] Mode_3[1:0] Mode_2[1:0] Mode_1[1:0]
ERRB_P ERRB_P ERRB_P ERRB_P
BACKTOP3[7 KT_EDG KT_EDG KT_EDG KT_EDG
0x422 0x00 – – – –
:0] E_SEL_ E_SEL_ E_SEL_ E_SEL_
4 3 2 1
ERRB_P
BACKTOP4[7 KT_DBL
0x423 0x12 – ERRB_PKT_DT_1[5:0]
:0] _MODE_
1
ERRB_P
BACKTOP5[7 KT_DBL
0x424 0x12 – ERRB_PKT_DT_2[5:0]
:0] _MODE_
2


ERRB_P
BACKTOP6[7 KT_DBL
0x425 0x12 – ERRB_PKT_DT_3[5:0]
:0] _MODE_
3
ERRB_P
BACKTOP7[7 KT_DBL
0x426 0x12 – ERRB_PKT_DT_4[5:0]
:0] _MODE_
4
ERRB_P
BACKTOP8[7 KT_VC_
0x427 0x0F – – ERRB_PKT_VC_OVRD_1[4:0]
:0] OVRD_E
N_1
ERRB_P
BACKTOP9[7 KT_VC_
:0] OVRD_E
N_2
ERRB_P
BACKTOP10[ KT_VC_
7:0] OVRD_E
N_3
ERRB_P
BACKTOP11[ KT_VC_
0x42A 0x0F – – ERRB_PKT_VC_OVRD_4[4:0]
7:0] OVRD_E
N_4
BACKTOP12[
0x42B 0x00 – – – ERRB_PKT_VC_1[4:0]
7:0]
BACKTOP13[
0x42C 0x00 – – – ERRB_PKT_VC_2[4:0]
7:0]
BACKTOP14[
0x42D 0x00 – – – ERRB_PKT_VC_3[4:0]
7:0]
BACKTOP15[
0x42E 0x00 – – – ERRB_PKT_VC_4[4:0]
7:0]
BACKTOP22[
0x435 0x01 – – – – n_vs_block[3:0]
7:0]
BACKTOP23[
0x436 0x00 – – – – dis_vs3 dis_vs2 dis_vs1 dis_vs0
7:0]
ERRB_P ERRB_P ERRB_P ERRB_P
BACKTOP24[ KT_WC_ KT_WC_ KT_WC_ KT_WC_
0x437 0x00 – – – –
7:0] OVRD_E OVRD_E OVRD_E OVRD_E
N_4 N_3 N_2 N_1
BACKTOP25[
0x438 0x00 ERRB_PKT_WC_1_H[7:0]
7:0]
BACKTOP26[
0x439 0x00 ERRB_PKT_WC_1_L[7:0]
7:0]
BACKTOP27[
0x43A 0x00 ERRB_PKT_WC_2_H[7:0]
7:0]
BACKTOP28[
0x43B 0x00 ERRB_PKT_WC_2_L[7:0]
7:0]
BACKTOP29[
0x43C 0x00 ERRB_PKT_WC_3_H[7:0]
7:0]
BACKTOP30[
0x43D 0x00 ERRB_PKT_WC_3_L[7:0]
7:0]


BACKTOP31[
0x43E 0x00 ERRB_PKT_WC_4_H[7:0]
7:0]
BACKTOP32[
0x43F 0x00 ERRB_PKT_WC_4_L[7:0]
7:0]
BACKTOP33[ FIFO_E FIFO_E FIFO_E FIFO_E
0x440 0x00 – – – –
7:0] MPTY_3 MPTY_2 MPTY_1 MPTY_0
TUN_HD TUN_HD TUN_HD TUN_HD TUN_HD TUN_HD
BACKTOP1_ TUN_HD TUN_HD
R_ERR_ R_CRC_ R_CRC_ R_CRC_ R_CRC_ R_ECC_
0x442 0x80 HDR_ERR[7: R_ERR_ R_ECC_
FLAG_0 ERR_3_ ERR_2_ ERR_1_ ERR_0_ ERR_FL
0] FLAG_0 FLAG_0
_OEN FLAG_0 FLAG_0 FLAG_0 FLAG_0 AG_0
0] FLAG_1 FLAG_1
0] FLAG_2 FLAG_2
0] FLAG_3 FLAG_3
BKTP3_ BKTP3_ BKTP3_ BKTP3_ BKTP3_ BKTP2_ BKTP1_ BKTP0_
BACKTOP39[
0x446 0xF0 LINE_LE LINE_LE LINE_LE LINE_LE LINE_LE LINE_LE LINE_LE LINE_LE
7:0]
N_OVRD N_OVRD N_OVRD N_OVRD N_OVRD N_OVRD N_OVRD N_OVRD
BACKTOP40[
0x447 0x07 BKTP0_LINE_LEN_H[7:0]
7:0]
BACKTOP41[
0x448 0x53 BKTP0_LINE_LEN_L[7:0]
7:0]
BACKTOP42[
0x449 0x07 BKTP1_LINE_LEN_H[7:0]
7:0]
BACKTOP43[
0x44A 0x53 BKTP1_LINE_LEN_L[7:0]
7:0]
BACKTOP44[
0x44B 0x07 BKTP2_LINE_LEN_H[7:0]
7:0]
BACKTOP45[
0x44C 0x53 BKTP2_LINE_LEN_L[7:0]
7:0]
BACKTOP46[
0x44D 0x07 BKTP3_LINE_LEN_H[7:0]
7:0]
BACKTOP47[
0x44E 0x53 BKTP3_LINE_LEN_L[7:0]
7:0]
BACKTOP48[ BKTP4_VM_TIMEO BKTP3_VM_TIMEO BKTP2_VM_TIMEO BKTP1_VM_TIMEO
0x44F 0xFF
7:0] UT_DIV[1:0] UT_DIV[1:0] UT_DIV[1:0] UT_DIV[1:0]
EMBED_ EMBED_
BACKTOP_E EMBED_LL_NUM_B EMBED_FL_NUM_B
0x450 0x00 LL_EN_ – FL_EN_ –
MBED0[7:0] KTP0[1:0] KTP0[1:0]
BKTP0 BKTP0
EMBED_ EMBED_
0x451 0x00 LL_EN_ – FL_EN_ –
MBED1[7:0] KTP1[1:0] KTP1[1:0]
BKTP1 BKTP1
EMBED_ EMBED_
0x452 0x00 LL_EN_ – FL_EN_ –
MBED2[7:0] KTP2[1:0] KTP2[1:0]
BKTP2 BKTP2


EMBED_ EMBED_
0x453 0x00 LL_EN_ – FL_EN_ –
MBED3[7:0] KTP3[1:0] KTP3[1:0]
BKTP3 BKTP3
CMD_O CMD_O CMD_O CMD_O
LMO_3_ LMO_2_ LMO_1_ LMO_0_
CMD_LMO_E VFL_3_E VFL_2_E VFL_1_E VFL_0_E
0x454 0xFF ERRB_O ERRB_O ERRB_O ERRB_O
RRB_EN[7:0] RRB_OE RRB_OE RRB_OE RRB_OE
EN EN EN EN
N N N N
CSIPLL3 CSIPLL2 CSIPLL1 CSIPLL0
CSI_DPL CSI_DPL CSI_DPL CSI_DPL
DPLL_ERRB_ _LOL_S _LOL_S _LOL_S _LOL_S
0x455 0x0F L3_ERR L2_ERR L1_ERR L0_ERR
OEN[7:0] TICKY_F TICKY_F TICKY_F TICKY_F
B_OEN B_OEN B_OEN B_OEN
LAG LAG LAG LAG
BACKTOP_O OVERRI OVERRI OVERRI OVERRI OVERRI OVERRI OVERRI OVERRI
0x456 0x00 VERRIDE_BP DE_VC_ DE_VC_ DE_VC_ DE_VC_ DE_BPP DE_BPP DE_BPP DE_BPP
P_DT[7:0] 3 2 1 0 _DT_3 _DT_2 _DT_1 _DT_0
OVERRI
BACKTOP_O
DE_VC_
0x457 0x00 VERRIDE_VC – – – – – – –
BITS_2_
[7:0]
AND_3
SRAM_L SRAM_L SRAM_L SRAM_L
SRAM_LCRC CRC_ER CRC_ER CRC_ER CRC_ER
0x458 0xF0 CRC_ER CRC_ER CRC_ER CRC_ER
_ERR[7:0] R_OEN_ R_OEN_ R_OEN_ R_OEN_
R_3 R_2 R_1 R_0
3 2 1 0
SRAM_L SRAM_L SRAM_L SRAM_L SRAM_L SRAM_L SRAM_L SRAM_L
SRAM_LCRC CRC_TU CRC_TU CRC_TU CRC_TU CRC_PI CRC_PI CRC_PI CRC_PI
0x459 0x00
_EN[7:0] N_CHK_ N_CHK_ N_CHK_ N_CHK_ XEL_CH XEL_CH XEL_CH XEL_CH
DIS_3 DIS_2 DIS_1 DIS_0 K_DIS_3 K_DIS_2 K_DIS_1 K_DIS_0
INIT_SR INIT_SR INIT_SR INIT_SR SRAM_L SRAM_L SRAM_L SRAM_L
SRAM_LCRC AM_LCR AM_LCR AM_LCR AM_LCR CRC_M CRC_M CRC_M CRC_M
0x45A 0x00
_RESET[7:0] C_ERR_ C_ERR_ C_ERR_ C_ERR_ ATCH_R ATCH_R ATCH_R ATCH_R
DIS_3 DIS_2 DIS_1 DIS_0 ESET_3 ESET_2 ESET_1 ESET_0
ERR_INJ
BKTOP_ERR CRC_ER CRC_ER CRC_ER CRC_ER
0x480 0x00 – – – –
_INJ_1[7:0] R_INJ_D R_INJ_D R_INJ_D R_INJ_D
IS_3 IS_2 IS_1 IS_0
MEM_E MEM_E MEM_E MEM_E
MEM_ERR_I RR_INJ_ RR_INJ_ RR_INJ_ RR_INJ_
0x481 0x00 – – – –
NJ_1BIT[7:0] 1BIT_BK 1BIT_BK 1BIT_BK 1BIT_BK
TP4 TP3 TP2 TP1
MEM_E MEM_E MEM_E MEM_E
MEM_ERR_I RR_INJ_ RR_INJ_ RR_INJ_ RR_INJ_
0x482 0x00 – – – –
NJ_2BIT[7:0] 2BIT_BK 2BIT_BK 2BIT_BK 2BIT_BK
TP4 TP3 TP2 TP1
MEM_E MEM_E
MEM_ERR_I RR_INJ_ RR_INJ_
0x483 0x01 NJ_WORD_L – – – – – – WORD_ WORD_
OC_EN[7:0] LOC_2_ LOC_1_
EN EN
MEM_ERR_I
0x484 0x00 NJ_WORD_L MEM_ERR_INJ_WORD_LOC_1[7:0]
OC_1[7:0]
MEM_ERR_I
0x485 0x00 NJ_WORD_L MEM_ERR_INJ_WORD_LOC_2[7:0]
OC_2[7:0]


MEM_ERR_I
0x486 0x00 NJ_PKT_NU – – – – MEM_ERR_INJ_PKT_NUM[3:0]
M[7:0]
MEM_ERR_I
0x487 0x03 NJ_BIT1_LO – – – MEM_ERR_INJ_BIT1_LOC[4:0]
C[7:0]
MEM_ERR_I
0x488 0x00 NJ_BIT2_LO – – – MEM_ERR_INJ_BIT2_LOC[4:0]
C[7:0]
FSYNC
FSYNC_
FSYNC_0[7:0 EN_VS_
0x4A0 0x0C RSVD RSVD OUT_PI FSYNC_MODE[1:0] FSYNC_METH[1:0]
] GEN
N
FSYNC_1[7:0
0x4A1 0x00 RSVD[1:0] RSVD[1:0] FSYNC_PER_DIV[3:0]
]
FSYNC_2[7:0 K_VAL_
0x4A2 0x81 MST_LINK_SEL[2:0] K_VAL[3:0]
] SIGN
FSYNC_3[7:0
0x4A3 0x00 P_VAL_L[7:0]
]
FSYNC_4[7:0 P_VAL_
0x4A4 0x00 – – P_VAL_H[4:0]
] SIGN
FSYNC_5[7:0
0x4A5 0x00 FSYNC_PERIOD_L[7:0]
]
FSYNC_6[7:0
0x4A6 0x00 FSYNC_PERIOD_M[7:0]
]
FSYNC_7[7:0
0x4A7 0x00 FSYNC_PERIOD_H[7:0]
]
FSYNC_8[7:0
0x4A8 0x00 FRM_DIFF_ERR_THR_L[7:0]
]
FSYNC_9[7:0
0x4A9 0x0F – – – FRM_DIFF_ERR_THR_H[4:0]
]
FSYNC_10[7:
0x4AA 0x00 OVLP_WINDOW_L[7:0]
0]
FSYNC_11[7: EN_FSI
0x4AB 0x00 – – OVLP_WINDOW_H[4:0]
0] N_LAST
FSYNC_15[7: FS_GPI FS_USE AUTO_F FS_LINK FS_LINK FS_LINK FS_LINK
0x4AF 0xCF –
0] O_TYPE _XTAL S_LINKS _3 _2 _1 _0
FSYNC_16[7:
0x4B0 0x00 FSYNC_ERR_CNT[7:0]
0]
FSYNC_17[7:
0x4B1 0xF0 FSYNC_TX_ID[4:0] FSYNC_ERR_THR[2:0]
0]
FSYNC_18[7:
0x4B2 0x00 CALC_FRM_LEN_L[7:0]
0]
FSYNC_19[7:
0x4B3 0x00 CALC_FRM_LEN_M[7:0]
0]
FSYNC_20[7:
0x4B4 0x00 CALC_FRM_LEN_H[7:0]
0]
FSYNC_21[7:
0x4B5 0x00 FRM_DIFF_L[7:0]
0]


FSYNC_
FSYNC_22[7: FSYNC_
0x4B6 0x00 LOSS_O FRM_DIFF_H[5:0]
0] LOCKED
F_LOCK
FSYNC_
FSYNC_23[7:
0x4B7 0x00 RSVD RSVD RST_MO – RSVD RSVD RSVD RSVD
0]
DE
CFGC_A CC_0
TX_CRC RX_CRC
0x500 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL[1:0] PRIO_CFG[1:0]
_EN _EN
0x503 0x00 TR3[7:0] – – – – – TX_SRC_ID[2:0]
MAX_RT
RT_CNT
0x506 0x72 ARQ1[7:0] – MAX_RT[2:0] RSVD RSVD _ERR_O
_OEN
EN
MAX_RT
0x507 0x00 ARQ2[7:0] RT_CNT[6:0]
_ERR
CFGC_B CC_0
TX_CRC RX_CRC
0x510 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_B[1:0] PRIO_CFG_B[1:0]
_EN_B _EN_B
0x513 0x00 TR3[7:0] – – – – – TX_SRC_ID_B[2:0]
MAX_RT
RT_CNT
0x516 0x72 ARQ1[7:0] – MAX_RT_B[2:0] RSVD RSVD _ERR_O
_OEN_B
EN_B
MAX_RT
0x517 0x00 ARQ2[7:0] RT_CNT_B[6:0]
_ERR_B
CFGC_C CC_0
TX_CRC RX_CRC
0x520 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_C[1:0] PRIO_CFG_C[1:0]
_EN_C _EN_C
0x523 0x00 TR3[7:0] – – – – – TX_SRC_ID_C[2:0]
0x524 0xFF TR4[7:0] RX_SRC_SEL_C[7:0]
MAX_RT
RT_CNT
0x526 0x72 ARQ1[7:0] – MAX_RT_C[2:0] RSVD RSVD _ERR_O
_OEN_C
EN_C
MAX_RT
0x527 0x00 ARQ2[7:0] RT_CNT_C[6:0]
_ERR_C
CFGC_D CC_0
TX_CRC RX_CRC
0x530 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_D[1:0] PRIO_CFG_D[1:0]
_EN_D _EN_D
0x531 0xB0 TR1[7:0] BW_MULT_D[1:0] BW_VAL_D[5:0]
0x533 0x00 TR3[7:0] – – – – – TX_SRC_ID_D[2:0]
0x534 0xFF TR4[7:0] RX_SRC_SEL_D[7:0]
MAX_RT
RT_CNT
0x536 0x72 ARQ1[7:0] – MAX_RT_D[2:0] RSVD RSVD _ERR_O
_OEN_D
EN_D


MAX_RT
0x537 0x00 ARQ2[7:0] RT_CNT_D[6:0]
_ERR_D
CFGC_A CC_1
TX_CRC RX_CRC
0x560 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL[1:0] PRIO_CFG[1:0]
_EN _EN
0x563 0x00 TR3[7:0] – – – – – TX_SRC_ID[2:0]
MAX_RT
RT_CNT
0x566 0x72 ARQ1[7:0] – MAX_RT[2:0] RSVD RSVD _ERR_O
_OEN
EN
MAX_RT
0x567 0x00 ARQ2[7:0] RT_CNT[6:0]
_ERR
CFGC_B CC_1
TX_CRC RX_CRC
0x570 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_B[1:0] PRIO_CFG_B[1:0]
_EN_B _EN_B
0x573 0x00 TR3[7:0] – – – – – TX_SRC_ID_B[2:0]
MAX_RT
RT_CNT
0x576 0x72 ARQ1[7:0] – MAX_RT_B[2:0] RSVD RSVD _ERR_O
_OEN_B
EN_B
MAX_RT
0x577 0x00 ARQ2[7:0] RT_CNT_B[6:0]
_ERR_B
CFGC_C CC_1
TX_CRC RX_CRC
0x580 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_C[1:0] PRIO_CFG_C[1:0]
_EN_C _EN_C
0x583 0x00 TR3[7:0] – – – – – TX_SRC_ID_C[2:0]
0x584 0xFF TR4[7:0] RX_SRC_SEL_C[7:0]
MAX_RT
RT_CNT
0x586 0x72 ARQ1[7:0] – MAX_RT_C[2:0] RSVD RSVD _ERR_O
_OEN_C
EN_C
MAX_RT
0x587 0x00 ARQ2[7:0] RT_CNT_C[6:0]
_ERR_C
CFGC_D CC_1
TX_CRC RX_CRC
0x590 0xF0 TR0[7:0] RSVD[1:0] PRIO_VAL_D[1:0] PRIO_CFG_D[1:0]
_EN_D _EN_D
0x591 0xB0 TR1[7:0] BW_MULT_D[1:0] BW_VAL_D[5:0]
0x593 0x00 TR3[7:0] – – – – – TX_SRC_ID_D[2:0]
0x594 0xFF TR4[7:0] RX_SRC_SEL_D[7:0]
MAX_RT
RT_CNT
0x596 0x72 ARQ1[7:0] – MAX_RT_D[2:0] RSVD RSVD _ERR_O
_OEN_D
EN_D
MAX_RT
0x597 0x00 ARQ2[7:0] RT_CNT_D[6:0]
_ERR_D


CC_G2P0_A
0x640 0x26 I2C_0[7:0] – RSVD SLV_SH_P0_A[1:0] – SLV_TO_P0_A[2:0]
0x641 0x56 I2C_1[7:0] RSVD MST_BT_P0_A[2:0] – MST_TO_P0_A[2:0]
0x642 0x00 I2C_2[7:0] SRC_A_P0_A[6:0] –
0x643 0x00 I2C_3[7:0] DST_A_P0_A[6:0] –
0x644 0x00 I2C_4[7:0] SRC_B_P0_A[6:0] –
0x645 0x00 I2C_5[7:0] DST_B_P0_A[6:0] –
CC_G2P0_B
0x650 0x26 I2C_0[7:0] – – SLV_SH_P0_B[1:0] – SLV_TO_P0_B[2:0]
0x651 0x56 I2C_1[7:0] RSVD MST_BT_P0_B[2:0] – MST_TO_P0_B[2:0]
0x652 0x00 I2C_2[7:0] SRC_A_P0_B[6:0] –
0x653 0x00 I2C_3[7:0] DST_A_P0_B[6:0] –
0x654 0x00 I2C_4[7:0] SRC_B_P0_B[6:0] –
0x655 0x00 I2C_5[7:0] DST_B_P0_B[6:0] –
CC_G2P0_C
0x660 0x26 I2C_0[7:0] – – SLV_SH_P0_C[1:0] – SLV_TO_P0_C[2:0]
0x661 0x56 I2C_1[7:0] RSVD MST_BT_P0_C[2:0] – MST_TO_P0_C[2:0]
0x662 0x00 I2C_2[7:0] SRC_A_P0_C[6:0] –
0x663 0x00 I2C_3[7:0] DST_A_P0_C[6:0] –
0x664 0x00 I2C_4[7:0] SRC_B_P0_C[6:0] –
0x665 0x00 I2C_5[7:0] DST_B_P0_C[6:0] –
CC_G2P0_D
0x670 0x26 I2C_0[7:0] – – SLV_SH_P0_D[1:0] – SLV_TO_P0_D[2:0]
0x671 0x56 I2C_1[7:0] RSVD MST_BT_P0_D[2:0] – MST_TO_P0_D[2:0]
0x672 0x00 I2C_2[7:0] SRC_A_P0_D[6:0] –
0x673 0x00 I2C_3[7:0] DST_A_P0_D[6:0] –
0x674 0x00 I2C_4[7:0] SRC_B_P0_D[6:0] –
0x675 0x00 I2C_5[7:0] DST_B_P0_D[6:0] –
CC_G2P1_A
I2C_HS
0x680 0x26 I2C_0[7:0] – SLV_SH_P1_A[1:0] – SLV_TO_P1_A[2:0]
M_P1
0x681 0x56 I2C_1[7:0] RSVD MST_BT_P1_A[2:0] – MST_TO_P1_A[2:0]
0x682 0x00 I2C_2[7:0] SRC_A_P1_A[6:0] –
0x683 0x00 I2C_3[7:0] DST_A_P1_A[6:0] –
0x684 0x00 I2C_4[7:0] SRC_B_P1_A[6:0] –
0x685 0x00 I2C_5[7:0] DST_B_P1_A[6:0] –
CC_G2P1_B
0x690 0x26 I2C_0[7:0] – – SLV_SH_P1_B[1:0] – SLV_TO_P1_B[2:0]
0x691 0x56 I2C_1[7:0] RSVD MST_BT_P1_B[2:0] – MST_TO_P1_B[2:0]
0x692 0x00 I2C_2[7:0] SRC_A_P1_B[6:0] –
0x693 0x00 I2C_3[7:0] DST_A_P1_B[6:0] –
0x694 0x00 I2C_4[7:0] SRC_B_P1_B[6:0] –
0x695 0x00 I2C_5[7:0] DST_B_P1_B[6:0] –


CC_G2P1_C
0x6A0 0x26 I2C_0[7:0] – – SLV_SH_P1_C[1:0] – SLV_TO_P1_C[2:0]
0x6A1 0x56 I2C_1[7:0] RSVD MST_BT_P1_C[2:0] – MST_TO_P1_C[2:0]
0x6A2 0x00 I2C_2[7:0] SRC_A_P1_C[6:0] –
0x6A3 0x00 I2C_3[7:0] DST_A_P1_C[6:0] –
0x6A4 0x00 I2C_4[7:0] SRC_B_P1_C[6:0] –
0x6A5 0x00 I2C_5[7:0] DST_B_P1_C[6:0] –
CC_G2P1_D
0x6B0 0x26 I2C_0[7:0] – – SLV_SH_P1_D[1:0] – SLV_TO_P1_D[2:0]
0x6B1 0x56 I2C_1[7:0] RSVD MST_BT_P1_D[2:0] – MST_TO_P1_D[2:0]
0x6B2 0x00 I2C_2[7:0] SRC_A_P1_D[6:0] –
0x6B3 0x00 I2C_3[7:0] DST_A_P1_D[6:0] –
0x6B4 0x00 I2C_4[7:0] SRC_B_P1_D[6:0] –
0x6B5 0x00 I2C_5[7:0] DST_B_P1_D[6:0] –
PROFILE_CTRL
PROFILE_MI
0x6E1 0x00 – – PROFILE_MIPI_SEL[5:0]
PI_SEL[7:0]
PROFILE_G
0x6EA 0x00 – PROFILE_GMSL_1[2:0] – PROFILE_GMSL_0[2:0]
MSL_1_0[7:0]
PROFILE_G
0x6EB 0x00 – PROFILE_GMSL_3[2:0] – PROFILE_GMSL_2[2:0]
MSL_3_2[7:0]
MIPI_TX_EXT 0
MIPI_TX_EXT
0x800 0x00 MAP_SRC_0_H[2:0] MAP_DST_0_H[2:0] – –
0[7:0]
MIPI_TX_EXT
1[7:0]
MIPI_TX_EXT
2[7:0]
MIPI_TX_EXT
3[7:0]
MIPI_TX_EXT
4[7:0]
MIPI_TX_EXT
5[7:0]
MIPI_TX_EXT
6[7:0]
MIPI_TX_EXT
7[7:0]
MIPI_TX_EXT
8[7:0]
MIPI_TX_EXT
9[7:0]
MIPI_TX_EXT
0x80A 0x00 MAP_SRC_10_H[2:0] MAP_DST_10_H[2:0] – –
10[7:0]
MIPI_TX_EXT
0x80B 0x00 MAP_SRC_11_H[2:0] MAP_DST_11_H[2:0] – –
11[7:0]


MIPI_TX_EXT
0x80C 0x00 MAP_SRC_12_H[2:0] MAP_DST_12_H[2:0] – –
12[7:0]
MIPI_TX_EXT
0x80D 0x00 MAP_SRC_13_H[2:0] MAP_DST_13_H[2:0] – –
13[7:0]
MIPI_TX_EXT
0x80E 0x00 MAP_SRC_14_H[2:0] MAP_DST_14_H[2:0] – –
14[7:0]
MIPI_TX_EXT
0x80F 0x00 MAP_SRC_15_H[2:0] MAP_DST_15_H[2:0] – –
15[7:0]
MIPI_TX_EXT 1
MIPI_TX_EXT
0[7:0]
MIPI_TX_EXT
1[7:0]
MIPI_TX_EXT
2[7:0]
MIPI_TX_EXT
3[7:0]
MIPI_TX_EXT
4[7:0]
MIPI_TX_EXT
5[7:0]
MIPI_TX_EXT
6[7:0]
MIPI_TX_EXT
7[7:0]
MIPI_TX_EXT
8[7:0]
MIPI_TX_EXT
9[7:0]
MIPI_TX_EXT
10[7:0]
MIPI_TX_EXT
11[7:0]
MIPI_TX_EXT
12[7:0]
MIPI_TX_EXT
13[7:0]
MIPI_TX_EXT
14[7:0]
MIPI_TX_EXT
15[7:0]
MIPI_TX_EXT 2
MIPI_TX_EXT
0[7:0]
MIPI_TX_EXT
1[7:0]
MIPI_TX_EXT
2[7:0]


MIPI_TX_EXT
3[7:0]
MIPI_TX_EXT
4[7:0]
MIPI_TX_EXT
5[7:0]
MIPI_TX_EXT
6[7:0]
MIPI_TX_EXT
7[7:0]
MIPI_TX_EXT
8[7:0]
MIPI_TX_EXT
9[7:0]
MIPI_TX_EXT
10[7:0]
MIPI_TX_EXT
11[7:0]
MIPI_TX_EXT
12[7:0]
MIPI_TX_EXT
13[7:0]
MIPI_TX_EXT
14[7:0]
MIPI_TX_EXT
15[7:0]
MIPI_TX_EXT 3
MIPI_TX_EXT
0[7:0]
MIPI_TX_EXT
1[7:0]
MIPI_TX_EXT
2[7:0]
MIPI_TX_EXT
3[7:0]
MIPI_TX_EXT
4[7:0]
MIPI_TX_EXT
5[7:0]
MIPI_TX_EXT
6[7:0]
MIPI_TX_EXT
7[7:0]
MIPI_TX_EXT
8[7:0]
MIPI_TX_EXT
9[7:0]
MIPI_TX_EXT
10[7:0]


MIPI_TX_EXT
11[7:0]
MIPI_TX_EXT
12[7:0]
MIPI_TX_EXT
13[7:0]
MIPI_TX_EXT
14[7:0]
MIPI_TX_EXT
15[7:0]
MIPI_PHY
MIPI_PHY0[7: force_csi force_clk force_clk phy_1x4 phy_1x4
0x8A0 0x04 phy_2x4 RSVD phy_4x2
0] _out_en 3_en 0_en b_22 a_22
MIPI_PHY1[7:
0x8A1 0x00 t_hs_przero[1:0] t_hs_prep[1:0] t_clk_trail[1:0] t_clk_przero[1:0]
0]
MIPI_PHY2[7:
0x8A2 0xF4 phy_Stdby_n[3:0] t_lpx[1:0] t_hs_trail[1:0]
0]
MIPI_PHY3[7:
0x8A3 0xE4 phy1_lane_map[3:0] phy0_lane_map[3:0]
0]
MIPI_PHY4[7:
0x8A4 0xE4 phy3_lane_map[3:0] phy2_lane_map[3:0]
0]
MIPI_PHY5[7:
0x8A5 0x00 t_clk_prep[1:0] phy1_pol_map[2:0] phy0_pol_map[2:0]
0]
MIPI_PHY6[7:
0x8A6 0x00 – – phy3_pol_map[2:0] phy2_pol_map[2:0]
0]
MIPI_PHY8[7:
0x8A8 0x00 t_lpxesc[2:0] RSVD RSVD RSVD RSVD RSVD
0]
MIPI_PHY9[7:
0x8A9 0x00 phy_cp0[4:0] – RSVD RSVD
0]
MIPI_PHY10[
0x8AA 0x02 phy_cp1[4:0] – RSVD RSVD
7:0]
MIPI_PHY11[
0x8AB 0x00 phy_cp_err[3:0] – – RSVD –
7:0]
MIPI_PHY13[
0x8AD 0x1F – – t_t3_prebegin[5:0]
7:0]
MIPI_PHY14[
0x8AE 0x5D – t_t3_post[4:0] t_t3_prep[1:0]
7:0]
TUN_CO
TUN_DA TUN_EC TUN_EC
NV_DAT
MIPI_PHY16[ TA_CRC C_UNC C_COR
0x8B0 0x78 – A_CRC_ – – –
7:0] _ERR_O ORR_ER R_ERR_
ERR_OE
EN R_OEN OEN
N
TUN_CO TUN_EC
TUN_DA TUN_EC
MIPI_PHY17[ NV_DAT C_UNC
0x8B1 0x00 – TA_CRC C_COR – – –
7:0] A_CRC_ ORR_ER
_ERR R_ERR
ERR R
csipll3_P csipll3_P csipll2_P csipll2_P csipll1_P csipll1_P csipll0_P csipll0_P
MIPI_PHY18[
0x8B2 0x00 LLORan LLORan LLORan LLORan LLORan LLORan LLORan LLORan
7:0]
geH geL geH geL geH geL geH geL


MIPI_PHY19[
0x8B3 0x00 LLORan LLORan LLORan LLORan LLORan LLORan LLORan LLORan
7:0]
geH_flag geL_flag geH_flag geL_flag geH_flag geL_flag geH_flag geL_flag
MIPI_PHY20[
0x8B4 0xFF LLORan LLORan LLORan LLORan LLORan LLORan LLORan LLORan
7:0]
geH_oen geL_oen geH_oen geL_oen geH_oen geL_oen geH_oen geL_oen
MIPI_PRBS_ MIPI_PRBS_EN_P1 MIPI_PRBS_EN_P1 MIPI_PRBS_EN_P0 MIPI_PRBS_EN_P0
0x8C0 0x00
0[7:0] _LN1[1:0] _LN0[1:0] _LN1[1:0] _LN0[1:0]
MIPI_PRBS_ MIPI_PRBS_EN_P3 MIPI_PRBS_EN_P3 MIPI_PRBS_EN_P2 MIPI_PRBS_EN_P2
0x8C1 0x00
1[7:0] _LN1[1:0] _LN0[1:0] _LN1[1:0] _LN0[1:0]
MIPI_CU MIPI_CU MIPI_CU MIPI_CU MIPI_CU MIPI_CU MIPI_CU MIPI_CU
MIPI_PRBS_ ST_SEE ST_SEE ST_SEE ST_SEE ST_SEE ST_SEE ST_SEE ST_SEE
0x8C2 0x00
2[7:0] D_EN_P D_EN_P D_EN_P D_EN_P D_EN_P D_EN_P D_EN_P D_EN_P
3_LN1 3_LN0 2_LN1 2_LN0 1_LN1 1_LN0 0_LN1 0_LN0
MIPI_PRBS_ MIPI_CUSTOM_SE
0x8C3 0xF2 RSVD RSVD RSVD RSVD – –
3[7:0] ED_2[1:0]
MIPI_PRBS_
0x8C4 0x78 MIPI_CUSTOM_SEED_1[7:0]
4[7:0]
MIPI_PRBS_
0x8C5 0x9A MIPI_CUSTOM_SEED_0[7:0]
5[7:0]
MIPI_PHY21[
0x8C6 0x0F Force_Video_Mask[3:0] Auto_Mask_En[3:0]
7:0]
Video_M
MIPI_PHY22[
0x8C7 0x0F ask_Latc – – – Video_Mask_Restart_En[3:0]
7:0]
h_Reset
MIPI_PHY24[
0x8C9 0x00 – – – – RST_MIPITX_LOC[3:0]
7:0]
MIPI_CTRL_ MIPI_CTRL_SEL_3[ MIPI_CTRL_SEL_2[ MIPI_CTRL_SEL_1[ MIPI_CTRL_SEL_0[
0x8CA 0xE4
SEL[7:0] 1:0] 1:0] 1:0] 1:0]
MIPI_PHY25[
0x8D0 0x00 csi2_tx1_pkt_cnt[3:0] csi2_tx0_pkt_cnt[3:0]
7:0]
MIPI_PHY26[
0x8D1 0x00 csi2_tx3_pkt_cnt[3:0] csi2_tx2_pkt_cnt[3:0]
7:0]
MIPI_PHY27[
0x8D2 0x00 phy1_pkt_cnt[3:0] phy0_pkt_cnt[3:0]
7:0]
MIPI_PHY28[
0x8D3 0x00 phy3_pkt_cnt[3:0] phy2_pkt_cnt[3:0]
7:0]
MIPI_PHY_C PHY_CP PHY_CP PHY_CP PHY_CP
0x8D4 0xF0 P_ERR_OE[7 1_UF_E 1_OV_E 0_UF_E 0_OV_E – – – –
:0] RR_OEN RR_OEN RR_OEN RR_OEN
DESKE DESKE DESKE DESKE
W_STAR W_STAR W_STAR W_STAR
MIPI_PHY_FL
0x8D5 0x00 – – – – T_OVER T_OVER T_OVER T_OVER
AGS[7:0]
LAP_FL LAP_FL LAP_FL LAP_FL
AG_3 AG_2 AG_1 AG_0
DESKE DESKE DESKE DESKE
W_STAR W_STAR W_STAR W_STAR
MIPI_PHY_O
0x8D6 0x0F – – – – T_OVER T_OVER T_OVER T_OVER
EN[7:0]
LAP_OE LAP_OE LAP_OE LAP_OE
N_3 N_2 N_1 N_0
MIPI_ERR_P ERR_PK
0x8D8 0x3E – ERR_PKT_DT_0[5:0]
KT_0[7:0] T_EN_0


MIPI_ERR_P ERR_PK
0x8D9 0x3E – ERR_PKT_DT_1[5:0]
KT_1[7:0] T_EN_1
MIPI_ERR_P ERR_PK
0x8DA 0x3E – ERR_PKT_DT_2[5:0]
KT_2[7:0] T_EN_2
MIPI_ERR_P ERR_PK
0x8DB 0x3E – ERR_PKT_DT_3[5:0]
KT_3[7:0] T_EN_3
ERR_PK
MIPI_ERR_P T_VC_O
0x8DC 0x0F – – ERR_PKT_VC_OVRD_0[4:0]
KT_4[7:0] VRD_EN
_0
ERR_PK
MIPI_ERR_P T_VC_O
0x8DD 0x0F – – ERR_PKT_VC_OVRD_1[4:0]
KT_5[7:0] VRD_EN
_1
ERR_PK
MIPI_ERR_P T_VC_O
0x8DE 0x0F – – ERR_PKT_VC_OVRD_2[4:0]
KT_6[7:0] VRD_EN
_2
ERR_PK
MIPI_ERR_P T_VC_O
0x8E0 0x0F – – ERR_PKT_VC_OVRD_3[4:0]
KT_7[7:0] VRD_EN
_3
MIPI_ERR_P
0x8E1 0x00 – – – ERR_PKT_VC_0[4:0]
KT_8[7:0]
MIPI_ERR_P
0x8E2 0x00 – – – ERR_PKT_VC_1[4:0]
KT_9[7:0]
MIPI_ERR_P
0x8E3 0x00 – – – ERR_PKT_VC_2[4:0]
KT_10[7:0]
MIPI_ERR_P
0x8E4 0x00 – – – ERR_PKT_VC_3[4:0]
KT_11[7:0]
ERR_PK ERR_PK ERR_PK ERR_PK
MIPI_ERR_P T_WC_O T_WC_O T_WC_O T_WC_O
0x8E5 0x00 – – – –
KT_12[7:0] VRD_EN VRD_EN VRD_EN VRD_EN
_3 _2 _1 _0
MIPI_ERR_P
0x8E6 0x00 ERR_PKT_WC_0_H[7:0]
KT_13[7:0]
MIPI_ERR_P
0x8E7 0x00 ERR_PKT_WC_0_L[7:0]
KT_14[7:0]
MIPI_ERR_P
0x8E8 0x00 ERR_PKT_WC_1_H[7:0]
KT_15[7:0]
MIPI_ERR_P
0x8E9 0x00 ERR_PKT_WC_1_L[7:0]
KT_16[7:0]
MIPI_ERR_P
0x8EA 0x00 ERR_PKT_WC_2_H[7:0]
KT_17[7:0]
MIPI_ERR_P
0x8EB 0x00 ERR_PKT_WC_2_L[7:0]
KT_18[7:0]
MIPI_ERR_P
0x8EC 0x00 ERR_PKT_WC_3_H[7:0]
KT_19[7:0]
MIPI_ERR_P
0x8ED 0x00 ERR_PKT_WC_3_L[7:0]
KT_20[7:0]


MIPI_TX 0
0x901 0x00 MIPI_TX1[7:0] MODE[7:0]
0x902 0x00 MIPI_TX2[7:0] STATUS[7:0]
0x903 0x87 MIPI_TX3[7:0] DESKEW_INIT[7:0]
0x904 0x81 MIPI_TX4[7:0] DESKEW_PER[7:0]
0x905 0x71 MIPI_TX5[7:0] CSI2_T_PRE[7:0]
0x906 0x19 MIPI_TX6[7:0] CSI2_T_POST[7:0]
0x907 0x1C MIPI_TX7[7:0] CSI2_TX_GAP[7:0]
0x908 0x00 MIPI_TX8[7:0] CSI2_TWAKEUP_L[7:0]
0x909 0x01 MIPI_TX9[7:0] CSI2_TWAKEUP_M[7:0]
MIPI_TX10[7: CSI2_LANE_CNT[1: CSI2_CP csi2_vcx
0x90A 0xD0 – CSI2_TWAKEUP_H[2:0]
0] 0] HY_EN _en
MIPI_TX11[7:
0x90B 0x00 MAP_EN_L[7:0]
0]
MIPI_TX12[7:
0x90C 0x00 MAP_EN_H[7:0]
0]
MIPI_TX13[7:
0x90D 0x00 MAP_SRC_0[7:0]
0]
MIPI_TX14[7:
0x90E 0x00 MAP_DST_0[7:0]
0]
MIPI_TX15[7:
0x90F 0x00 MAP_SRC_1[7:0]
0]
MIPI_TX16[7:
0x910 0x00 MAP_DST_1[7:0]
0]
MIPI_TX17[7:
0x911 0x00 MAP_SRC_2[7:0]
0]
MIPI_TX18[7:
0x912 0x00 MAP_DST_2[7:0]
0]
MIPI_TX19[7:
0x913 0x00 MAP_SRC_3[7:0]
0]
MIPI_TX20[7:
0x914 0x00 MAP_DST_3[7:0]
0]
MIPI_TX21[7:
0x915 0x00 MAP_SRC_4[7:0]
0]
MIPI_TX22[7:
0x916 0x00 MAP_DST_4[7:0]
0]
MIPI_TX23[7:
0x917 0x00 MAP_SRC_5[7:0]
0]
MIPI_TX24[7:
0x918 0x00 MAP_DST_5[7:0]
0]
MIPI_TX25[7:
0x919 0x00 MAP_SRC_6[7:0]
0]
MIPI_TX26[7:
0x91A 0x00 MAP_DST_6[7:0]
0]
MIPI_TX27[7:
0x91B 0x00 MAP_SRC_7[7:0]
0]
MIPI_TX28[7:
0x91C 0x00 MAP_DST_7[7:0]
0]


MIPI_TX29[7:
0x91D 0x00 MAP_SRC_8[7:0]
0]
MIPI_TX30[7:
0x91E 0x00 MAP_DST_8[7:0]
0]
MIPI_TX31[7:
0x91F 0x00 MAP_SRC_9[7:0]
0]
MIPI_TX32[7:
0x920 0x00 MAP_DST_9[7:0]
0]
MIPI_TX33[7:
0x921 0x00 MAP_SRC_10[7:0]
0]
MIPI_TX34[7:
0x922 0x00 MAP_DST_10[7:0]
0]
MIPI_TX35[7:
0x923 0x00 MAP_SRC_11[7:0]
0]
MIPI_TX36[7:
0x924 0x00 MAP_DST_11[7:0]
0]
MIPI_TX37[7:
0x925 0x00 MAP_SRC_12[7:0]
0]
MIPI_TX38[7:
0x926 0x00 MAP_DST_12[7:0]
0]
MIPI_TX39[7:
0x927 0x00 MAP_SRC_13[7:0]
0]
MIPI_TX40[7:
0x928 0x00 MAP_DST_13[7:0]
0]
MIPI_TX41[7:
0x929 0x00 MAP_SRC_14[7:0]
0]
MIPI_TX42[7:
0x92A 0x00 MAP_DST_14[7:0]
0]
MIPI_TX43[7:
0x92B 0x00 MAP_SRC_15[7:0]
0]
MIPI_TX44[7:
0x92C 0x00 MAP_DST_15[7:0]
0]
MIPI_TX45[7: MAP_DPHY_DEST_ MAP_DPHY_DEST_ MAP_DPHY_DEST_ MAP_DPHY_DEST_
0x92D 0x00
0] 3[1:0] 2[1:0] 1[1:0] 0[1:0]
0x92E 0x00
0] 7[1:0] 6[1:0] 5[1:0] 4[1:0]
0x92F 0x00
0] 11[1:0] 10[1:0] 9[1:0] 8[1:0]
0x930 0x00
0] 15[1:0] 14[1:0] 13[1:0] 12[1:0]
MIPI_TX49[7:
0x931 0x00 MAP_CON[7:0]
0]
MIPI_TX50[7:
0x932 0x00 SKEW_PER_SEL[7:0]
0]
ALT2_M ALT_ME ALT_ME
MIPI_TX51[7: MODE_ ALT_ME
0x933 0x00 – – – EM_MA M_MAP1 M_MAP1
0] DT M_MAP8
P8 0 2
MIPI_TX52[7:
0x934 0x00 video_masked_latched[3:0] video_masked[3:0]
0]


MIPI_TX54[7: TUN_NO TUN_SER_LANE_N DESKEW_TUN_SR
0x936 0x08 DESKEW_TUN[1:0] TUN_EN
0] _CORR UM[1:0] C[1:0]
MIPI_TX56[7:
0x938 0x00 PKT_START_ADDR[7:0]
0]
TUN_DP
DIS_AU TUN_DP
DIS_AU HY_TO_
MIPI_TX57[7: TO_SER HY_TO_
0x939 0x10 TO_TUN TUN_DEST[1:0] – CPHY_C RSVD
0] _LANE_ CPHY_C
_DET ONV_OV
DET ONV
RD
DCPHY_
MIPI_ERR_IN CONV_E
0x93A 0x00 – – DCPHY_CONV_ERR_INJ_B1_SITE[4:0]
J_B1[7:0] RR_INJ_
B1_EN
DCPHY_
MIPI_ERR_IN CONV_E
0x93B 0x00 – – DCPHY_CONV_ERR_INJ_B2_SITE[4:0]
J_B2[7:0] RR_INJ_
B2_EN
DESKE DESKE DESKE
MIPI_ERRB_ W_BEF W_AFTE W_BEF
0x93C 0x00 DESKEW_OR – – – – ORE_ER R_ERRB ORE_VS –
DER[7:0] RB_PKT _PKT_M _PKT_M
_MODE ODE ODE
MIPI_TX 1
0x941 0x00 MIPI_TX1[7:0] MODE[7:0]
0x942 0x00 MIPI_TX2[7:0] STATUS[7:0]
0] 0] HY_EN _en
MIPI_TX11[7:
0x94B 0x00 MAP_EN_L[7:0]
0]
MIPI_TX12[7:
0x94C 0x00 MAP_EN_H[7:0]
0]
MIPI_TX13[7:
0x94D 0x00 MAP_SRC_0[7:0]
0]
MIPI_TX14[7:
0x94E 0x00 MAP_DST_0[7:0]
0]
MIPI_TX15[7:
0x94F 0x00 MAP_SRC_1[7:0]
0]
MIPI_TX16[7:
0x950 0x00 MAP_DST_1[7:0]
0]
MIPI_TX17[7:
0x951 0x00 MAP_SRC_2[7:0]
0]
MIPI_TX18[7:
0x952 0x00 MAP_DST_2[7:0]
0]


MIPI_TX19[7:
0x953 0x00 MAP_SRC_3[7:0]
0]
MIPI_TX20[7:
0x954 0x00 MAP_DST_3[7:0]
0]
MIPI_TX21[7:
0x955 0x00 MAP_SRC_4[7:0]
0]
MIPI_TX22[7:
0x956 0x00 MAP_DST_4[7:0]
0]
MIPI_TX23[7:
0x957 0x00 MAP_SRC_5[7:0]
0]
MIPI_TX24[7:
0x958 0x00 MAP_DST_5[7:0]
0]
MIPI_TX25[7:
0x959 0x00 MAP_SRC_6[7:0]
0]
MIPI_TX26[7:
0x95A 0x00 MAP_DST_6[7:0]
0]
MIPI_TX27[7:
0x95B 0x00 MAP_SRC_7[7:0]
0]
MIPI_TX28[7:
0x95C 0x00 MAP_DST_7[7:0]
0]
MIPI_TX29[7:
0x95D 0x00 MAP_SRC_8[7:0]
0]
MIPI_TX30[7:
0x95E 0x00 MAP_DST_8[7:0]
0]
MIPI_TX31[7:
0x95F 0x00 MAP_SRC_9[7:0]
0]
MIPI_TX32[7:
0x960 0x00 MAP_DST_9[7:0]
0]
MIPI_TX33[7:
0x961 0x00 MAP_SRC_10[7:0]
0]
MIPI_TX34[7:
0x962 0x00 MAP_DST_10[7:0]
0]
MIPI_TX35[7:
0x963 0x00 MAP_SRC_11[7:0]
0]
MIPI_TX36[7:
0x964 0x00 MAP_DST_11[7:0]
0]
MIPI_TX37[7:
0x965 0x00 MAP_SRC_12[7:0]
0]
MIPI_TX38[7:
0x966 0x00 MAP_DST_12[7:0]
0]
MIPI_TX39[7:
0x967 0x00 MAP_SRC_13[7:0]
0]
MIPI_TX40[7:
0x968 0x00 MAP_DST_13[7:0]
0]
MIPI_TX41[7:
0x969 0x00 MAP_SRC_14[7:0]
0]
MIPI_TX42[7:
0x96A 0x00 MAP_DST_14[7:0]
0]
MIPI_TX43[7:
0x96B 0x00 MAP_SRC_15[7:0]
0]


MIPI_TX44[7:
0x96C 0x00 MAP_DST_15[7:0]
0]
0x96D 0x00
0] 3[1:0] 2[1:0] 1[1:0] 0[1:0]
0x96E 0x00
0] 7[1:0] 6[1:0] 5[1:0] 4[1:0]
0x96F 0x00
0] 11[1:0] 10[1:0] 9[1:0] 8[1:0]
0x970 0x00
0] 15[1:0] 14[1:0] 13[1:0] 12[1:0]
MIPI_TX49[7:
0x971 0x00 MAP_CON[7:0]
0]
MIPI_TX50[7:
0x972 0x00 SKEW_PER_SEL[7:0]
0]
0x973 0x00 – – – EM_MA M_MAP1 M_MAP1
0] DT M_MAP8
P8 0 2
MIPI_TX52[7:
0x974 0x00 video_masked_latched[3:0] video_masked[3:0]
0]
0x976 0x08 DESKEW_TUN[1:0] TUN_EN
0] _CORR UM[1:0] C[1:0]
MIPI_TX56[7:
0x978 0x00 PKT_START_ADDR[7:0]
0]
TUN_DP
DIS_AU TUN_DP
DIS_AU HY_TO_
0x979 0x10 TO_TUN TUN_DEST[1:0] – CPHY_C RSVD
0] _LANE_ CPHY_C
_DET ONV_OV
DET ONV
RD
DCPHY_
MIPI_ERR_IN CONV_E
0x97A 0x00 – – DCPHY_CONV_ERR_INJ_B1_SITE[4:0]
J_B1[7:0] RR_INJ_
B1_EN
DCPHY_
MIPI_ERR_IN CONV_E
0x97B 0x00 – – DCPHY_CONV_ERR_INJ_B2_SITE[4:0]
J_B2[7:0] RR_INJ_
B2_EN
DESKE DESKE DESKE
MIPI_ERRB_ W_BEF W_AFTE W_BEF
0x97C 0x00 DESKEW_OR – – – – ORE_ER R_ERRB ORE_VS –
_MODE ODE ODE
MIPI_TX 2
0x981 0x00 MIPI_TX1[7:0] MODE[7:0]
0x982 0x00 MIPI_TX2[7:0] STATUS[7:0]


0] 0] HY_EN _en
MIPI_TX11[7:
0x98B 0x00 MAP_EN_L[7:0]
0]
MIPI_TX12[7:
0x98C 0x00 MAP_EN_H[7:0]
0]
MIPI_TX13[7:
0x98D 0x00 MAP_SRC_0[7:0]
0]
MIPI_TX14[7:
0x98E 0x00 MAP_DST_0[7:0]
0]
MIPI_TX15[7:
0x98F 0x00 MAP_SRC_1[7:0]
0]
MIPI_TX16[7:
0x990 0x00 MAP_DST_1[7:0]
0]
MIPI_TX17[7:
0x991 0x00 MAP_SRC_2[7:0]
0]
MIPI_TX18[7:
0x992 0x00 MAP_DST_2[7:0]
0]
MIPI_TX19[7:
0x993 0x00 MAP_SRC_3[7:0]
0]
MIPI_TX20[7:
0x994 0x00 MAP_DST_3[7:0]
0]
MIPI_TX21[7:
0x995 0x00 MAP_SRC_4[7:0]
0]
MIPI_TX22[7:
0x996 0x00 MAP_DST_4[7:0]
0]
MIPI_TX23[7:
0x997 0x00 MAP_SRC_5[7:0]
0]
MIPI_TX24[7:
0x998 0x00 MAP_DST_5[7:0]
0]
MIPI_TX25[7:
0x999 0x00 MAP_SRC_6[7:0]
0]
MIPI_TX26[7:
0x99A 0x00 MAP_DST_6[7:0]
0]
MIPI_TX27[7:
0x99B 0x00 MAP_SRC_7[7:0]
0]
MIPI_TX28[7:
0x99C 0x00 MAP_DST_7[7:0]
0]
MIPI_TX29[7:
0x99D 0x00 MAP_SRC_8[7:0]
0]
MIPI_TX30[7:
0x99E 0x00 MAP_DST_8[7:0]
0]
MIPI_TX31[7:
0x99F 0x00 MAP_SRC_9[7:0]
0]
MIPI_TX32[7:
0x9A0 0x00 MAP_DST_9[7:0]
0]
MIPI_TX33[7:
0x9A1 0x00 MAP_SRC_10[7:0]
0]


MIPI_TX34[7:
0x9A2 0x00 MAP_DST_10[7:0]
0]
MIPI_TX35[7:
0x9A3 0x00 MAP_SRC_11[7:0]
0]
MIPI_TX36[7:
0x9A4 0x00 MAP_DST_11[7:0]
0]
MIPI_TX37[7:
0x9A5 0x00 MAP_SRC_12[7:0]
0]
MIPI_TX38[7:
0x9A6 0x00 MAP_DST_12[7:0]
0]
MIPI_TX39[7:
0x9A7 0x00 MAP_SRC_13[7:0]
0]
MIPI_TX40[7:
0x9A8 0x00 MAP_DST_13[7:0]
0]
MIPI_TX41[7:
0x9A9 0x00 MAP_SRC_14[7:0]
0]
MIPI_TX42[7:
0x9AA 0x00 MAP_DST_14[7:0]
0]
MIPI_TX43[7:
0x9AB 0x00 MAP_SRC_15[7:0]
0]
MIPI_TX44[7:
0x9AC 0x00 MAP_DST_15[7:0]
0]
0x9AD 0x00
0] 3[1:0] 2[1:0] 1[1:0] 0[1:0]
0x9AE 0x00
0] 7[1:0] 6[1:0] 5[1:0] 4[1:0]
0x9AF 0x00
0] 11[1:0] 10[1:0] 9[1:0] 8[1:0]
0x9B0 0x00
0] 15[1:0] 14[1:0] 13[1:0] 12[1:0]
MIPI_TX49[7:
0x9B1 0x00 MAP_CON[7:0]
0]
MIPI_TX50[7:
0x9B2 0x00 SKEW_PER_SEL[7:0]
0]
0x9B3 0x00 – – – EM_MA M_MAP1 M_MAP1
0] DT M_MAP8
P8 0 2
MIPI_TX52[7:
0x9B4 0x00 video_masked_latched[3:0] video_masked[3:0]
0]
0x9B6 0x08 DESKEW_TUN[1:0] TUN_EN
0] _CORR UM[1:0] C[1:0]
MIPI_TX56[7:
0x9B8 0x00 PKT_START_ADDR[7:0]
0]
TUN_DP
DIS_AU TUN_DP
DIS_AU HY_TO_ TUN_NO
0x9B9 0x10 TO_TUN TUN_DEST[1:0] – CPHY_C _CORR_
0] _LANE_ CPHY_C
_DET ONV_OV LENGTH
DET ONV
RD


DCPHY_
MIPI_ERR_IN CONV_E
0x9BA 0x00 – – DCPHY_CONV_ERR_INJ_B1_SITE[4:0]
J_B1[7:0] RR_INJ_
B1_EN
DCPHY_
MIPI_ERR_IN CONV_E
0x9BB 0x00 – – DCPHY_CONV_ERR_INJ_B2_SITE[4:0]
J_B2[7:0] RR_INJ_
B2_EN
DESKE DESKE DESKE
MIPI_DESKE W_BEF W_AFTE W_BEF
0x9BC 0x00 W_ERRB_OR – – – – ORE_ER R_ERRB ORE_VS –
_MODE ODE ODE
MIPI_TX 3
0x9C1 0x00 MIPI_TX1[7:0] MODE[7:0]
0x9C2 0x00 MIPI_TX2[7:0] STATUS[7:0]
0x9C3 0x87 MIPI_TX3[7:0] DESKEW_INIT[7:0]
0x9C4 0x81 MIPI_TX4[7:0] DESKEW_PER[7:0]
0x9C5 0x71 MIPI_TX5[7:0] CSI2_T_PRE[7:0]
0x9C6 0x19 MIPI_TX6[7:0] CSI2_T_POST[7:0]
0x9C7 0x1C MIPI_TX7[7:0] CSI2_TX_GAP[7:0]
0x9C8 0x00 MIPI_TX8[7:0] CSI2_TWAKEUP_L[7:0]
0x9C9 0x01 MIPI_TX9[7:0] CSI2_TWAKEUP_M[7:0]
0x9CA 0xD0 – CSI2_TWAKEUP_H[2:0]
0] 0] HY_EN _en
MIPI_TX11[7:
0x9CB 0x00 MAP_EN_L[7:0]
0]
MIPI_TX12[7:
0x9CC 0x00 MAP_EN_H[7:0]
0]
MIPI_TX13[7:
0x9CD 0x00 MAP_SRC_0[7:0]
0]
MIPI_TX14[7:
0x9CE 0x00 MAP_DST_0[7:0]
0]
MIPI_TX15[7:
0x9CF 0x00 MAP_SRC_1[7:0]
0]
MIPI_TX16[7:
0x9D0 0x00 MAP_DST_1[7:0]
0]
MIPI_TX17[7:
0x9D1 0x00 MAP_SRC_2[7:0]
0]
MIPI_TX18[7:
0x9D2 0x00 MAP_DST_2[7:0]
0]
MIPI_TX19[7:
0x9D3 0x00 MAP_SRC_3[7:0]
0]
MIPI_TX20[7:
0x9D4 0x00 MAP_DST_3[7:0]
0]
MIPI_TX21[7:
0x9D5 0x00 MAP_SRC_4[7:0]
0]
MIPI_TX22[7:
0x9D6 0x00 MAP_DST_4[7:0]
0]


MIPI_TX23[7:
0x9D7 0x00 MAP_SRC_5[7:0]
0]
MIPI_TX24[7:
0x9D8 0x00 MAP_DST_5[7:0]
0]
MIPI_TX25[7:
0x9D9 0x00 MAP_SRC_6[7:0]
0]
MIPI_TX26[7:
0x9DA 0x00 MAP_DST_6[7:0]
0]
MIPI_TX27[7:
0x9DB 0x00 MAP_SRC_7[7:0]
0]
MIPI_TX28[7:
0x9DC 0x00 MAP_DST_7[7:0]
0]
MIPI_TX29[7:
0x9DD 0x00 MAP_SRC_8[7:0]
0]
MIPI_TX30[7:
0x9DE 0x00 MAP_DST_8[7:0]
0]
MIPI_TX31[7:
0x9DF 0x00 MAP_SRC_9[7:0]
0]
MIPI_TX32[7:
0x9E0 0x00 MAP_DST_9[7:0]
0]
MIPI_TX33[7:
0x9E1 0x00 MAP_SRC_10[7:0]
0]
MIPI_TX34[7:
0x9E2 0x00 MAP_DST_10[7:0]
0]
MIPI_TX35[7:
0x9E3 0x00 MAP_SRC_11[7:0]
0]
MIPI_TX36[7:
0x9E4 0x00 MAP_DST_11[7:0]
0]
MIPI_TX37[7:
0x9E5 0x00 MAP_SRC_12[7:0]
0]
MIPI_TX38[7:
0x9E6 0x00 MAP_DST_12[7:0]
0]
MIPI_TX39[7:
0x9E7 0x00 MAP_SRC_13[7:0]
0]
MIPI_TX40[7:
0x9E8 0x00 MAP_DST_13[7:0]
0]
MIPI_TX41[7:
0x9E9 0x00 MAP_SRC_14[7:0]
0]
MIPI_TX42[7:
0x9EA 0x00 MAP_DST_14[7:0]
0]
MIPI_TX43[7:
0x9EB 0x00 MAP_SRC_15[7:0]
0]
MIPI_TX44[7:
0x9EC 0x00 MAP_DST_15[7:0]
0]
0x9ED 0x00
0] 3[1:0] 2[1:0] 1[1:0] 0[1:0]
0x9EE 0x00
0] 7[1:0] 6[1:0] 5[1:0] 4[1:0]
0x9EF 0x00
0] 11[1:0] 10[1:0] 9[1:0] 8[1:0]


0x9F0 0x00
0] 15[1:0] 14[1:0] 13[1:0] 12[1:0]
MIPI_TX49[7:
0x9F1 0x00 MAP_CON[7:0]
0]
MIPI_TX50[7:
0x9F2 0x00 SKEW_PER_SEL[7:0]
0]
0x9F3 0x00 – – – EM_MA M_MAP1 M_MAP1
0] DT M_MAP8
P8 0 2
MIPI_TX52[7:
0x9F4 0x00 video_masked_latched[3:0] video_masked[3:0]
0]
0x9F6 0x08 DESKEW_TUN[1:0] TUN_EN
0] _CORR UM[1:0] C[1:0]
MIPI_TX56[7:
0x9F8 0x00 PKT_START_ADDR[7:0]
0]
TUN_DP
DIS_AU TUN_DP
DIS_AU HY_TO_ TUN_NO
0x9F9 0x10 TO_TUN TUN_DEST[1:0] – CPHY_C _CORR_
0] _LANE_ CPHY_C
_DET ONV_OV LENGTH
DET ONV
RD
DCPHY_
MIPI_ERR_IN CONV_E
0x9FA 0x00 – – DCPHY_CONV_ERR_INJ_B1_SITE[4:0]
J_B1[7:0] RR_INJ_
B1_EN
DCPHY_
MIPI_ERR_IN CONV_E
0x9FB 0x00 – – DCPHY_CONV_ERR_INJ_B2_SITE[4:0]
J_B2[7:0] RR_INJ_
B2_EN
DESKE DESKE DESKE
MIPI_DESKE W_BEF W_AFTE W_BEF
0x9FC 0x00 W_ERRB_OR – – – – ORE_ER R_ERRB ORE_VS –
_MODE ODE ODE
GMSL1 A
GMSL1_4[7:0 CC_POR REVCCE FWDCC
0xB04 0x03 – – PRBSEN – –
] T_SEL N EN
GMSL1_5[7:0 NO_RE HVTR_M
0xB05 0x39 RSVD EN_EQ EQTUNE[3:0]
] M_MST ODE
GMSL1_6[7:0 HIGHIM MAX_RT I2C_RT_ GPI_CO GPI_RT_
0xB06 0x6F HV_SRC[2:0]
] M _EN EN MP_EN EN
GMSL1_7[7:0 PXL_CR
0xB07 0x04 DBL DRS BWS – HIBW HVEN –
] C
GMSL1_8[7:0 EN_FSY PKTCC_ CC_CRC_LENGTH[
0xB08 0x21 GPI_SEL[1:0] GPI_EN –
] NC_TX EN 1:0]
HS_TRA
GMSL1_D[7:0 I2C_LOC
0xB0D 0x00 RSVD – – – CK_FSY RSVD RSVD
] _ACK
NC
GMSL1_E[7:0
0xB0E 0x00 DET_THR[7:0]
]
GMSL1_F[7:0 EN_DE_ EN_HS_ EN_VS_ PRBS_T
0xB0F 0x01 – DE_EN – –
] FILT FILT FILT YPE


GMSL1_10[7: RCEG_B RCEG_E
0xB10 0x02 RCEG_TYPE[1:0] RCEG_ERR_NUM[3:0]
0] OUND N
GMSL1_11[7: RCEG_LO_BST_PR RCEG_LO_BST_LE
0xB11 0xF0 RCEG_ERR_RATE[3:0]
0] B[1:0] N[1:0]
UNDER CC_CRC LINE_C MAX_RT RCEG_E
GMSL1_12[7: LINE_CRC_LOC[1:0
0xB12 0x52 BST_DE _ERR_E RC_EN_ – _ERR_E RR_PER
0] ]
T_EN N GMSL1 N _EN
EOM_M
EOM_PE
GMSL1_13[7: EOM_E AN_TRG
0xB13 0xC0 R_MOD EOM_MIN_THR_G1[4:0]
0] N_G1 _REQ_G
E_G1
1
AEQ_PE AEQ_MA
GMSL1_14[7:
0xB14 0x80 AEQ_EN R_MOD N_TRG_ EOM_PER_THR[4:0]
0]
E REQ
GMSL1_15[7:
0xB15 0x00 DET_ERR[7:0]
0]
GMSL1_16[7:
0xB16 0x00 PRBS_ERR[7:0]
0]
MAX_RT MAX_RT
GMSL1_17[7: PRBS_O
0xB17 0x00 RSVD _ERR_I2 GPI_IN _ERR_G – – –
0] K
C PI
GMSL1_18[7:
0xB18 0x00 CC_RETR_CNT[7:0]
0]
GMSL1_19[7:
0xB19 0x00 CC_CRC_ERRCNT[7:0]
0]
GMSL1_1A[7:
0xB1A 0x00 RCEG_ERR_CNT[7:0]
0]
GMSL1_1B[7: LINE_C
0xB1B 0x00 – – – – – – –
0] RC_ERR
GMSL1_1C[7:
0xB1C 0x00 – – EOM_EYE_WIDTH[5:0]
0]
UNDER
GMSL1_1D[7:
0xB1D 0x00 – – – BOOST_ AEQ_BST[3:0]
0]
DET
GMSL1_20[7:
0xB20 0x00 CRC_VALUE_0[7:0]
0]
GMSL1_21[7:
0]
GMSL1_22[7:
0]
GMSL1_23[7:
0]
CONV_
GMSL1_96[7: DBL_ALI
0xB96 0x3B CONV_GMSL1_DATATYPE[4:0] RSVD GMSL1_
0] GN_TO
EN
GMSL1_CB[7 LOCKED
0xBCB 0x00 RSVD RSVD RSVD RSVD RSVD RSVD RSVD
:0] _G1
GMSL1 B
0xC04 0x03 – – PRBSEN – –
] T_SEL N EN


0xC05 0x39 RSVD EN_EQ EQTUNE[3:0]
] M_MST ODE
0xC06 0x6F HV_SRC[2:0]
] M _EN EN MP_EN EN
GMSL1_7[7:0 PXL_CR
0xC07 0x04 DBL DRS BWS – HIBW HVEN –
] C
0xC08 0x21 GPI_SEL[1:0] GPI_EN –
] NC_TX EN 1:0]
HS_TRA
GMSL1_D[7:0 I2C_LOC
0xC0D 0x00 RSVD – – – CK_FSY RSVD RSVD
] _ACK
NC
GMSL1_E[7:0
0xC0E 0x00 DET_THR[7:0]
]
0xC0F 0x01 – DE_EN – –
0xC10 0x02 RCEG_TYPE[1:0] RCEG_ERR_NUM[3:0]
0] OUND N
0xC11 0xF0 RCEG_ERR_RATE[3:0]
0] B[1:0] N[1:0]
0xC12 0x52 BST_DE _ERR_E RC_EN_ – _ERR_E RR_PER
0] ]
T_EN N GMSL1 N _EN
EOM_M
EOM_PE
0xC13 0xC0 R_MOD EOM_MIN_THR_G1[4:0]
0] N_G1 _REQ_G
E_G1
1
AEQ_PE AEQ_MA
GMSL1_14[7:
0xC14 0x80 AEQ_EN R_MOD N_TRG_ EOM_PER_THR[4:0]
0]
E REQ
GMSL1_15[7:
0xC15 0x00 DET_ERR[7:0]
0]
GMSL1_16[7:
0xC16 0x00 PRBS_ERR[7:0]
0]
MAX_RT MAX_RT
GMSL1_17[7: PRBS_O
0xC17 0x00 RSVD _ERR_I2 GPI_IN _ERR_G – – –
0] K
C PI
GMSL1_18[7:
0xC18 0x00 CC_RETR_CNT[7:0]
0]
GMSL1_19[7:
0xC19 0x00 CC_CRC_ERRCNT[7:0]
0]
GMSL1_1A[7:
0xC1A 0x00 RCEG_ERR_CNT[7:0]
0]
GMSL1_1B[7: LINE_C
0xC1B 0x00 – – – – – – –
0] RC_ERR
GMSL1_1C[7:
0xC1C 0x00 – – EOM_EYE_WIDTH[5:0]
0]
UNDER
GMSL1_1D[7:
0xC1D 0x00 – – – BOOST_ AEQ_BST[3:0]
0]
DET
GMSL1_20[7:
0xC20 0x00 CRC_VALUE_0[7:0]
0]


GMSL1_21[7:
0]
GMSL1_22[7:
0]
GMSL1_23[7:
0]
CONV_
GMSL1_96[7: DBL_ALI
0xC96 0x3B CONV_GMSL1_DATATYPE[4:0] RSVD GMSL1_
0] GN_TO
EN
GMSL1_CB[7 LOCKED
0xCCB 0x00 RSVD RSVD RSVD RSVD RSVD RSVD RSVD
:0] _G1
GMSL1 C
0xD04 0x03 – – PRBSEN – –
] T_SEL N EN
0xD05 0x39 RSVD EN_EQ EQTUNE[3:0]
] M_MST ODE
0xD06 0x6F HV_SRC[2:0]
] M _EN EN MP_EN EN
GMSL1_7[7:0 PXL_CR
0xD07 0x04 DBL DRS BWS – HIBW HVEN –
] C
0xD08 0x21 GPI_SEL[1:0] GPI_EN –
] NC_TX EN 1:0]
HS_TRA
GMSL1_D[7:0 I2C_LOC
0xD0D 0x00 RSVD – – – CK_FSY RSVD RSVD
] _ACK
NC
GMSL1_E[7:0
0xD0E 0x00 DET_THR[7:0]
]
0xD0F 0x01 – DE_EN – –
0xD10 0x02 RCEG_TYPE[1:0] RCEG_ERR_NUM[3:0]
0] OUND N
0xD11 0xF0 RCEG_ERR_RATE[3:0]
0] B[1:0] N[1:0]
0xD12 0x52 BST_DE _ERR_E RC_EN_ – _ERR_E RR_PER
0] ]
T_EN N GMSL1 N _EN
EOM_M
EOM_PE
0xD13 0xC0 R_MOD EOM_MIN_THR_G1[4:0]
0] N_G1 _REQ_G
E_G1
1
AEQ_PE AEQ_MA
GMSL1_14[7:
0xD14 0x80 AEQ_EN R_MOD N_TRG_ EOM_PER_THR[4:0]
0]
E REQ
GMSL1_15[7:
0xD15 0x00 DET_ERR[7:0]
0]
GMSL1_16[7:
0xD16 0x00 PRBS_ERR[7:0]
0]
MAX_RT MAX_RT
GMSL1_17[7: PRBS_O
0xD17 0x00 RSVD _ERR_I2 GPI_IN _ERR_G – – –
0] K
C PI


GMSL1_18[7:
0xD18 0x00 CC_RETR_CNT[7:0]
0]
GMSL1_19[7:
0xD19 0x00 CC_CRC_ERRCNT[7:0]
0]
GMSL1_1A[7:
0xD1A 0x00 RCEG_ERR_CNT[7:0]
0]
GMSL1_1B[7: LINE_C
0xD1B 0x00 – – – – – – –
0] RC_ERR
GMSL1_1C[7:
0xD1C 0x00 – – EOM_EYE_WIDTH[5:0]
0]
UNDER
GMSL1_1D[7:
0xD1D 0x00 – – – BOOST_ AEQ_BST[3:0]
0]
DET
GMSL1_20[7:
0xD20 0x00 CRC_VALUE_0[7:0]
0]
GMSL1_21[7:
0]
GMSL1_22[7:
0]
GMSL1_23[7:
0]
CONV_
GMSL1_96[7: DBL_ALI
0xD96 0x3B CONV_GMSL1_DATATYPE[4:0] RSVD GMSL1_
0] GN_TO
EN
GMSL1_CB[7 LOCKED
0xDCB 0x00 RSVD RSVD RSVD RSVD RSVD RSVD RSVD
:0] _G1
GMSL1 D
0xE04 0x03 – – PRBSEN – –
] T_SEL N EN
0xE05 0x39 RSVD EN_EQ EQTUNE[3:0]
] M_MST ODE
0xE06 0x6F HV_SRC[2:0]
] M _EN EN MP_EN EN
GMSL1_7[7:0 PXL_CR
0xE07 0x04 DBL DRS BWS – HIBW HVEN –
] C
0xE08 0x21 GPI_SEL[1:0] GPI_EN –
] NC_TX EN 1:0]
HS_TRA
GMSL1_D[7:0 I2C_LOC
0xE0D 0x00 RSVD – – – CK_FSY RSVD RSVD
] _ACK
NC
GMSL1_E[7:0
0xE0E 0x00 DET_THR[7:0]
]
0xE0F 0x01 – DE_EN – –
0xE10 0x02 RCEG_TYPE[1:0] RCEG_ERR_NUM[3:0]
0] OUND N
0xE11 0xF0 RCEG_ERR_RATE[3:0]
0] B[1:0] N[1:0]


0xE12 0x52 BST_DE _ERR_E RC_EN_ – _ERR_E RR_PER
0] ]
T_EN N GMSL1 N _EN
EOM_M
EOM_PE
0xE13 0xC0 R_MOD EOM_MIN_THR_G1[4:0]
0] N_G1 _REQ_G
E_G1
1
AEQ_PE AEQ_MA
GMSL1_14[7:
0xE14 0x80 AEQ_EN R_MOD N_TRG_ EOM_PER_THR[4:0]
0]
E REQ
GMSL1_15[7:
0xE15 0x00 DET_ERR[7:0]
0]
GMSL1_16[7:
0xE16 0x00 PRBS_ERR[7:0]
0]
MAX_RT MAX_RT
GMSL1_17[7: PRBS_O
0xE17 0x00 RSVD _ERR_I2 GPI_IN _ERR_G – – –
0] K
C PI
GMSL1_18[7:
0xE18 0x00 CC_RETR_CNT[7:0]
0]
GMSL1_19[7:
0xE19 0x00 CC_CRC_ERRCNT[7:0]
0]
GMSL1_1A[7:
0xE1A 0x00 RCEG_ERR_CNT[7:0]
0]
GMSL1_1B[7: LINE_C
0xE1B 0x00 – – – – – – –
0] RC_ERR
GMSL1_1C[7:
0xE1C 0x00 – – EOM_EYE_WIDTH[5:0]
0]
UNDER
GMSL1_1D[7:
0xE1D 0x00 – – – BOOST_ AEQ_BST[3:0]
0]
DET
GMSL1_20[7:
0xE20 0x00 CRC_VALUE_0[7:0]
0]
GMSL1_21[7:
0]
GMSL1_22[7:
0]
GMSL1_23[7:
0]
CONV_
GMSL1_96[7: DBL_ALI
0xE96 0x3B CONV_GMSL1_DATATYPE[4:0] RSVD GMSL1_
0] GN_TO
EN
GMSL1_CB[7 LOCKED
0xECB 0x00 RSVD RSVD RSVD RSVD RSVD RSVD RSVD
:0] _G1
GMSL A
ERRG_E
0x1001 0x00 TX1[7:0] RSVD – – – – RSVD RSVD
N
ERRG_P
0x1002 0x20 TX2[7:0] ERRG_CNT[1:0] ERRG_RATE[1:0] ERRG_BURST[2:0]
ER
0x1003 0x44 TX3[7:0] RSVD[1:0] – – – TIMEOUT[2:0]
0x1004 0x00 RX0[7:0] PKT_CNT_LBW[1:0] – RSVD PKT_CNT_SEL[3:0]


GPIO_T
0x1008 0x41 GPIOA[7:0] RSVD GPIO_FWD_CDLY[5:0]
X_CASC
GPIO_TX_WNDW[1:
0x1009 0x88 GPIOB[7:0] GPIO_REV_CDLY[5:0]
0]
GMSL B
ERRG_E
N
ERRG_P
ER
GPIO_T
X_CASC
GPIO_TX_WNDW[1:
0]
GMSL C
ERRG_E
N
ERRG_P
ER
GPIO_T
X_CASC
GPIO_TX_WNDW[1:
0]
GMSL D
ERRG_E
N
ERRG_P
ER
GPIO_T
X_CASC
GPIO_TX_WNDW[1:
0]
VRX_PATGEN_0 0
PATGEN_0[7:
0x1050 0x03 GEN_VS GEN_HS GEN_DE VS_INV HS_INV DE_INV VTG_MODE[1:0]
0]
PATGEN_1[7: GRAD_ PATGEN_MODE[1:0 VS_TRI
0x1051 0x00 – – – –
0] MODE ] G
VS_DLY_2[7:
0x1052 0x00 VS_DLY_2[7:0]
0]
VS_DLY_1[7:
0x1053 0x00 VS_DLY_1[7:0]
0]
VS_DLY_0[7:
0x1054 0x00 VS_DLY_0[7:0]
0]


VS_HIGH_2[7
0x1055 0x00 VS_HIGH_2[7:0]
:0]
VS_HIGH_1[7
0x1056 0x2A VS_HIGH_1[7:0]
:0]
VS_HIGH_0[7
0x1057 0xF8 VS_HIGH_0[7:0]
:0]
VS_LOW_2[7:
0x1058 0x26 VS_LOW_2[7:0]
0]
VS_LOW_1[7:
0x1059 0x40 VS_LOW_1[7:0]
0]
VS_LOW_0[7:
0x105A 0x00 VS_LOW_0[7:0]
0]
0x105B 0x00 V2H_2[7:0] V2H_2[7:0]
0x105C 0x00 V2H_1[7:0] V2H_1[7:0]
0x105D 0x00 V2H_0[7:0] V2H_0[7:0]
HS_HIGH_1[7
0x105E 0x00 HS_HIGH_1[7:0]
:0]
HS_HIGH_0[7
0x105F 0xD0 HS_HIGH_0[7:0]
:0]
HS_LOW_1[7
0x1060 0x09 HS_LOW_1[7:0]
:0]
HS_LOW_0[7
0x1061 0x50 HS_LOW_0[7:0]
:0]
HS_CNT_1[7:
0x1062 0x04 HS_CNT_1[7:0]
0]
HS_CNT_0[7:
0x1063 0xDA HS_CNT_0[7:0]
0]
0x1064 0x00 V2D_2[7:0] V2D_2[7:0]
0x1065 0x55 V2D_1[7:0] V2D_1[7:0]
0x1066 0xF0 V2D_0[7:0] V2D_0[7:0]
DE_HIGH_1[7
0x1067 0x07 DE_HIGH_1[7:0]
:0]
DE_HIGH_0[7
0x1068 0x80 DE_HIGH_0[7:0]
:0]
DE_LOW_1[7
0x1069 0x00 DE_LOW_1[7:0]
:0]
DE_LOW_0[7
0x106A 0x40 DE_LOW_0[7:0]
:0]
DE_CNT_1[7:
0x106B 0x04 DE_CNT_1[7:0]
0]
DE_CNT_0[7:
0x106C 0xB0 DE_CNT_0[7:0]
0]
GRAD_INCR[
0x106D 0x06 GRAD_INCR[7:0]
7:0]
CHKR_COLO
0x106E 0x80 CHKR_COLOR_A_L[7:0]
R_A_L[7:0]
CHKR_COLO
0x106F 0x00 CHKR_COLOR_A_M[7:0]
R_A_M[7:0]


CHKR_COLO
0x1070 0x04 CHKR_COLOR_A_H[7:0]
R_A_H[7:0]
CHKR_COLO
0x1071 0x00 CHKR_COLOR_B_L[7:0]
R_B_L[7:0]
CHKR_COLO
0x1072 0x08 CHKR_COLOR_B_M[7:0]
R_B_M[7:0]
CHKR_COLO
0x1073 0x80 CHKR_COLOR_B_H[7:0]
R_B_H[7:0]
CHKR_RPT_
0x1074 0x50 CHKR_RPT_A[7:0]
A[7:0]
CHKR_RPT_
0x1075 0x50 CHKR_RPT_B[7:0]
B[7:0]
CHKR_ALT[7:
0x1076 0x50 CHKR_ALT[7:0]
0]
TEST_CTRL
DPLL_A DP_RST
DP_ORSTB_ DP_RST DP_RST DP_RST DP_RST DP_RST DP_RST
0x1191 0xFF UTO_RS _STABL
CTL[7:0] _MIPI3 _MIPI2 _MIPI _VP _FS _CC
T E
VID_PXL_CRC_ERR
0x11D0 0x00 CNT_AX[7:0] VID_PXL_CRC_ERR_AX[7:0]
0x11D1 0x00 CNT_AY[7:0] VID_PXL_CRC_ERR_AY[7:0]
0x11D2 0x00 CNT_AZ[7:0] VID_PXL_CRC_ERR_AZ[7:0]
0x11E0 0x00 CNT_AU[7:0] VID_PXL_CRC_ERR_AU[7:0]
0x11E1 0x00 CNT_BX[7:0] VID_PXL_CRC_ERR_BX[7:0]
0x11E2 0x00 CNT_BY[7:0] VID_PXL_CRC_ERR_BY[7:0]
0x11E3 0x00 CNT_BZ[7:0] VID_PXL_CRC_ERR_BZ[7:0]
0x11E4 0x00 CNT_BU[7:0] VID_PXL_CRC_ERR_BU[7:0]
0x11E5 0x00 CNT_CX[7:0] VID_PXL_CRC_ERR_CX[7:0]
0x11E6 0x00 CNT_CY[7:0] VID_PXL_CRC_ERR_CY[7:0]
0x11E7 0x00 CNT_CZ[7:0] VID_PXL_CRC_ERR_CZ[7:0]
0x11E8 0x00 CNT_CU[7:0] VID_PXL_CRC_ERR_CU[7:0]
0x11E9 0x00 CNT_DX[7:0] VID_PXL_CRC_ERR_DX[7:0]
0x11EA 0x00 CNT_DY[7:0] VID_PXL_CRC_ERR_DY[7:0]
0x11EB 0x00 CNT_DZ[7:0] VID_PXL_CRC_ERR_DZ[7:0]
0x11EC 0x00 CNT_DU[7:0] VID_PXL_CRC_ERR_DU[7:0]
VID_HVD_DET
DE_DET DE_DET DE_DET DE_DET
0x11F0 0x00 DE_DET[7:0] – – – –
_3 _2 _1 _0
HS_DET HS_DET HS_DET HS_DET
0x11F1 0x00 HS_DET[7:0] – – – –
_3 _2 _1 _0
VS_DET VS_DET VS_DET VS_DET
0x11F2 0x00 VS_DET[7:0] – – – –
_3 _2 _1 _0
HS_POL HS_POL HS_POL HS_POL
0x11F3 0x00 HS_POL[7:0] – – – –
_3 _2 _1 _0
VS_POL VS_POL VS_POL VS_POL
0x11F4 0x00 VS_POL[7:0] – – – –
_3 _2 _1 _0


HVD_CN HVD_CN HVD_CN HVD_CN
HVD_CNT_C HVD_CN HVD_CN HVD_CN HVD_CN
0x11F9 0x0F T_RST_ T_RST_ T_RST_ T_RST_
TRL[7:0] T_EN_3 T_EN_2 T_EN_1 T_EN_0
3 2 1 0
HVD_CN HVD_CN HVD_CN HVD_CN
HVD_CNT_O
0x11FA 0x00 – – – – T_OS_E T_OS_E T_OS_E T_OS_E
S[7:0]
N_3 N_2 N_1 N_0
VS_CNT_WN
VS_CNT_WINDOW
0x1200 0x03 DW_0_MSB[7 – – – – – –
_0_MSB[1:0]
:0]
VS_CNT_WN
0x1201 0xE8 DW_0_LSB[7: VS_CNT_WINDOW_0_LSB[7:0]
0]
VS_CNT_0_C
0x1202 0x00 – – VS_CNT_0_CMP[5:0]
MP[7:0]
HS_CNT_0_C
0x1203 0x00 – – – – HS_CNT_0_CMP_MSB[3:0]
MP_MSB[7:0]
HS_CNT_0_C
0x1204 0x00 HS_CNT_0_CMP_LSB[7:0]
MP_LSB[7:0]
DE_CNT_0_C
0x1205 0x00 – – – – DE_CNT_0_CMP_MSB[3:0]
MP_MSB[7:0]
DE_CNT_0_C
0x1206 0x00 DE_CNT_0_CMP_LSB[7:0]
MP_LSB[7:0]
VS_CNT_0[7:
0x1207 0x00 – – VS_CNT_0[5:0]
0]
HS_CNT_0_
0x1208 0x00 – – – – HS_CNT_0_MSB[3:0]
MSB[7:0]
HS_CNT_0_L
0x1209 0x00 HS_CNT_0_LSB[7:0]
SB[7:0]
DE_CNT_0_
0x120A 0x00 – – – – DE_CNT_0_MSB[3:0]
MSB[7:0]
DE_CNT_0_L
0x120B 0x00 DE_CNT_0_LSB[7:0]
SB[7:0]
VS_CNT HS_CNT DE_CNT
VRX_0_CMP
_0_CMP _0_CMP _0_CMP
0x120C 0xE0 _ERR_OEN[7 – – – – –
_ERR_O _ERR_O _ERR_O
:0]
EN EN EN
VRX_0_CMP
0x120D 0x00 _ERR_FLAG[ – – – – –
_ERR_F _ERR_F _ERR_F
7:0]
LAG LAG LAG
VS_CNT_WN
VS_CNT_WINDOW
0x1210 0x03 DW_1_MSB[7 – – – – – –
_1_MSB[1:0]
:0]
VS_CNT_WN
0]
VS_CNT_1_C
0x1212 0x00 – – VS_CNT_1_CMP[5:0]
MP[7:0]
HS_CNT_1_C
0x1213 0x00 – – – – HS_CNT_1_CMP_MSB[3:0]
MP_MSB[7:0]


HS_CNT_1_C
0x1214 0x00 HS_CNT_1_CMP_LSB[7:0]
MP_LSB[7:0]
DE_CNT_1_C
0x1215 0x00 – – – – DE_CNT_1_CMP_MSB[3:0]
MP_MSB[7:0]
DE_CNT_1_C
0x1216 0x00 DE_CNT_1_CMP_LSB[7:0]
MP_LSB[7:0]
VS_CNT_1[7:
0x1217 0x00 – – VS_CNT_1[5:0]
0]
HS_CNT_1_
0x1218 0x00 – – – – HS_CNT_1_MSB[3:0]
MSB[7:0]
HS_CNT_1_L
0x1219 0x00 HS_CNT_1_LSB[7:0]
SB[7:0]
DE_CNT_1_
0x121A 0x00 – – – – DE_CNT_1_MSB[3:0]
MSB[7:0]
DE_CNT_1_L
0x121B 0x00 DE_CNT_1_LSB[7:0]
SB[7:0]
VRX_1_CMP
0x121C 0xE0 _ERR_OEN[7 – – – – –
:0]
EN EN EN
VRX_1_CMP
0x121D 0x00 _ERR_FLAG[ – – – – –
7:0]
LAG LAG LAG
VS_CNT_WN
VS_CNT_WINDOW
0x1220 0x03 DW_2_MSB[7 – – – – – –
_2_MSB[1:0]
:0]
VS_CNT_WN
0]
VS_CNT_2_C
0x1222 0x00 – – VS_CNT_2_CMP[5:0]
MP[7:0]
HS_CNT_2_C
0x1223 0x00 – – – – HS_CNT_2_CMP_MSB[3:0]
MP_MSB[7:0]
HS_CNT_2_C
0x1224 0x00 HS_CNT_2_CMP_LSB[7:0]
MP_LSB[7:0]
DE_CNT_2_C
0x1225 0x00 – – – – DE_CNT_2_CMP_MSB[3:0]
MP_MSB[7:0]
DE_CNT_2_C
0x1226 0x00 DE_CNT_2_CMP_LSB[7:0]
MP_LSB[7:0]
VS_CNT_2[7:
0x1227 0x00 – – VS_CNT_2[5:0]
0]
HS_CNT_2_
0x1228 0x00 – – – – HS_CNT_2_MSB[3:0]
MSB[7:0]
HS_CNT_2_L
0x1229 0x00 HS_CNT_2_LSB[7:0]
SB[7:0]
DE_CNT_2_
0x122A 0x00 – – – – DE_CNT_2_MSB[3:0]
MSB[7:0]
DE_CNT_2_L
0x122B 0x00 DE_CNT_2_LSB[7:0]
SB[7:0]


VRX_2_CMP
0x122C 0xE0 _ERR_OEN[7 – – – – –
:0]
EN EN EN
VRX_2_CMP
0x122D 0x00 _ERR_FLAG[ – – – – –
7:0]
LAG LAG LAG
VS_CNT_WN
VS_CNT_WINDOW
0x1230 0x03 DW_3_MSB[7 – – – – – –
_3_MSB[1:0]
:0]
VS_CNT_WN
0]
VS_CNT_3_C
0x1232 0x00 – – VS_CNT_3_CMP[5:0]
MP[7:0]
HS_CNT_3_C
0x1233 0x00 – – – – HS_CNT_3_CMP_MSB[3:0]
MP_MSB[7:0]
HS_CNT_3_C
0x1234 0x00 HS_CNT_3_CMP_LSB[7:0]
MP_LSB[7:0]
DE_CNT_3_C
0x1235 0x00 – – – – DE_CNT_3_CMP_MSB[3:0]
MP_MSB[7:0]
DE_CNT_3_C
0x1236 0x00 DE_CNT_3_CMP_LSB[7:0]
MP_LSB[7:0]
VS_CNT_3[7:
0x1237 0x00 – – VS_CNT_3[5:0]
0]
HS_CNT_3_
0x1238 0x00 – – – – HS_CNT_3_MSB[3:0]
MSB[7:0]
HS_CNT_3_L
0x1239 0x00 HS_CNT_3_LSB[7:0]
SB[7:0]
DE_CNT_3_
0x123A 0x00 – – – – DE_CNT_3_MSB[3:0]
MSB[7:0]
DE_CNT_3_L
0x123B 0x00 DE_CNT_3_LSB[7:0]
SB[7:0]
VRX_3_CMP
0x123C 0xE0 _ERR_OEN[7 – – – – –
:0]
EN EN EN
VRX_3_CMP
0x123D 0x00 _ERR_FLAG[ – – – – –
7:0]
LAG LAG LAG
TUN_DET
CPHY_M BACKTO BACKTO BACKTO BACKTO
TUN_MODE_
0x1260 0x00 ODE_OV – – – P4_TUN P3_TUN P2_TUN P1_TUN
DET[7:0]
RD_EN _DET _DET _DET _DET
BACKTO BACKTO BACKTO BACKTO BACKTO BACKTO BACKTO BACKTO
TUN_CPHY_ P4_CPH P3_CPH P2_CPH P1_CPH P4_CPH P3_CPH P2_CPH P1_CPH
0x1261 0xF0
DET[7:0] Y_MOD Y_MOD Y_MOD Y_MOD Y_MOD Y_MOD Y_MOD Y_MOD
E_OVRD E_OVRD E_OVRD E_OVRD E_DET E_DET E_DET E_DET


TUN_CPHY_ BACKTOP4_TUN_C BACKTOP3_TUN_C BACKTOP2_TUN_C BACKTOP1_TUN_C
0x1262 0x00 LANE_DET[7: PHY_SER_LANE_D PHY_SER_LANE_D PHY_SER_LANE_D PHY_SER_LANE_D
0] ET[1:0] ET[1:0] ET[1:0] ET[1:0]
BACKTO BACKTO BACKTO
BACKTO BACKTO
TMD_HEADE P1_TMD P1_TMD P1_TMD
P1_TMD P1_TMD
0x1264 0x00 R_ERR_FLA – _CRC_2 _CRC_1 – – _ECC_E
_SP_DE _ECC_F
GS_1[7:0] L_ERR_ L_ERR_ RR_FLA
T_ERR LAG
FLAG FLAG G
BACKTO BACKTO
P2_TMD P2_TMD
_SP_DE _ECC_F
T_ERR LAG
FLAG FLAG G
BACKTO BACKTO
P3_TMD P3_TMD
_SP_DE _ECC_F
T_ERR LAG
FLAG FLAG G
BACKTO BACKTO
P4_TMD P4_TMD
_SP_DE _ECC_F
T_ERR LAG
FLAG FLAG G
TMD_PKT_C
0x126A 0x00 TMD_PKT_CNT_1[7:0]
NT_1[7:0]
TMD_PKT_C
0x126B 0x00 TMD_PKT_CNT_2[7:0]
NT_2[7:0]
TMD_PKT_C
0x126C 0x00 TMD_PKT_CNT_3[7:0]
NT_3[7:0]
TMD_PKT_C
0x126D 0x00 TMD_PKT_CNT_4[7:0]
NT_4[7:0]
TMD_PKT_C
0x126E 0x00 – – – TMD_PKT_CNT_1_H[4:0]
NT_1_H[7:0]
TMD_PKT_C
0x126F 0x00 – – – TMD_PKT_CNT_2_H[4:0]
NT_2_H[7:0]
TMD_PKT_C
0x1270 0x00 – – – TMD_PKT_CNT_3_H[4:0]
NT_3_H[7:0]
TMD_PKT_C
0x1271 0x00 – – – TMD_PKT_CNT_4_H[4:0]
NT_4_H[7:0]
Register Details
REG0 (0x0)
Device I2C address and Blocks I2C register writes

BIT 7 6 5 4 3 2 1 0
CFG_BLOC
Field DEV_ADDR[6:0]
K
Reset 0b0100111 0b0
Access
Write, Read Write, Read
Type

BITFIELD BITS DESCRIPTION DECODE

0b0000000: I2C write/read address is 0x00/0x01
...
...
Device Address 0b1001000: I2C write/read address is 0x90/0x91
Default address is set by the CFG0 pin at 0b1001100: I2C write/read address is 0x98/0x99
DEV_ADDR 7:1 power-up. Refer to data sheet discussion of 0b1101000: I2C write/read address is 0xD0/0xD1
the CFG0 pin for further information. Address 0b1101010: I2C write/read address is 0xD4/0xD5
can be changed following power-up by 0b1101100: I2C write/read address is 0xD8/0xD9
updating the contents of this register. 0b0101000: I2C write/read address is 0x50/0x51
...
...
0b1111111: I2C write/read address is 0xFE/0xFF
Configuration Block
When set, all registers become non-writable

(read-only). Only blocks writeable registers
0b0: Not blocked
CFG_BLOCK 0 from being written. This bit is used to freeze
0b1: Blocked
the chip configuration. After set, this bit
becomes not writeable. To reset the register
to "Not blocked," the part must be powered
down or power cycled.
REG1 (0x1)
BIT 7 6 5 4 3 2 1 0
Field RSVD[1:0] DIS_LOC_CC[1:0] – – – –
Reset 0b11 0b00 – – – –
Access
Write, Read – – – –
Type

0bx0: Port 0 Rx/SDA and Tx/SCL connected to
Disables control channel connection to I2C
control channel
Ports 1 and 0
0bx1: Port 0 Rx/SDA and Tx/SCL disconnected
DIS_LOC_C from control channel
5:4 Bit 4 controls Port 0.
C 0b0x: Port 1 Rx1/SDA1 and Tx1/SCL1 connected
Bit 5 controls Port 1.
to control channel
0b1x: Port 1 Rx1/SDA1 and Tx1/SCL1
See bit 2 for control of control channel Port 2.
disconnected from control channel
REG3 (0x3)
BIT 7 6 5 4 3 2 1 0
Field DIS_REM_CC_D[1:0] DIS_REM_CC_C[1:0] DIS_REM_CC_B[1:0] DIS_REM_CC_A[1:0]
Reset 0b10 0b10 0b10 0b10
Access
Write, Read Write, Read Write, Read Write, Read
Type


Disable GMSL2 remote control channel link
DIS_REM_C from each CC port to Link D 0b0: Remote control channel enabled
7:6
C_D Bit 0 disables the connection from port 0. 0b1: Remote control channel disabled
Bit 1 disables the connection from port 1.
DIS_REM_C from each CC port to Link C 0b0: Remote control channel enabled
5:4
C_C Bit 0 disables the connection from port 0. 0b1: Remote control channel disabled
DIS_REM_C from each CC port to Link B 0b0: Remote control channel enabled
3:2
C_B Bit 0 disables the connection from port 0. 0b1: Remote control channel disabled
DIS_REM_C from each CC port to Link A 0b0: Remote control channel enabled
1:0
C_A Bit 0 disables the connection from port 0. 0b1: Remote control channel disabled
REG4 (0x4)
Video channel - GMSL2 Video pipe access

BIT 7 6 5 4 3 2 1 0
Field – – – – VID_EN_3 VID_EN_2 VID_EN_1 VID_EN_0
Reset – – – – 0b1 0b1 0b1 0b1
Access
– – – – Write, Read Write, Read Write, Read Write, Read
Type

VID_EN3 Video Enable - Video switch used 0b0: Video transmit Channel 3 disabled
VID_EN_3 3
to access Pipe 3 video flow 0b1: Video transmit Channel 3 enabled
VID_EN_2 2
VID_EN_1 1
VID_EN_0 0
REG5 (0x5)
LOCK and ERRB enable and configuration

BIT 7 6 5 4 3 2 1 0
ERRB_LOC ERRB_MST
Field LOCK_EN ERRB_EN LOCK_CFG – – RSVD
K_OEN _RST
Reset 0x1 0x1 0b0 0b0 – –
Access Write Clears
Write, Read Write, Read Write, Read Write, Read – –
Type All, Read

0b0: LOCK output disabled
LOCK_EN 7 Enable LOCK output
0b1: LOCK output enabled
0b0: ERRB output disabled
ERRB_EN 6 Enables ERRB output to GPIO
0b1: ERRB output enabled


Configures LOCK pin behavior.
0b0: GMSL2 link locked
LOCK_CFG 5 See the LOCK_POUT register field for
0b1: GMSL2 link locked and MIPI output started
additional information.
Enable output of lock through the ERRB pin.
1'b0 - Disable
1'b1 - Enable
ERRB_LOCK 0x0: Disable
4 When enabled, if any one of the enabled
_OEN 0x1: Enable
GMSL links is not locked, the status is
reflected on the ERRB pin that is asserted
low.
Master ERRB output reset.
Write 1 to clear all the inputs to the ERRB
generation logic.
This bit self-clears.
ERRB_MST_ 0x0: Disabled
3 Note: This does not clear the error
RST 0x1: Enabled - returns to 0 after assertion
condition(s) that resulted from assertion of
the ERRB output.
The user must address and fix the cause for
the error condition(s) before asserting this
master reset.
REG6 (0x6)
BIT 7 6 5 4 3 2 1 0
Field GMSL2_D GMSL2_C GMSL2_B GMSL2_A LINK_EN_D LINK_EN_C LINK_EN_B LINK_EN_A
Reset 0b1 0b1 0b1 0b1 0x1 0x1 0x1 0x1
Access
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Type

GMSL1/GMSL2 Selection for Link D
0b0: GMSL1
GMSL2_D 7 Bit is set according to the latched CFG1/ 0b1: GMSL2
MFP6 pin value at power-up
GMSL1/GMSL2 Selection for Link C
0b0: GMSL1
GMSL2_C 6 Bit is set according to the latched CFG1/ 0b1: GMSL2
GMSL1/GMSL2 Selection for Link B
0b0: GMSL1
GMSL2_B 5 Bit is set according to the latched CFG1/ 0b1: GMSL2
GMSL1/GMSL2 Selection for Link A
0b0: GMSL1
GMSL2_A 4 Bit is set according to the latched CFG1/ 0b1: GMSL2
0b0: DisableLink D
LINK_EN_D 3 Enables Link D
0b1: Enable Link D
0b0: Disable Link C
LINK_EN_C 2 Enables Link C
0b1: Enable Link C
0b0: Disable Link B
LINK_EN_B 1 Enables Link B
0b1: Enable Link B
0b0: Disable Link A
LINK_EN_A 0 Enables Link A
0b1: Enable Link A

REG7 (0x7)
BIT 7 6 5 4 3 2 1 0
Field CC_CROSSOVER_SEL[3:0] RSVD[3:0]
Reset 0x0
Access
Write, Read
Type

Control Channel Port Crossover Selector
The primary microcontroller must be

connected to I2C Port 0. The secondary
microcontroller(s) should be connected to I2C
Port 1.
Typically, most serializers have only a single

control channel (CC) I2C port which, by
default, is connected across the GMSL2 link
to the GM24 I2C Port 0. The crossover bits
are used to allow the secondary
microcontroller to connect Port 1 to access
the CC in the serializer; otherwise, it is not 0bXXX0XXX0: Link A—No Crossover
possible for the microcontroller on Port 1 to 0bXXX1XXX0: Link A—Enable Crossover between
program the serializer. Port 0 and Port 1
0bXXX0XXX1: Link A—Enable Crossover between
Bits in this register select whether control Port 0 and Port 1
channel port crossover is disabled or enabled 0bXX0XXX0X: Link B—No Crossover
between Port 0 and Port 1 0bXX1XXX0X: Link B—Enable Crossover between
Port 0 and Port 1
Each of the links is controlled by a bit in the 0bXX0XXX1X: Link B—Enable Crossover between
CC_CROSS bitfield. Port 0 and Port 1
7:4
OVER_SEL 0bX0XXX0XX: Link C—No Crossover
The description of each link’s bits are as 0bX1XXX0XX: Link C—Enable Crossover between
follows: Port 0 and Port 1
0bX0XXX1XX: Link C—Enable Crossover between
Link A Port 0 and Port 1
Bit[4]: 0—No Crossover 0b0XXX0XXX: Link D—No Crossover
1—Enable Crossover 0b1XXX0XXX: Link D—Enable Crossover between
between Port 0 and Port 1 Port 0 and Port 1
0b0XXX1XXX: Link D—Enable Crossover between
Link B Port 0 and Port 1
Bit[5]: 0—No Crossover
1—Enable Crossover
between Port 0 and Port 1
Link C
Bit[6] 0—No Crossover
Link D
Bit[7]: 0—No Crossover

CTRL12 (0xA)
GMSL Link Lock status

BIT 7 6 5 4 3 2 1 0
Field RSVD RSVD – – LOCKED_B – – –
Reset 0b0 0b0 – – 0b0 – – –
Access
– – Read Only – – –
Type

0b0: GMSL2 link not locked
LOCKED_B 3 GMSL2 Link Locked - Link B Only
CTRL13 (0xB)

BIT 7 6 5 4 3 2 1 0
Field RSVD RSVD – – LOCKED_C – – –
Reset 0b0 0b0 – – 0b0 – – –
Access
Type

LOCKED_C 3 GMSL2 Link Locked - Link C Only
CTRL14 (0xC)

BIT 7 6 5 4 3 2 1 0
Field RSVD RSVD – – LOCKED_D – – –
Reset 0b0 0b0 – – 0b0 – – –
Access
Type

LOCKED_D 3 GMSL2 Link Locked - Link D Only
REG13 (0xD)
BIT 7 6 5 4 3 2 1 0
Field DEV_ID[7:0]
Reset 0xA2
Access
Read Only
Type

0xA2: MAX96724
DEV_ID 7:0 Device Identifier 0xA3: MAX96724F
0xA4: MAX96724R

REG26 (0x10)
BIT 7 6 5 4 3 2 1 0
Field TX_RATE_PHYB[1:0] RX_RATE_PHYB[1:0] TX_RATE_PHYA[1:0] RX_RATE_PHYA[1:0]
Reset 0x0 0x2 0x0 0x2
Access
Type

0b00: 187.5Mbps
TX_RATE_P Transmitter Rate (when changed, becomes 0b01: Reserved
7:6
HYB active after next link reset) 0b10: Reserved
0b11: Reserved
Receiver Rate (when changed, becomes
0b00: Reserved
active after next link reset)
RX_RATE_P 0b01: 3Gbps
5:4
HYB 0b10: 6Gbps
Default value is set by CFG1/MFP6 pin at
0b11: Reserved
power-up.
0b00: 187.5Mbps
3:2
HYA active after next link reset) 0b10: Reserved
0b11: Reserved
0b00: Reserved
1:0
HYA 0b10: 6Gbps
0b11: Reserved
power-up.
REG27 (0x11)
BIT 7 6 5 4 3 2 1 0
Field TX_RATE_PHYD[1:0] RX_RATE_PHYD[1:0] TX_RATE_PHYC[1:0] RX_RATE_PHYC[1:0]
Access
Type

0b00: 187.5Mbps
7:6
HYD active after next link reset) 0b10: Reserved
0b11: Reserved
0b00: Reserved
5:4
HYD 0b10: 6Gbps
0b11: Reserved
power-up.
0b00: 187.5Mbps
3:2
HYC active after next link reset) 0b10: Reserved
0b11: Reserved


0b00: Reserved
1:0
HYC 0b10: 6Gbps
0b11: Reserved
power-up.
PWR0 (0x12)
BIT 7 6 5 4 3 2 1 0
Field VDDBAD_STATUS[2:0] CMP_STATUS[4:0]
Reset 0x0 0x0
Access
Read Only Read Only
Type

0bXX1: Latched high when VDDA_sw < 0.82V
VDDBAD_ST Power manager switched 1V supply
7:5 0bX1X: Latched high when VDD_sw < 0.82V
ATUS comparator status bits.
0b1XX: Reserved
0bXXXX0: Latched low when VDD18 < 1.617V
0bXXX0X: Latched low when switched VDDIO
CMP_STATU supply < 1.617V
4:0 Power manager comparator status bits.
S 0bXX0XX: Latched low when CAPVDD < 0.82V
0bX0XXX: Reserved
0b0XXXX: Reserved
PWR1 (0x13)
BIT 7 6 5 4 3 2 1 0
RESET_AL
Field RSVD RSVD[5:0]
L
Reset 0b0 0b0 0x0
Access
Write, Read
Type

Device Reset
Writing 1 to this bit resets the device. All

0b0: No action
RESET_ALL 6 blocks and registers are reset to defaults.
0b1: Activate chip reset
This is equivalent to toggling the PWDNB pin.
The bit is cleared when written.
CTRL1 (0x18)
BIT 7 6 5 4 3 2 1 0
RESET_LIN RESET_LIN RESET_LIN RESET_LIN RESET_ON RESET_ON RESET_ON RESET_ON
Field
K_D K_C K_B K_A ESHOT_D ESHOT_C ESHOT_B ESHOT_A
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access Write Clears Write Clears Write Clears Write Clears
Type All, Read All, Read All, Read All, Read


Link D Reset
Resets whole data path (keep register

RESET_LIN 0b0: Release link reset
7 settings).
K_D 0b1: Activate link reset
Write 1 to activate reset, write 0 to release
reset.
Link C Reset

6 settings).
K_C 0b1: Activate link reset
reset.
Link B Reset

5 settings).
K_B 0b1: Activate link reset
reset.
Link A Reset

4 settings).
K_A 0b1: Activate link reset
reset.
Link D One-Shot Reset

RESET_ONE 0b0: No action
3 settings) one shot.
SHOT_D 0b1: Reset data path
Write 1 to activate reset, bit self-clears and
automatically releases reset.
Link C One-Shot Reset

SHOT_C 0b1: Reset data path
Link B One-Shot Reset

SHOT_B 0b1: Reset data path
Link A One-Shot Reset

SHOT_A 0b1: Reset data path

CTRL3 (0x1A)
BIT 7 6 5 4 3 2 1 0
CMU_LOC
Field RSVD RSVD RSVD[1:0] LOCKED_A ERROR LOCK_PIN
KED
Reset 0b0 0b0 0x1 0b0 0b0 0b0 0x0
Access
Read Only Read Only Read Only Read Only
Type

LOCKED_A 3 GMSL2 link lock (bidirectional)—Link A only
Reflects error status (inverse of ERRB pin 0b0: ERRB not asserted (ERRB pin = 1)
ERROR 2
value) 0b1: ERRB asserted (ERRB pin = 0)
CMU_LOCK 0b0: CMU not locked
1 Clock Multiplier Unit (CMU) lock
ED 0b1: CMU locked
Reflects LOCK pin output.
See the LOCK_EN, LOCK_CFG, and
0x0: 1 or more enabled GMSL links are not locked
LOCK_PIN 0 ERRB_LOCK register fields for additional
0x1: All enabled GMSL links are locked
information.
CTRL11 (0x22)
BIT 7 6 5 4 3 2 1 0
Field RSVD CXTP_D RSVD CXTP_C RSVD CXTP_B RSVD CXTP_A
Reset 0b1 0b1 0b1 0b1 0b1 0b1 0b1 0b1
Access
Type

Coax/Twisted-Pair Cable Select for Link D
0b0: Shielded twisted-pair drive
CXTP_D 6 Bit is set according to the latched CFG1/ 0b1: Coax drive
MFP6 pin value at power-up.
Coax/Twisted-Pair Cable Select for Link C
CXTP_C 4 Bit is set according to the latched CFG1/ 0b1: Coax drive
Coax/Twisted-Pair Cable Select for Link B
CXTP_B 2 Bit is set according to the latched CFG1/ 0b1: Coax drive
Coax/Twisted-Pair Cable Select for Link A
CXTP_A 0 Bit is set according to the latched CFG1 pin 0b1: Coax drive
value at power-up.

INTR2 (0x25)
BIT 7 6 5 4 3 2 1 0
DEC_ERR_ DEC_ERR_ DEC_ERR_ DEC_ERR_
Field RSVD RSVD RSVD RSVD
OEN_D OEN_C OEN_B OEN_A
Reset 0b0 0b0 0b0 0b0 0b1 0b1 0b1 0b1
Access
Type

0b0: Disable reporting of decoding errors
DEC_ERR_ Enables reporting of decoding errors (DEC_ERR_FLAG_D) at ERRB pin
3
OEN_D (DEC_ERR_FLAG_D—0x26) at ERRB pin. 0b1: Enable reporting of decoding errors
(DEC_ERR_FLAG_D) at ERRB pin
DEC_ERR_ Enables reporting of decoding errors (DEC_ERR_FLAG_C) at ERRB pin
2
OEN_C (DEC_ERR_FLAG_C—0x26) at ERRB pin. 0b1: Enable reporting of decoding errors
(DEC_ERR_FLAG_C) at ERRB pin
DEC_ERR_ Enables reporting of decoding errors (DEC_ERR_FLAG_B) at ERRB pin
1
OEN_B (DEC_ERR_FLAG_B—0x26) at ERRB pin. 0b1: Enable reporting of decoding errors
(DEC_ERR_FLAG_B) at ERRB pin
DEC_ERR_ Enables reporting of decoding errors (DEC_ERR_FLAG_A) at ERRB pin
0
OEN_A (DEC_ERR_FLAG_A—0x26) at ERRB pin. 0b1: Enable reporting of decoding errors
(DEC_ERR_FLAG_A) at ERRB pin
INTR3 (0x26)
BIT 7 6 5 4 3 2 1 0
DEC_ERR_ DEC_ERR_ DEC_ERR_ DEC_ERR_
FLAG_D FLAG_C FLAG_B FLAG_A
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type

Decoding error flag for Link D, asserted when
DEC_ERR_F DEC_ERR_D ≥ DEC_ERR_THR. 0b0: DEC_ERR_D < DEC_ERR_THR
3
LAG_D 0b1: DEC_ERR_D ≥ DEC_ERR_THR
To clear this flag, read register DEC_ERR_D
Decoding error flag for Link C, asserted when
DEC_ERR_F DEC_ERR_C ≥ DEC_ERR_THR. 0b0: DEC_ERR_C < DEC_ERR_THR
2
LAG_C 0b1: DEC_ERR_C ≥ DEC_ERR_THR
To clear this flag, read register DEC_ERR_C
Decoding error flag for Link B, asserted when
DEC_ERR_F DEC_ERR_B ≥ DEC_ERR_THR. 0b0: DEC_ERR_B < DEC_ERR_THR
1
LAG_B 0b1: DEC_ERR_B ≥ DEC_ERR_THR
To clear this flag, read register DEC_ERR_B
Decoding error flag for Link A, asserted when
DEC_ERR_F DEC_ERR_A ≥ DEC_ERR_THR. 0b0: DEC_ERR_A < DEC_ERR_THR
0
LAG_A 0b1: DEC_ERR_A ≥ DEC_ERR_THR
To clear this flag, read register DEC_ERR_A

INTR4 (0x27)
BIT 7 6 5 4 3 2 1 0
EOM_ERR_ EOM_ERR_ EOM_ERR_ EOM_ERR_ LFLT_INT_
Field RSVD – –
OEN_D OEN_C OEN_B OEN_A OEN
Reset 0b1 0b1 0b1 0b1 0b0 0x1 – –
Access
Write, Read Write, Read Write, Read Write, Read Write, Read – –
Type

0b0: Disable reporting of eye-opening monitor error
Enables reporting of eye-opening monitor
EOM_ERR_ (EOM_ERR_FLAG_D) for Link D at ERRB pin
7 error (EOM_ERR_FLAG_D—0x28) for Link D
OEN_D 0b1: Enable reporting of eye-opening monitor error
at ERRB pin.
(EOM_ERR_FLAG_D) for Link D at ERRB pin
EOM_ERR_ (EOM_ERR_FLAG_C) for Link C at ERRB pin
6 error (EOM_ERR_FLAG_C—0x28) for Link
OEN_C 0b1: Enable reporting of eye-opening monitor error
C at ERRB pin.
(EOM_ERR_FLAG_C) for Link C at ERRB pin
EOM_ERR_ (EOM_ERR_FLAG_B) for Link B at ERRB pin
5 error (EOM_ERR_FLAG_B—0x28) for Link B
OEN_B 0b1: Enable reporting of eye-opening monitor error
at ERRB pin.
(EOM_ERR_FLAG_B) for Link B at ERRB pin
EOM_ERR_ (EOM_ERR_FLAG_A) for Link A at ERRB pin
4 error (EOM_ERR_FLAG_A0x28) for Link A at
OEN_A 0b1: Enable reporting of eye-opening monitor error
ERRB pin.
(EOM_ERR_FLAG_A) for Link A at ERRB pin
0b0: Disable reporting of line fault interrupt
LFLT_INT_O Enable reporting of line fault interrupt (LFLT_INT) at ERRB pin
2
EN (LFLT_INT) at ERRB pin 0b1: Enable reporting of line fault interrupt
(LFLT_INT) at ERRB pin
INTR5 (0x28)
BIT 7 6 5 4 3 2 1 0
EOM_ERR_ EOM_ERR_ EOM_ERR_ EOM_ERR_
Field RSVD LFLT_INT – –
Reset 0b0 0b0 0b0 0b0 0x0 0b0 – –
Access
Read Only Read Only Read Only Read Only Read Only – –
Type

Link D Eye-opening Threshold Status 0b0: Eye-opening is above configured threshold for
EOM_ERR_ Link D
7
FLAG_D Indicates whether or not eye-opening is 0b1: Eye-opening is below configured threshold for
below configured threshold for Link D. Link D
Link C Eye-opening Threshold Status 0b0: Eye-opening is above configured threshold for
EOM_ERR_ Link C
6
FLAG_C Indicates whether or not eye-opening is 0b1: Eye-opening is below configured threshold for
below configured threshold for Link C. Link C
Link B Eye-opening Threshold Status 0b0: Eye-opening is above configured threshold for
EOM_ERR_ Link B
5
FLAG_B Indicates whether or not eye-opening is 0b1: Eye-opening is below configured threshold for
below configured threshold for Link B. Link B


Link A Eye-opening Threshold Status 0b0: Eye-opening is above configured threshold for
EOM_ERR_ Link A
4
FLAG_A Indicates whether or not eye-opening is 0b1: Eye-opening is below configured threshold for
below configured threshold for Link A. Link A
Line Fault Interrupt
Asserted when any one of the line fault

monitors indicates a fault status.
When enabled, this interrupt will be enabled

onto the ERRB pin. See register
LFLT_INT_OEN
0x0: no Line Fault interrupt asserted
LFLT_INT 2 See the LF_0, LF_1, LF_2, LF_3, and
0x1: Line Fault Interrupt asserted
LFLT_INT_FLAG register fields.
Note: This bit is sticky and will only be

cleared when the LFLT_INT_FLAG is read.
The individual line fault interrupt outputs

maybe masked. See the MASK_LF0,
MASK_LF1, MASK_LF2, and MASK_LF3
registers.
INTR6 (0x29)
BIT 7 6 5 4 3 2 1 0
G1_D_ERR G1_C_ERR G1_B_ERR G1_A_ERR LCRC_ERR VPRBS_ER REM_ERR_ FSYNC_ER
Field
_OEN _OEN _OEN _OEN _OEN R_OEN OEN R_OEN
Reset 0x1 0x1 0x1 0x1 0b1 0b1 0b1 0b1
Access
Type

Enables reporting of GMSL1 Link D errors
(G1_D_ERR_FLAG) at ERRB pin.
This controls a composite output to the ERRB

pin.
Individual error flag outputs to the ERRB pin
are controlled by the following registers for
Link D:
DET_ERRB_OEN (DER_ERR_FLAG)
0b0: Disable GMSL1 Link D error reporting
EOM_ERRB_OEN (EOM_ERR_FLAG)
G1_D_ERR_ (G1_D_ERR_FLAG) at ERRB pin
7 LINE_CRC_ERRB_OEN
OEN 0b1: Enable GMSL1 Link D error reporting
(LINE_CRC_ERR_FLAG)
(G1_D_ERR_FLAG) at ERRB pin
UNDERBST_DET_ERRB_OEN
(UNDERBST_DET_FLAG)
MAX_RT_I2C_ERRB_OEN
(MAX_RT_I2C_ERR_FLAG)
MAX_RT_GPI_ERRB_OEN
(MAX_RT_GPI_ERR_FLAG)
CC_CRC_ERRB_OEN
(CC_CRC_ERR_FLAG)
PRBS_ERRB_OEN (PRBS_ERR_FLAG)


Enables reporting of GMSL1 Link C errors
(G1_C_ERR_FLAG) at ERRB pin.

pin.
Link C:
0b0: Disable GMSL1 Link C error reporting
G1_C_ERR_ (G1_C_ERR_FLAG) at ERRB pin
6 LINE_CRC_ERRB_OEN
OEN 0b1: Enable GMSL1 Link C error reporting
(LINE_CRC_ERR_FLAG)
(G1_C_ERR_FLAG) at ERRB pin
(UNDERBST_DET_FLAG)
MAX_RT_I2C_ERRB_OEN
MAX_RT_GPI_ERRB_OEN
CC_CRC_ERRB_OEN
(CC_CRC_ERR_FLAG)
Enables reporting of GMSL1 Link B errors
(G1_B_ERR_FLAG) at ERRB pin.

pin.
Link B:
0b0: Disable GMSL1 Link B error reporting
G1_B_ERR_ (G1_B_ERR_FLAG) at ERRB pin
5 LINE_CRC_ERRB_OEN
OEN 0b1: Enable GMSL1 Link B error reporting
(LINE_CRC_ERR_FLAG)
(G1_B_ERR_FLAG) at ERRB pin
(UNDERBST_DET_FLAG)
MAX_RT_I2C_ERRB_OEN
MAX_RT_GPI_ERRB_OEN
CC_CRC_ERRB_OEN
(CC_CRC_ERR_FLAG)


Enables reporting of GMSL1 Link A errors
(G1_A_ERR_FLAG) at ERRB pin.

pin.
Link A:
0b0: Disable GMSL1 Link A error reporting
G1_A_ERR_ (G1_A_ERR_FLAG) at ERRB pin
4 LINE_CRC_ERRB_OEN
OEN 0b1: Enable GMSL1 Link A error reporting
(LINE_CRC_ERR_FLAG)
(G1_A_ERR_FLAG) at ERRB pin
(UNDERBST_DET_FLAG)
MAX_RT_I2C_ERRB_OEN
MAX_RT_GPI_ERRB_OEN
CC_CRC_ERRB_OEN
(CC_CRC_ERR_FLAG)
0b0: Disable video line CRC error reporting
LCRC_ERR_ Enables reporting of video line CRC errors (LCRC_ERR_FLAG) at ERRB pin
3
OEN (LCRC_ERR_FLAG—0x2A) at ERRB pin. 0b1: Enable video line CRC error reporting
(LCRC_ERR_FLAG) at ERRB pin
0b0: Disable video PRBS error reporting
VPRBS_ERR Enables reporting of video PRBS errors (VPRBS_ERR_FLAG) at ERRB pin
2
_OEN (VPRBS_ERR_FLAG—0x2A) at ERRB pin. 0b1: Enable video PRBS error reporting
(VPRBS_ERR_FLAG) at ERRB pin
0b0: Disable remote error status (REM_ERR)
REM_ERR_ Enables reporting of remote error status reporting at ERRB pin
1
OEN (REM_ERR—0x2A) at ERRB pin. 0b1: Enable remote error status (REM_ERR)
reporting at ERRB pin
0b0: Disable frame sync error reporting
FSYNC_ERR Enables reporting of frame sync errors (FSYNC_ERR_FLAG) at ERRB pin
0
_OEN (FSYNC_ERR_FLAG—0x2A) at ERRB pin. 0b1: Enable frame sync error reporting
(FSYNC_ERR_FLAG) at ERRB pin
INTR7 (0x2A)
BIT 7 6 5 4 3 2 1 0
G1_D_ERR G1_C_ERR G1_B_ERR G1_A_ERR LCRC_ERR VPRBS_ER REM_ERR_ FSYNC_ER
Field
_FLAG _FLAG _FLAG _FLAG _FLAG R_FLAG FLAG R_FLAG
Reset 0x0 0x0 0x0 0x0 0b0 0b0 0b0 0b0
Access
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Type


GMSL1 Link D Error Flag
When PRBS test is enabled, this bit is

asserted if at least one PRBS error is
detected.
When PRBS test is not enabled, this flag is

asserted when any of these conditions is true:
1. The number of detected decoding errors is

greater than the detected error threshold
(DET_ERR (0xB15) > DET_THR (0xC0E)).
G1_D_ERR_ 2. The measured eye-opening is less than or 0b0: No error detected

7
FLAG equal to the eye-opening threshold 0b1: Error detected
(EOM_EYE_WIDTH (0xC1C) ≤
EOM_MIN_THR_G1 (0xB13)).
3. The adaptive EQ has detected an under

boost.
4. A video line CRC error is detected.
5. The maximum retransmission count in

PKTCC communication has been exceeded.
6. A CRC error is detected in PKTCC

communication.
GMSL1 Link C Error Flag

detected.

asserted when any of these conditions are
true:

(DET_ERR (0xB15) > DET_THR (0xCOE)).
G1_C_ERR_ 0b0: No error detected
6 2. The measured eye-opening is less than or
FLAG 0b1: Error detected
equal to the eye-opening threshold

boost.

PKTCC communication is exceeded.

communication.


GMSL1 Link B Error Flag

detected.

true:

G1_B_ERR_ 0b0: No error detected

boost.


communication.
GMSL1 Link A Error Flag

detected.

true:

G1_A_ERR_ 0b0: No error detected

boost.


communication.


Video Line CRC Error Flag
LCRC_ERR_ 0b0: No video line CRC error detected
3
FLAG Assert when a video line CRC error is 0b1: Video line CRC error detected
detected.
Video PRBS Error Flag
VPRBS_ERR 0b0: VPRBS_ERR ≤ 0
2
_FLAG 0b1: VPRBS_ERR > 0
Asserted when VPRBS_ERR (0x1D8) > 0.
REM_ERR_F Receives remote side error status (inverse of 0b0: No remote side error status received
1
LAG remote side ERRB pin level). 0b1: Remote side error status received
Frame Sync Error Flag
FSYNC_ERR 0b0: FSYNC_ERR_CNT < FSYNC_ERR_THR
0
_FLAG Asserted when FSYNC_ERR_CNT (0x4B0) ≥ 0b1: FSYNC_ERR_CNT ≥ FSYNC_ERR_THR
FSYNC_ERR_THR (0x4B1).
INTR8 (0x2B)
BIT 7 6 5 4 3 2 1 0
IDLE_ERR_ IDLE_ERR_ IDLE_ERR_ IDLE_ERR_
OEN_D OEN_C OEN_B OEN_A
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type

0b0: Disable idle word error reporting
IDLE_ERR_ Enables reporting of idle word errors (IDLE_ERR_FLAG_D) at ERRB pin
3
OEN_D (IDLE_ERR_FLAG_D) at ERRB pin. 0b1: Enable idle word error reporting
(IDLE_ERR_FLAG_D) at ERRB pin
IDLE_ERR_ Enables reporting of idle word errors (IDLE_ERR_FLAG_C) at ERRB pin
2
OEN_C (IDLE_ERR_FLAG_C) at ERRB pin. 0b1: Enable idle word error reporting
(IDLE_ERR_FLAG_C) at ERRB pin
IDLE_ERR_ Enables reporting of idle word errors (IDLE_ERR_FLAG_B) at ERRB pin
1
OEN_B (IDLE_ERR_FLAG_B) at ERRB pin. 0b1: Enable idle word error reporting
(IDLE_ERR_FLAG_B) at ERRB pin
IDLE_ERR_ Enables reporting of idle word errors (IDLE_ERR_FLAG_A) at ERRB pin
0
OEN_A (IDLE_ERR_FLAG_A) at ERRB pin. 0b1: Enable idle word error reporting
(IDLE_ERR_FLAG_A) at ERRB pin
INTR9 (0x2C)
BIT 7 6 5 4 3 2 1 0
IDLE_ERR_ IDLE_ERR_ IDLE_ERR_ IDLE_ERR_
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type


Idle Word Error Flag D
IDLE_ERR_F 0b0: IDLE_ERR_D < DEC_ERR_THR
3
LAG_D Asserted when IDLE_ERR_D (0x3C) ≥ 0b1: IDLE_ERR_D ≥ DEC_ERR_THR
DEC_ERR_THR (0x23).
Idle Word Error Flag C
IDLE_ERR_F 0b0: IDLE_ERR_C < DEC_ERR_THR
2
LAG_C Asserted when IDLE_ERR_C (0x3B) ≥ 0b1: IDLE_ERR_C ≥ DEC_ERR_THR
DEC_ERR_THR.
Idle Word Error Flag B
IDLE_ERR_F 0b0: IDLE_ERR_B < DEC_ERR_THR
1
LAG_B Asserted when IDLE_ERR_B (x3A0 ≥ 0b1: IDLE_ERR_B ≥ DEC_ERR_THR
DEC_ERR_THR (0x23).
Idle Word Error Flag A
IDLE_ERR_F 0b0: IDLE_ERR_A < DEC_ERR_THR
0
LAG_A Asserted when IDLE_ERR_A (0x39) ≥ 0b1: IDLE_ERR_A ≥ DEC_ERR_THR
DEC_ERR_THR (0x23).
INTR10 (0x2D)
BIT 7 6 5 4 3 2 1 0
RT_CNT_O RT_CNT_O RT_CNT_O RT_CNT_O MAX_RT_O MAX_RT_O MAX_RT_O MAX_RT_O
Field
EN_D EN_C EN_B EN_A EN_D EN_C EN_B EN_A
Reset 0b0 0b0 0b0 0b0 0b1 0b1 0b1 0b1
Access
Type

0b0: Disable reporting of combined ARQ
retransmission event flag (RT_CNT_FLAG_D) at
Enables reporting of combined ARQ
RT_CNT_OE ERRB pin
7 retransmission event flag
N_D 0b1: Enable reporting of combined ARQ
(RT_CNT_FLAG_D—0x2E) at ERRB pin.
retransmission event flag (RT_CNT_FLAG_D) at
ERRB pin
retransmission event flag (RT_CNT_FLAG_C) at
RT_CNT_OE ERRB pin
N_C 0b1: Enable reporting of combined ARQ
(RT_CNT_FLAG_C—0x2E) at ERRB pin.
retransmission event flag (RT_CNT_FLAG_C) at
ERRB pin
retransmission event flag (RT_CNT_FLAG_B) at
RT_CNT_OE ERRB pin
N_B 0b1: Enable reporting of combined ARQ
(RT_CNT_FLAG_B—0x2E) at ERRB pin.
retransmission event flag (RT_CNT_FLAG_B) at
ERRB pin
retransmission event flag (RT_CNT_FLAG_A) at
RT_CNT_OE ERRB pin
N_A 0b1: Enable reporting of combined ARQ
(RT_CNT_FLAG_A—0x2E) at ERRB pin.
retransmission event flag (RT_CNT_FLAG_A) at
ERRB pin


0b0: Disable reporting of combined ARQ maximum
retransmission limit error flag (MAX_RT_FLAG_D)
MAX_RT_OE at ERRB pin
3 maximum retransmission limit error flag
N_D 0b1: Enable reporting of combined ARQ maximum
(MAX_RT_FLAG_D—0x2E) at ERRB pin.
retransmission limit error flag (MAX_RT_FLAG_D)
at ERRB pin
retransmission limit error flag (MAX_RT_FLAG_C)
N_C 0b1: Enable reporting of combined ARQ maximum
(MAX_RT_FLAG_C—0x2E) at ERRB pin.
retransmission limit error flag (MAX_RT_FLAG_C)
at ERRB pin
retransmission limit error flag (MAX_RT_FLAG_B)
N_B 0b1: Enable reporting of combined ARQ maximum
(MAX_RT_FLAG_B—0x2E) at ERRB pin.
retransmission limit error flag (MAX_RT_FLAG_B)
at ERRB pin
retransmission limit error flag (MAX_RT_FLAG_A)
N_A 0b1: Enable reporting of combined ARQ maximum
(MAX_RT_FLAG_A—0x2E) at ERRB pin.
retransmission limit error flag (MAX_RT_FLAG_A)
at ERRB pin
INTR11 (0x2E)
BIT 7 6 5 4 3 2 1 0
RT_CNT_F RT_CNT_F RT_CNT_F RT_CNT_F MAX_RT_F MAX_RT_F MAX_RT_F MAX_RT_F
Field
LAG_D LAG_C LAG_B LAG_A LAG_D LAG_C LAG_B LAG_A
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type

Combined ARQ Retransmission Event Flag D
0b0: None of the selected channels have done at
RT_CNT_FL Asserted when any of the selected channels least one ARQ retransmission
7
AG_D have done at least one ARQ retransmission. 0b1: One or more of the selected channels has
Selection is done by each channel's done at least one ARQ retransmission
RT_CNT_OEN_D (0x2D) register bit.
Combined ARQ Retransmission Event Flag C
6
AG_C have done at least one ARQ retransmission. 0b1: One or more of the selected channels has
RT_CNT_OEN_C (0x2D) register bit.
Combined ARQ Retransmission Event Flag B
5
AG_B have done at least one ARQ retransmission. 0b1: One or more of the selected channels has
RT_CNT_OEN_B (0x2D) register bit.


Combined ARQ Retransmission Event Flag A
4
AG_A have done at least one ARQ retransmission. 0b1: One or more of the selected channels has
RT_CNT_OEN_A (0x2D) register bit.
Combined ARQ Maximum Retransmission
Limit Error Flag D
0b0: None of the selected channels have reached
MAX_RT_FL the maximum retry limit
3 Asserted when any of the selected channel's
AG_D 0b1: One or more of the selected channels has
ARQ retransmission limit is reached.
reached the maximum retry limit
Selection is done by each channel's
MAX_RT_ERR_OEN_D (0x2D) register bit.
Limit Error Flag C
AG_C 0b1: One or more of the selected channels has
MAX_RT_ERR_OEN_C (0x2D) register bit.
Limit Error Flag B
AG_B 0b1: One or more of the selected channels has
MAX_RT_ERR_OEN_B (0x2D) register bit.
Limit Error Flag A
AG_A 0b1: One or more of the selected channels has
MAX_RT_ERR_OEN_A (0x2D) register bit.
INTR12 (0x2F)
BIT 7 6 5 4 3 2 1 0
ERR_TX_E
Field – – ERR_TX_ID[4:0]
N
Reset 0b1 – – 0x1F
Access
Write, Read – – Write, Read
Type

0b0: Do not transmit local error status to remote
Transmits local error status (inverse of ERRB
side through GPIO channel
ERR_TX_EN 7 pin level) to remote side through GPIO
0b1: Transmit local error status to remote side
channel.
through GPIO channel
ERR_TX_ID 4:0 GPIO ID used for transmitting ERR_TX. 0bXXXXX: GPIO ID used for transmitting ERR_TX

INTR13 (0x30)
BIT 7 6 5 4 3 2 1 0
ERR_RX_E ERR_RX_R
Field – ERR_RX_ID_A[4:0]
N_A ECVED_A
Reset 0b1 0b1 – 0x1F
Access
Write, Read Write, Read – Write, Read
Type

0b0: Do not receive remote error status through
Receives remote error status (inverse of
ERR_RX_EN GPIO channel for GMSL2 Link A
7 ERRB pin level) through GPIO channel for
_A 0b1: Receive remote error status through GPIO
GMSL2 Link A.
channel for GMSL2 Link A
ERR_RX_RE 0b0: ERR_RX value for Link A received
6 Received ERR_RX value for Link A
CVED_A 0b1: ERR_RX value for Link A not received
ERR_RX_ID GPIO ID used for receiving ERR_RX for 0bXXXXX: GPIO ID used for receiving ERR_RX
4:0
_A GMSL2 Link A. Link A
INTR14 (0x31)
BIT 7 6 5 4 3 2 1 0
ERR_RX_E ERR_RX_R
Field – ERR_RX_ID_B[4:0]
N_B ECVED_B
Access
Type

ERR_RX_EN GPIO channel for GMSL2 Link B
_B 0b1: Receive remote error status through GPIO
GMSL2 Link B.
channel for GMSL2 Link B
ERR_RX_RE 0x0: ERR_RX value for Link B received
6 Received ERR_RX value for link B
CVED_B 0x1: ERR_RX value for Link B not received
4:0
_B GMSL2 Link B. Link B
INTR15 (0x32)
BIT 7 6 5 4 3 2 1 0
ERR_RX_E ERR_RX_R
Field – ERR_RX_ID_C[4:0]
N_C ECVED_C
Access
Type

ERR_RX_EN GPIO channel for GMSL2 Link C
_C 0b1: Receive remote error status through GPIO
GMSL2 Link C.
channel for GMSL2 Link C


ERR_RX_RE 0x0: ERR_RX value for Link C received
6 Received ERR_RX value for Link C
CVED_C 0x1: ERR_RX value for Link C not received
4:0
_C GMSL2 link C link C
INTR16 (0x33)
BIT 7 6 5 4 3 2 1 0
ERR_RX_E ERR_RX_R
Field – ERR_RX_ID_D[4:0]
N_D ECVED_D
Access
Type

ERR_RX_EN GPIO channel for GMSL2 Link D
_D 0b1: Receive remote error status through GPIO
GMSL2 Link D.
channel for GMSL2 Link D
ERR_RX_RE 0x0: ERR_RX value for Link D received
6 Received ERR_RX value for Link D
CVED_D 0x1: ERR_RX value for Link D not received
4:0
_D GMSL2 link D link D
CNT0 (0x35)
BIT 7 6 5 4 3 2 1 0
Field DEC_ERR_A[7:0]
Reset 0x00
Access
Read Clears All
Type

The number of decoding (disparity) errors
detected at Link A
DEC_ERR_A 7:0 0xXX: Number of Link A decoding errors detected
Reset after reading or with the rising edge of
LOCK.
CNT1 (0x36)
BIT 7 6 5 4 3 2 1 0
Field DEC_ERR_B[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at Link B
DEC_ERR_B 7:0 0xXX: Number of Link B decoding errors detected
LOCK.

CNT2 (0x37)
BIT 7 6 5 4 3 2 1 0
Field DEC_ERR_C[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at Link C
DEC_ERR_C 7:0 0xXX: Number of Link C decoding errors detected
LOCK.
CNT3 (0x38)
BIT 7 6 5 4 3 2 1 0
Field DEC_ERR_D[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at Link D
DEC_ERR_D 7:0 0xXX: Number of Link D decoding errors detected
LOCK.
CNT4 (0x39)
BIT 7 6 5 4 3 2 1 0
Field IDLE_ERR_A[7:0]
Reset 0x00
Access
Read Clears All
Type

The number of idle word errors detected at
IDLE_ERR_ Link A
7:0 0xXX: Number of idle word errors detected
A Reset after reading or with the rising edge of
LOCK.
CNT5 (0x3A)
BIT 7 6 5 4 3 2 1 0
Field IDLE_ERR_B[7:0]
Reset 0x00
Access
Read Clears All
Type


IDLE_ERR_ Link B
B Reset after reading or with the rising edge of
LOCK.
CNT6 (0x3B)
BIT 7 6 5 4 3 2 1 0
Field IDLE_ERR_C[7:0]
Reset 0x00
Access
Read Clears All
Type

IDLE_ERR_ Link C
C Reset after reading or with the rising edge of
LOCK.
CNT7 (0x3C)
BIT 7 6 5 4 3 2 1 0
Field IDLE_ERR_D[7:0]
Reset 0x00
Access
Read Clears All
Type

Number of idle word errors detected at Link D
IDLE_ERR_
7:0 Reset after reading or with the rising edge of 0xXX: Number of idle word errors detected
D
LOCK.
VID_PXL_CRC_ERR_VIDEOMASK_OEN (0x44)
BIT 7 6 5 4 3 2 1 0
VIDEO_MA VIDEO_MA VIDEO_MA VIDEO_MA VID_PXL_C VID_PXL_C VID_PXL_C VID_PXL_C
Field SKED_3_O SKED_2_O SKED_1_O SKED_0_O RC_ERR_O RC_ERR_O RC_ERR_O RC_ERR_O
EN EN EN EN EN_D EN_C EN_B EN_A
Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1
Access
Type

VIDEO_MAS 0x0: Video Masked 3 status disabled on ERRB pin
7 Enable Video Masked 3 status on ERRB
KED_3_OEN 0x1: Video Masked 3 status enabled on ERRB pin


0b0: Disable video pixel CRC error counter
VID_PXL_C
Video Pixel CRC Error Counter Interrupt interrupt output
RC_ERR_O 3
Output Enable 0b1: Enable video pixel CRC error counter
EN_D
interrupt output
VID_PXL_C
RC_ERR_O 2
EN_C
interrupt output
VID_PXL_C
RC_ERR_O 1
EN_B
interrupt output
VID_PXL_C
RC_ERR_O 0
EN_A
interrupt output
VID_PXL_CRC_VIDEOMASK_INT_FLAG (0x45)
BIT 7 6 5 4 3 2 1 0
VIDEO_MA VIDEO_MA VIDEO_MA VIDEO_MA
VID_PXL_C VID_PXL_C VID_PXL_C VID_PXL_C
Field SKED_3_F SKED_2_F SKED_1_F SKED_0_F
RC_ERR_D RC_ERR_C RC_ERR_B RC_ERR_A
LAG LAG LAG LAG
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access Read Read Read Read
Type Clears All Clears All Clears All Clears All

Sticky status value for Video Masked 3. Flag
will be set if any of Video Pipes 0-3 apart of
VIDEO_MAS 4WxH or Wx4H synchronous aggregation of 0x0: Video Pipe 3 video output has not been
KED_3_FLA 7 Controller 3 lose video lock. See masked
G video_masked registers in MIPI_TX_x 0x1: Video Pipe 3 video output has been masked
registers to determine which Video Pipe was
masked.
masked.
masked.


masked.
0b0: No video pixel CRC error counter interrupt
VID_PXL_C detected
3 Video Pixel CRC Error Counter Interrupt
RC_ERR_D 0b1: Video pixel CRC error counter interrupt
detected
VID_PXL_C detected
RC_ERR_C 0b1: Video pixel CRC error counter interrupt
detected
VID_PXL_C detected
RC_ERR_B 0b1: Video pixel CRC error counter interrupt
detected
VID_PXL_C detected
RC_ERR_A 0b1: Video pixel CRC error counter interrupt
detected
PWR_STATUS_OEN (0x48)
BIT 7 6 5 4 3 2 1 0
VDDBAD_I
Field RSVD – RSVD – – RSVD[1:0]
NT_OEN
Reset 0x1 0x1 – 0x0 – – 0x1
Access
Write, Read – – –
Type
BITFIELD BITS DESCRIPTION

VDDBAD_INT_OEN 7 Enable reporting of VDDBAD interrupt (VDDBAD_INT_FLAG) at ERRB pin
PWR_STATUS_OV_FLAG (0x49)
BIT 7 6 5 4 3 2 1 0
CMP_STAT CMP_STAT CMP_STAT CMP_STAT
VDDBAD_I
Field RSVD RSVD RSVD US_VDD_O US_VDD12 US_vddio_o US_VDD18
NT_FLAG
V _OV v _OV
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access Read
Type Clears All

VDDBAD_IN
7 Combined VDDBAD indicator
T_FLAG
0x0: VDD operating in normal range
CMP_STATU
3 VDD Comparator Status 0x1: VDD measured above overvoltage
S_VDD_OV
comparator threshold


CMP_STATU 0x0: VTERM operating in normal range
S_VDD12_O 2 0x1: VTERM measured above overvoltage
V comparator threshold
0x0: VDDIO operating in normal range
CMP_STATU
1 0x1: VDDIO measured above overvoltage
S_vddio_ov
comparator threshold
CMP_STATU 0x0: VDD18 operating in normal range
S_VDD18_O 0 0x1: VDD18 measured above overvoltage
V comparator threshold
VDDCMP_MASK (0x4A)
BIT 7 6 5 4 3 2 1 0
VDDCMP_I CMP_VTER
Field – VDDCMP_MASK[4:0]
NT_OEN M_MASK
Reset 0x1 – 0x1 0x07
Access
Write, Read – Write, Read Write, Read
Type

Enables reporting of VDD comparator interrupt (VDDCMP_INT_FLAG) at
VDDCMP_INT_OEN 7 ERRB pin.
See registers VDDCMP_MASK, CMP_STATUS, and VDDCMP_INT_FLAG
Enable VTERM voltage comparator status to drive VDDCMP_INT_FLAG error
flag and ERRB pin output.
See CMP_VTERM_STATUS register.
CMP_VTERM_MASK 5 Program to zero to mask status contribution to VDDCMP_INT_FLAG and
ERRB pin.
Program to one to enable status contribution to VDDCMP_INT_FLAG and
ERRB pin.
Select which voltage comparator status bits are masked from contributing to
the VDDCMP_INT_FLAG error flag and ERRB pin. See the CMP_STATUS
register field.
Programming a bit to zero will mask the corresponding bit in the

CMP_STATUS register field and prevent it from contributing to the
VDDCMP_INT_FLAG. Note that this does not mask the CMP_STATUS
VDDCMP_MASK 4:0 register field; it only masks the contribution to the VDDCMP_INT_FLAG and
ERRB pin output.
0 - Mask corresponding CMP_STATUS bit contribution to
VDDCMP_INT_FLAG and ERRB
1 - Enable corresponding CMP_STATUS bit contribution to
VDDCMP_INT_FLAG and ERRB
See the VDDCMP_INT_FLAG and VDDCMP_INT_OEN register fields.

VDDCMP_STATUS_FLAG (0x4B)
BIT 7 6 5 4 3 2 1 0
VDDCMP_I CMP_VTER
Field – – – – – –
NT_FLAG M_STATUS
Reset 0x0 – 0x0 – – – – –
Access Read
– Read Only – – – – –
Type Clears All

Combined VDD comparator output.
VDDCMP_INT_FLAG 7
See CMP_STATUS and VDDCMP_MASK registers.
Power manager VTERM comparator status. Latched low when switched
CMP_VTERM_STATUS 5 VTERM supply < 1V. Cleared when the CMP_STATUS word (register 0x12) is
read and the switched VTERM supply is > 1V.
DEV_REV (0x4C)
BIT 7 6 5 4 3 2 1 0
Field – – – – DEV_REV[3:0]
Reset – – – – 0x1
Access
– – – – Read Only
Type

DEV_REV 3:0 Device Revision 0x0: Revision number
EFUSE_CTRL (0x4D)
BIT 7 6 5 4 3 2 1 0
EFUSE_CR EFUSE_CR EFUSE_CR
Field – C_ERR_RS C_ERR_RS C_ERR_OE – – – –
T_OS T N
Reset – 0b0 0b0 0b1 – – – –
Access Write Clears
– Write, Read Write, Read – – – –
Type All, Read

Resets EFUSE CRC Error output.
EFUSE_CRC
Write 1 to reset the EFUSE CRC Error 0x0: normal operation
_ERR_RST_ 6
output. 0x1: Reset eFuse CRC Error Output (self-clearing)
OS
This register is self clearing.
Resets EFUSE CRC Error output.
Write 1 to reset the EFUSE CRC Error 0x0: clear eFuse CRC Error Output Reset
EFUSE_CRC
5 output. 0x1: Reset eFuse CRC Error Output (NOT self-
_ERR_RST
Write 0 to clear the reset request. clearing)
This register is not self clearing.
0x0: Efuse CRC error report not enabled at ERRB
EFUSE_CRC
4 Enable reporting efuse CRC at ERRB pin pin
_ERR_OEN
0x1: Efuse CRC error report enabled at ERRB pin

EFUSE_CRC_ERR (0x4E)
BIT 7 6 5 4 3 2 1 0
EFUSE_CR
Field – – – – – – –
C_ERR
Reset – – – – – – –
Access
– – – Read Only – – – –
Type

EFUSE_CRC 0x0: Efuse CRC error not reported at ERRB pin
4
_ERR 0x1: Efuse CRC error observed at ERRB pin
CFGH_VIDEO_CRC0 (0x60)
BIT 7 6 5 4 3 2 1 0
Field RX_CRC_EN_A_B[7:0]
Reset 0b0
Access
Write, Read
Type

Received Packet CRC Enable for Ports A and
B
0bXXXXXXX0: No CRC on received
packets—RX_CRC_EN_A_VIDEO_X
Each bit enables CRC for one pipe within a
0bXXXXXXX1: Received packets have CRC and
GMSL link as described below. Setting a
checking is enabled—RX_CRC_EN_A_VIDEO_X
given bit indicates that packets received at
0bXXXXXX0X: No CRC on received packets—
the corresponding port/pipe have appended
RX_CRC_EN_A_VIDEO_Y
CRC and CRC checking must be performed
0bXXXXXX1X: Received packets have CRC and
RX_CRC_EN at each packet.
7:0 checking is enabled— RX_CRC_EN_A_VIDEO_Y
_A_B
...
Bit 0: RX_CRC_EN_A_VIDEO_X
...
Bit 1: RX_CRC_EN_A_VIDEO_Y
...
Bit 2: RX_CRC_EN_A_VIDEO_Z
0b0XXXXXXX: No CRC on received packets—
Bit 3: RX_CRC_EN_A_VIDEO_U
RX_CRC_EN_B_VIDEO_U
Bit 4: RX_CRC_EN_B_VIDEO_X
0b1XXXXXXX: Received packets have CRC and
Bit 5: RX_CRC_EN_B_VIDEO_Y
checking is enabled— RX_CRC_EN_B_VIDEO_U
Bit 6: RX_CRC_EN_B_VIDEO_Z
Bit 7: RX_CRC_EN_B_VIDEO_U
CFGH_VIDEO_CRC1 (0x61)
BIT 7 6 5 4 3 2 1 0
Field RX_CRC_EN_C_D[7:0]
Reset 0b0
Access
Write, Read
Type


Received Packet CRC Enable for Ports C
and D
0bXXXXXXX0: No CRC on received
packets—RX_CRC_EN_C_VIDEO_X
Each bit enables CRC for one pipe within a
0bXXXXXXX1: Received packets have CRC and
GMSL link as described below. Setting a
checking is enabled—RX_CRC_EN_C_VIDEO_X
given bit indicates that packets received at
0bXXXXXX0X: No CRC on received packets—
the corresponding port/pipe have appended
RX_CRC_EN_C_VIDEO_Y
CRC and CRC checking must be performed
0bXXXXXX1X: Received packets have CRC and
RX_CRC_EN at each packet.
7:0 checking is enabled— RX_CRC_EN_C_VIDEO_Y
_C_D
...
Bit 0: RX_CRC_EN_C_VIDEO_X
...
Bit 1: RX_CRC_EN_C_VIDEO_Y
...
Bit 2: RX_CRC_EN_C_VIDEO_Z
0b0XXXXXXX: No CRC on received packets—
Bit 3: RX_CRC_EN_C_VIDEO_U
RX_CRC_EN_D_VIDEO_U
Bit 4: RX_CRC_EN_D_VIDEO_X
0b1XXXXXXX: Received packets have CRC and
Bit 5: RX_CRC_EN_D_VIDEO_Y
checking is enabled— RX_CRC_EN_D_VIDEO_U
Bit 6: RX_CRC_EN_D_VIDEO_Z
Bit 7: RX_CRC_EN_D_VIDEO_U
TR0 (0x70)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL[1:0] RSVD[1:0]
N N
Reset 0b1 0b1 0x3 0x0 0x0
Access
Write, Read Write, Read Write, Read
Type

When set, calculates and appends CRC to 0b0: Transmit CRC disabled
TX_CRC_EN 7
each packet transmitted from this port. 0b1: Transmit CRC enabled
When set, indicates that packets received at
0b0: Receive CRC disabled
RX_CRC_EN 6 this port have appended CRC. CRC checking
0b1: Receive CRC enabled
should be performed at each packet.
0b00: Low priority
Sets the priority for this channel's packet 0b01: Normal priority
PRIO_VAL 3:2
requests. 0b10: High priority
0b11: Urgent priority
TR1 (0x71)
BIT 7 6 5 4 3 2 1 0
Field BW_MULT[1:0] BW_VAL[5:0]
Reset 0x2 0x30
Access
Type

0b00: Multiply BW_VAL by 1
Channel bandwidth-allocation multiplication 0b01: Multiply BW_VAL by 4
BW_MULT 7:6
factor. 0b10: Multiply BW_VAL by 16


Channel bandwidth-allocation base.
BW_VAL 5:0 Fair bandwidth use ratio = BW_VAL x 0bXXXXXX: Channel base-bandwidth value
BW_MULT/10 as a percentage of total link
bandwidth.
TR2 (0x72)
BIT 7 6 5 4 3 2 1 0
Field – – – – – TX_SRC_ID[2:0]
Reset – – – – – 0x0
Access
– – – – – Write, Read
Type

Source identifier used in packets transmitted
TX_SRC_ID 2:0 from this port. Default value is set by CFG0 0bXXX: Source ID for packets from this channel
pin.
TR3 (0x73)
BIT 7 6 5 4 3 2 1 0
Field RX_SRC_SEL[7:0]
Reset 0xFF
Access
Write, Read
Type

0x00: No packets received
Receives packets from selected sources 0x01: Packets from source ID 0 received
0x02: Packets from source ID 1 received
Each bit indicates whether packets with that 0x03: Packets from source ID 0 and 1 received
RX_SRC_SE source ID should be received or not. For
7:0 0x04: Packets from source ID 2 received
L example, when RX_SRC_SEL = 00001001, ...
then packets with source ID equal to 0 and 3 ...
will be received. ...
0xFF: Packets from all source IDs received
TR0 (0x74)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_B[1:0] RSVD[1:0]
N_B N_B
Access
Type

TX_CRC_EN When set, calculates and appends CRC to 0b0: Transmit CRC disabled
7
_B each packet transmitted from this port. 0b1: Transmit CRC enabled


RX_CRC_EN 0b0: Receive CRC disabled
6 this port have appended CRC. CRC checking
_B 0b1: Receive CRC enabled
0b00: Low priority
PRIO_VAL_ Sets the priority for this channel's packet 0b01: Normal priority
3:2
B requests 0b10: High priority
TR1 (0x75)
BIT 7 6 5 4 3 2 1 0
Field BW_MULT_B[1:0] BW_VAL_B[5:0]
Reset 0x2 0x30
Access
Type

0b00: Multiply BW_VAL_B by 1
BW_MULT_ Channel bandwidth-allocation multiplication 0b01: Multiply BW_VAL_B by 4
7:6
B factor. 0b10: Multiply BW_VAL_B by 16
Channel bandwidth-allocation base.
BW_VAL_B 5:0 Fair bandwidth use ratio = BW_VAL_B x 0bXXXXXX: Channel base-bandwidth value
BW_MULT_B/10 as a percentage of total link
bandwidth
TR2 (0x76)
BIT 7 6 5 4 3 2 1 0
Field – – – – – TX_SRC_ID_B[2:0]
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
2:0 from this port. Default value is set by CFG0 0bXXX: Source ID for packets from this channel
B
pin.
TR3 (0x77)
BIT 7 6 5 4 3 2 1 0
Field RX_SRC_SEL_B[7:0]
Reset 0xFF
Access
Write, Read
Type


L_B example, when RX_SRC_SEL_B = ...
00001001, then packets with source ID equal ...
to 0 and 3 will be received. ...
TR0 (0x78)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_C[1:0] RSVD[1:0]
N_C N_C
Access
Type

7
_C each packet transmitted from this port. 0b1: Transmit CRC enabled
_C 0b1: Receive CRC enabled
0b00: Low priority
3:2
C requests. 0b10: High priority
TR1 (0x79)
BIT 7 6 5 4 3 2 1 0
Field BW_MULT_C[1:0] BW_VAL_C[5:0]
Reset 0x2 0x30
Access
Type

0b00: Multiply BW_VAL_C by 1
BW_MULT_ Channel bandwidth-allocation multiplication 0b01: Multiply BW_VAL_C by 4
7:6
C factor 0b10: Multiply BW_VAL_C by 16
Channel bandwidth-allocation base. Fair
bandwidth use ratio = BW_VAL_C x
BW_VAL_C 5:0 0bXXXXXX: Channel base-bandwidth value
BW_MULT_C/10 as a percentage of total link
bandwidth

TR2 (0x7A)
BIT 7 6 5 4 3 2 1 0
Field – – – – – TX_SRC_ID_C[2:0]
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
C
pin.
TR3 (0x7B)
BIT 7 6 5 4 3 2 1 0
Field RX_SRC_SEL_C[7:0]
Reset 0xFF
Access
Write, Read
Type

L_C example, when RX_SRC_SEL_C = ...
TR0 (0x7C)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_D[1:0] RSVD[1:0]
N_D N_D
Access
Type

7
_D each packet transmitted from this port 0b1: Transmit CRC enabled
_D 0b1: Receive CRC enabled
0b00: Low priority
3:2
D requests. 0b10: High priority

TR1 (0x7D)
BIT 7 6 5 4 3 2 1 0
Field BW_MULT_D[1:0] BW_VAL_D[5:0]
Reset 0x2 0x30
Access
Type

0b00: Multiply BW_VAL_D by 1
BW_MULT_ Channel bandwidth-allocation multiplication 0b01: Multiply BW_VAL_D by 4
7:6
D factor 0b10: Multiply BW_VAL_D by 16
bandwidth use ratio = BW_VAL_D x
BW_VAL_D 5:0 0bXXXXXX: Channel base-bandwidth value
BW_MULT_D/10 as a percentage of total link
bandwidth
TR2 (0x7E)
BIT 7 6 5 4 3 2 1 0
Field – – – – – TX_SRC_ID_D[2:0]
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
D
pin.
TR3 (0x7F)
BIT 7 6 5 4 3 2 1 0
Field RX_SRC_SEL_D[7:0]
Reset 0xFF
Access
Write, Read
Type

Receives packets from selected sources. 0x01: Packets from source ID 0 received
L_D example, when RX_SRC_SEL_D = ...

TR0 (0xA0)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL[1:0] RSVD[1:0]
N N
Access
Type

When set, calculates and appends CRC to 0b0: Transmit CRC disabled
TX_CRC_EN 7
each packet transmitted from this port. 0b1: Transmit CRC enabled
0b0: Receive CRC disabled
0b1: Receive CRC enabled
0b00: Low priority
PRIO_VAL 3:2
requests. 0b10: High priority
TR1 (0xA1)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

BW_MULT 7:6
factor 0b10: Multiply BW_VAL by 16
BW_VAL 5:0 bandwidth use ratio = BW_VAL x BW_MULT/ 0bXXXXXX: Channel base-bandwidth value
10 as a percentage of total link bandwidth
TR3 (0xA3)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

pin.

TR4 (0xA4)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

then packets with source ID equal to 0 and 3 ...
will be received. ...
ARQ1 (0xA6)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
Field – MAX_RT[2:0] RSVD RSVD
RR_OEN EN
Reset – 0x7 0x0 0x0 0b1 0b0
Access
– Write, Read Write, Read Write, Read
Type

Maximum retransmit limit. ARQ will stop
MAX_RT 6:4 retransmission after reaching the limit for a 0bXXX: Maximum retransmit limit
single packet.
Enables reporting of ARQ maximum 0b0: ARQ maximum retransmit limit errors
MAX_RT_ER retransmission limit errors reporting at ERRB pin disabled
1
R_OEN (MAX_RT_ERR—0xA7) for this channel at 0b1: ARQ maximum retransmit limit errors
ERRB pin reporting at ERRB pin enabled
Enables reporting of ARQ retransmission 0b0: ARQ retransmission count reporting at ERRB
RT_CNT_OE event for this channel at ERRB pin. When pin disabled
0
N enabled, ERRB is asserted when RT_CNT 0b1: ARQ retransmission count reporting at ERRB
(0xA7) of this channel is greater than 0. pin enabled
ARQ2 (0xA7)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT[6:0]
RR
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

Reached maximum retransmit limit
MAX_RT_ER 0b0: Maximum retransmission limit not reached
7 (MAX_RT—0xA6) for one packet in this
R 0b1: Maximum retransmission limit reached
channel


0bXXXXXXX: Count of retransmissions for this
RT_CNT 6:0 Total retransmission count in this channel
channel
TR0 (0xA8)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_B[1:0] RSVD[1:0]
N_B N_B
Access
Type

7
_B each packet transmitted from this port. 0b1: Transmit CRC enabled
_B 0b1: Receive CRC enabled
0b00: Low priority
3:2
TR1 (0xA9)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
B factor. 0b10: Multiply BW_VAL_B by 16
bandwidth use ratio = BW_VAL_B x
BW_VAL_B 5:0 0bXXXXXX: Channel base-bandwidth value
bandwidth
TR3 (0xAB)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type


TX_SRC_ID_
B
pin.
TR4 (0xAC)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

Each bit indicates whether packets with that 0x02: Packets from source ID 1 received
RX_SRC_SE source ID should be received or not. For 0x03: Packets from source ID 0 and 1 received
7:0
L_B example, when RX_SRC_SEL_B = 0x04: Packets from source ID 2 received
ARQ1 (0xAE)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
Field – MAX_RT_B[2:0] RSVD RSVD
RR_OEN_B EN_B
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_B 6:4 retransmission after reaching the limit for a 0bXXX: Maximum retransmit limit
single packet.
1
R_OEN_B (MAX_RT_ERR_B—0xAF) for this channel at 0b1: ARQ maximum retransmit limit errors
0
N_B enabled, ERRB is asserted when RT_CNT_B 0b1: ARQ retransmission count reporting at ERRB
(0xAF) of this channel is greater than 0. pin enabled
ARQ2 (0xAF)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_B[6:0]
RR_B
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All


7 (MAX_RT_B—0xAE) for one packet in this
R_B 0b1: Maximum retransmission limit reached
channel.
RT_CNT_B 6:0 Total retransmission count in this channel.
channel
TR0 (0xB0)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_C[1:0] RSVD[1:0]
N_C N_C
Access
Type

7
_C each packet transmitted from this port. 0b1: Transmit CRC enabled
_C 0b1: Receive CRC enabled
0b00: Low priority
3:2
C requests. 0b10: High priority
TR1 (0xB1)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
C factor. 0b10: Multiply BW_VAL_C by 16
bandwidth
TR3 (0xB3)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type


TX_SRC_ID_
C
pin.
TR4 (0xB4)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

ARQ1 (0xB6)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
Field – MAX_RT_C[2:0] RSVD RSVD
RR_OEN_C EN_C
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_C 6:4 retransmission after reaching the limit for a 0bXXX: Maximum retransmit limit
single packet.
1
R_OEN_C (MAX_RT_ERR_C—0xB7) for this channel at 0b1: ARQ maximum retransmit limit errors
0
N_C enabled, ERRB is asserted when RT_CNT_C 0b1: ARQ retransmission count reporting at ERRB
(0xB7) of this channel is greater than 0. pin enabled

ARQ2 (0xB7)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_C[6:0]
RR_C
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_C—0xB6) for one packet in this
R_C 0b1: Maximum retransmission limit reached
channel.
RT_CNT_C 6:0 Total retransmission count in this channel.
channel
TR0 (0xB8)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_D[1:0] RSVD[1:0]
N_D N_D
Access
Type

7
_D each packet transmitted from this port. 0b1: Transmit CRC enabled
_D 0b1: Receive CRC enabled
0b00: Low priority
3:2
D requests. 0b10: High priority
TR1 (0xB9)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
D factor. 0b10: Multiply BW_VAL_D by 16
bandwidth

TR3 (0xBB)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
D
pin.
TR4 (0xBC)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

ARQ1 (0xBE)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
Field – MAX_RT_D[2:0] RSVD RSVD
RR_OEN_D EN_D
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_D 6:4 retransmission after reaching the limit for a 0bXXX: Maximum retransmit limit
single packet.
1
R_OEN_D (MAX_RT_ERR_D—0xBF) for this channel at 0b1: ARQ maximum retransmit limit errors
0
N_D enabled, ERRB is asserted when RT_CNT_D 0b1: ARQ retransmission count reporting at ERRB
(0xBF) of this channel is greater than 0. pin enabled

ARQ2 (0xBF)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_D[6:0]
RR_D
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_D—0xBE) for one packet in this
R_D 0b1: Maximum retransmission limit reached
channel.
RT_CNT_D 6:0 Total retransmission count in this channel.
channel
I2C_7 (0xC7)
BIT 7 6 5 4 3 2 1 0
I2C_REGSL I2C_REGSL
Field V_1_TIMED I2C_INTREG_SLV_1_TO[2:0] V_0_TIMED I2C_INTREG_SLV_0_TO[2:0]
_OUT _OUT
Access
Read Only Write, Read Read Only Write, Read
Type

0b0: Internal I2C-to-register slave for Port 1 has
I2C_REGSL Internal I2C-to-register slave for Port 1 has
not timed out
V_1_TIMED_ 7 timed out while waiting for the master or the
OUT internal register access FSM.
timed out
I2C-to-Internal Register Slave 1 Timeout 0b000: 16μs
Setting 0b001: 1ms
0b010: 2ms
I2C_INTREG Internal register I2C Slave 1 times out after 0b011: 4ms
6:4
_SLV_1_TO the configured duration if it does not receive 0b100: 8ms
any response from the external master or 0b101: 16ms
internal register FSM. This slave serves I2C 0b110: 32ms
Port 1. 0b111: Disabled
I2C_REGSL Internal I2C-to-register slave for Port 0 has
not timed out
V_0_TIMED_ 3 timed out while waiting for the master or the
OUT internal register access FSM.
timed out
I2C-to-Internal Register Slave 0 Timeout 0b000: 16μs
Setting 0b001: 1ms
0b010: 2ms
I2C_INTREG Internal register I2C Slave 0 times out after 0b011: 4ms
2:0
_SLV_0_TO the configured duration if it does not receive 0b100: 8ms
any response from the external master or 0b101: 16ms
internal register FSM. This slave serves I2C 0b110: 32ms
Port 0. 0b111: Disabled

REG0 (0xE0)
BIT 7 6 5 4 3 2 1 0
Field – – – – PU_LF3 PU_LF2 PU_LF1 PU_LF0
Reset – – – – 0x0 0x0 0x0 0x0
Access
Type

0b0: Line fault monitor 3 disabled
PU_LF3 3 Power up Line Fault monitor 3
0b1: Line fault monitor 3 enabled
REG1 (0xE1)
BIT 7 6 5 4 3 2 1 0
Field – LF_1[2:0] – LF_0[2:0]
Reset – 0x2 – 0x2
Access
– Read Only – Read Only
Type

0b000: Short to battery
0b001: Short to GND
Line Fault status of wire connected to LMN1
LF_1 6:4 0b010: Normal Operation
pin
0b011: Line Open
0b1XX: Line-to-line short
0b001: Short to GND
pin
0b011: Line Open
REG2 (0xE2)
BIT 7 6 5 4 3 2 1 0
Field – LF_3[2:0] – LF_2[2:0]
Access
Type

0b001: Short to GND
pin
0b011: Line Open


0b001: Short to GND
pin
0b011: Line Open
REG5 (0xE5)
BIT 7 6 5 4 3 2 1 0
Field – – – – LFLT_INT_FLAG[3:0]
Reset – – – – 0x0
Access
– – – – Read Clears All
Type

0x0: Gets set to 1 when (!mask_lf0 && pu_lf0 &&
(LF_0 != 3'b010)). Read clears
LFLT_INT_F (LF_1 != 3'b010)). Read clears
3:0 Line-Fault Error Flag Indicators
LAG 0x2: Gets set to 1 when (!mask_lf2 && pu_lf2 &&
REG6 (0xE6)
BIT 7 6 5 4 3 2 1 0
Field – – – – MASK_LF3 MASK_LF2 MASK_LF1 MASK_LF0
Reset – – – – 0x0 0x0 0x0 0x0
Access
Type

0b0: Line fault monitor 3 interrupt enabled
MASK_LF3 3 Mask Line Fault monitor 3 Interrupt
0b1: Line fault monitor 3 interrupt masked
VIDEO_PIPE_SEL_0 (0xF0)
BIT 7 6 5 4 3 2 1 0
Field VIDEO_PIPE_SEL_1[3:0] VIDEO_PIPE_SEL_0[3:0]
Reset 0x6 0x2
Access
Type


Bits [7:6]
0b00: GMSL2 PHY A
0b01: GMSL2 PHY B
Video Pipe 1 Input Selection Control
0b10: GMSL2 PHY C
VIDEO_PIPE 0b11: GMSL2 PHY D
7:4 Bits [7:6]: GMSL2 Phy Link selection for Pipe
_SEL_1 Bits [5:4]
1
0b00: Pipe X
Bits [5:4]: Input Pipe selection for Pipe 1
0b01: Pipe Y
0b10: Pipe Z
0b11: Pipe U
Bits [3:2]
0b00: GMSL2 PHY A
0b01: GMSL2 PHY B
Video Pipe 0 Input Selection Control
0b10: GMSL2 PHY C
_SEL_0 Bits [1:0]
0
0b00: Pipe X
0b01: Pipe Y
0b10: Pipe Z
0b11: Pipe U
VIDEO_PIPE_SEL_1 (0xF1)
BIT 7 6 5 4 3 2 1 0
Field VIDEO_PIPE_SEL_3[3:0] VIDEO_PIPE_SEL_2[3:0]
Reset 0xe 0xa
Access
Type

Bits [7:6]
0b00: GMSL2 PHY A
0b01: GMSL2 PHY B
Video Pipe 3 Selection
0b10: GMSL2 PHY C
_SEL_3 Bits [5:4]
3
0b00: Pipe X
0b01: Pipe Y
0b10: Pipe Z
0b11: Pipe U
Bits [3:2]
0b00: GMSL2 PHY A
0b01: GMSL2 PHY B
Video Pipe 2 Selection
0b10: GMSL2 PHY C
_SEL_2 Bits [1:0]
2
0b00: Pipe X
0b01: Pipe Y
0b10: Pipe Z
0b11: Pipe U

VIDEO_PIPE_EN (0xF4)
BIT 7 6 5 4 3 2 1 0
STREAM_S
Field – – – VIDEO_PIPE_EN[3:0]
EL_ALL
Reset – – – 0x1 0xF
Access
– – – Write, Read Write, Read
Type

When set to a 1, overrides
VIDEO_PIPE_SEL_*[1:0] select bits such
STREAM_SE that all X,Y,Z, and U streams are selected, 0x0: Legacy (MAX96712) mode
4
L_ALL not just one. When cleared to 0, 0x1: Select all streams (X,Y,Z and/or U)
VIDEO_PIPE_SEL_0[1:0] will select which
stream to pass to pipe 0.
0bXXXXXXX0: Disable Pipe 0
0bXXXXXXX1: Enable Pipe 0
0bXXXXXX0X: Disable Pipe 1
VIDEO_PIPE 0bXXXXXX1X: Enable Pipe 1
3:0 Video Pipe Enable Register
_EN 0bXXXXX0XX: Disable Pipe 2
0bXXXXX1XX: Enable Pipe 2
0bXXXX0XXX: Disable Pipe 3
0bXXXX1XXX: Enable Pipe 3
HVD_GPIO_CTRL_EN (0xFA)
BIT 7 6 5 4 3 2 1 0
Field – – – – HVD_OUT_EN[3:0]
Reset – – – – 0x0
Access
– – – – Write, Read
Type


0x0: Disable all HVD GPIO
0x1: Enable only HVD GPIO on MFP1, all others
disabled
disabled
0x3: Enable HVD GPIO on MFP1 and MFP3, all
others disabled
disabled
0x5: Enable HVD GPIO on MFP1 and MFP7, all
This register field controls which (if any) of others disabled
the VSYNC/HSYNC/DE GPIO are enabled. 0x6: Enable HVD GPIO on MFP3 and MFP7, all
Desired output signals are selected using the others disabled
HVD_HS_SEL*, HVD_VS_SEL*, 0x7: Enable HVD GPIO on MFP1, MFP3, and
HVD_OUT_E HVD_DE_SEL*, and HVD_OUT_SEL MFP7, all others disabled
3:0
N registers 0x8: Enable only HVD GPIO on MFP8, all others
When Bit 0 = 1 Enables HDV GPIO on MFP1 disabled
When Bit 1 = 1 Enables HDV GPIO on MFP3 0x9: Enable HVD GPIO on MFP1 and MFP8
When Bit 2 = 1 Enables HDV GPIO on MFP7 0xA: Enable HVD GPIO on MFP3 and MFP8, all
When Bit 3 = 1 Enables HDV GPIO on MFP8 others disabled
0xB: Enable HVD GPIO on MFP1, MFP3 and
MFP8, all others disabled
0xC: Enable HVD GPIO on MFP7 and MFP8, all
others disabled
0xD: Enable HVD GPIO on MFP1, MFP7 and
0xE: Enable HVD GPIO on MFP3, MFP7, and
0xF: Enable HVD GPIO on MFP1, MFP3, MFP7,
and MFP8, all others disabled
HVD_GPIO_CTRL_HS (0xFB)
BIT 7 6 5 4 3 2 1 0
Field HVD_HS_SEL3[1:0] HVD_HS_SEL2[1:0] HVD_HS_SEL1[1:0] HVD_HS_SEL0[1:0]
Reset 0b00 0b00 0b00 0b00
Access
Type

Selects which Video Pipe HS Sync to Output on MFP8
Note: Must also program HVD_OUT_EN and HVD_OUT_SEL
2'b00 - HS Sync for Video Pipe 0
HVD_HS_SEL3 7:6
HVD_HS_SEL2 5:4


HVD_HS_SEL1 3:2
HVD_HS_SEL0 1:0
HVD_GPIO_CTRL_VS (0xFC)
BIT 7 6 5 4 3 2 1 0
Field HVD_VS_SEL3[1:0] HVD_VS_SEL2[1:0] HVD_VS_SEL1[1:0] HVD_VS_SEL0[1:0]
Reset 0b00 0b00 0b00 0b00
Access
Type

Selects which Video Pipe VS Sync to Output on MFP8
2'b00 - VS Sync for Video Pipe 0
HVD_VS_SEL3 7:6
HVD_VS_SEL2 5:4
HVD_VS_SEL1 3:2
HVD_VS_SEL0 1:0

HVD_GPIO_CTRL_DE (0xFD)
BIT 7 6 5 4 3 2 1 0
Field HVD_DE_SEL3[1:0] HVD_DE_SEL2[1:0] HVD_DE_SEL1[1:0] HVD_DE_SEL0[1:0]
Reset 0b00 0b00 0b00 0b00
Access
Type

Selects which Video Pipe DE to Output on MFP8
2'b00 - DE Sync for Video Pipe 0
HVD_DE_SEL3 7:6
HVD_DE_SEL2 5:4
HVD_DE_SEL1 3:2
HVD_DE_SEL0 1:0
HVD_GPIO_CTRL_SEL (0xFE)
BIT 7 6 5 4 3 2 1 0
Field HVD_OUT_SEL3[1:0] HVD_OUT_SEL2[1:0] HVD_OUT_SEL1[1:0] HVD_OUT_SEL0[1:0]
Reset 0b00 0b00 0b00 0b00
Access
Type

Selects Signal type, VSYNC, HSYNC, or DE to be output on MFP8. Using the
HVD_HS_SEL*, HVD_VS_SEL*, and HVD_DE_SEL* registers, users can
select one of any of the video pipe HSYNC, VSYNC, or DE signals to be
output on MFP8.
HVD_OUT_SEL3 7:6
2'b00 - Output HSYNC selected by HVD_HS_SEL3 on MFP8
2'b01 - Output VSYNC selected by HVD_VS_SEL3 on MFP8
2'b10 - Output DE selected by HVD_DE_SEL3 on MFP8
2'b11 - Output TX Start selected by HVD_ST_SEL3 on MFP8


output on MFP7.
HVD_OUT_SEL2 5:4
output on MFP3.
HVD_OUT_SEL1 3:2
output on MFP1.
HVD_OUT_SEL0 1:0
HVD_GPIO_CTRL_ST (0xFF)
BIT 7 6 5 4 3 2 1 0
Field HVD_ST_SEL3[1:0] HVD_ST_SEL2[1:0] HVD_ST_SEL1[1:0] HVD_ST_SEL0[1:0]
Reset 0b00 0b00 0b00 0b00
Access
Type

Selects which Video Pipe TX Start to Output on MFP8
2'b00 - TX Start for Video Pipe 0
HVD_ST_SEL3 7:6
HVD_ST_SEL2 5:4
HVD_ST_SEL1 3:2


HVD_ST_SEL0 1:0
VIDEO_RX0 (0x100, 0x112, 0x124, 0x136)
BIT 7 6 5 4 3 2 1 0
SEQ_MISS LINE_CRC_ DIS_PKT_D
Field LCRC_ERR RSVD RSVD RSVD RSVD
_EN EN ET
Reset 0x0 0b0 0b1 0b1 0b0 0b0 0b1 0b0
Access Read
Type Clears All

Video Line CRC Error Flag
0b0: No video line CRC error detected
LCRC_ERR 7
Asserted when a video line CRC error is 0b1: Video line CRC error detected
detected
0b0: Disable Video Sequence Miss Detection
SEQ_MISS_
4 Video sequence miss detection enable 0b1: Video Sequence Miss Detection Enabled
EN
(Default)
LINE_CRC_ 0b0: Disable video line CRC
1 Video Line CRC Enable
EN 0b1: Enable video line CRC
Disable Packet Detector
DIS_PKT_D If the video is restarted with a different BPP 0b0: Enable packet detect (default)
0
ET when the packet detector is disabled, toggle 0b1: Disable packet detect
this register or the video receive enable
register to make sure the video link restarts.
VIDEO_RX6 (0x106, 0x118, 0x12A, 0x13C)
BIT 7 6 5 4 3 2 1 0
VID_SEQ_ LIM_HEAR
Field RSVD[2:0] – RSVD RSVD
ERR_OEN T
Reset 0x0 0b1 0b0 – 0b1 0b0
Access
Write, Read Write, Read –
Type

Enables reflection of Video Sequencing Error
VID_SEQ_E
4 onto the ERRB pin. 0x0: Disabled
RR_OEN
Refer to the VID_SEQ_ERR register field. 0x1: Enabled


If enabled, there is a configurable timeout
using VRX_PKT_DET.TIMEOUT_x (default is
10ms) to detect loss of video lock. If disabled,
there is a 100us timeout to detect loss of
video lock. If Heartbeat is disabled
(LIM_HEART = 1 on Serializer), set
0x0
LIM_HEART 3 VRX_PKT_DET.TIMEOUT_x from 1 to
0x1: See Description
127ms, as per requirement.
Use together with SEQ_MISS_EN and
DIS_PKT_DET registers in deserializer.
Embedded data should use the Heartbeat to
ensure loss of video lock timeout does not
occur.
VIDEO_RX8 (0x108, 0x11A, 0x12C, 0x13E)
BIT 7 6 5 4 3 2 1 0
VID_PKT_D VID_SEQ_
Field RSVD VID_LOCK RSVD[3:0]
ET ERR
Reset 0b0 0b0 0b0 0b0 0x2
Access Read
Read Only Read Only
Type Clears All

0b0: Video pipeline not locked
VID_LOCK 6 Video pipeline locked
0b1: Video pipeline locked
VID_PKT_D Video Rx sufficient packet throughput 0b0: Insufficient packet throughput
5
ET detection. 0b1: Sufficient packet throughput
VID_SEQ_E 0b0: No video Rx sequence error detected
4 Video Rx sequence error detection.
RR 0b1: Video Rx sequence error detected
LIM_HEART_TIMEOUT_0 (0x160)
BIT 7 6 5 4 3 2 1 0
Field – LIM_HEART_TIMEOUT_0[6:0]
Reset – 0xA
Access
– Write, Read
Type

Video Pipe 0 Packet Detection Timeout used when LIM_HEART=1. Timeout
can be configured from 1 to 127 in milliseconds.
LIM_HEART_TIMEOUT
6:0
_0 bits [6:0]: Timeout count (in ms)
Note: Value of 0 will also default to 1ms.

BIT 7 6 5 4 3 2 1 0
Reset – 0xA
Access
– Write, Read
Type

LIM_HEART_TIMEOUT
6:0
BIT 7 6 5 4 3 2 1 0
Reset – 0xA
Access
– Write, Read
Type

LIM_HEART_TIMEOUT
6:0
BIT 7 6 5 4 3 2 1 0
Reset – 0xA
Access
– Write, Read
Type

LIM_HEART_TIMEOUT
6:0

CROSS_HS (0x1D8, 0x1F8, 0x218, 0x238)
BIT 7 6 5 4 3 2 1 0
CROSS_HS CROSS_HS
Field – CROSS_HS[4:0]
_I _F
Reset – 0x0 0x0 0x18
Access
Type

CROSS_HS_ 0b0: Do not invert bit
6 Inverts CrossX
I 0b1: Invert bit
CROSS_HS_ 0b0: Do not force bit to zero
5 Forces CrossX to 0 before inversion
F 0b1: Force bit to zero
CROSS_HS 4:0 Maps selected internal signal to Cross X 0bXXXXX: Incoming bit position
CROSS_VS (0x1D9, 0x1F9, 0x219, 0x239)
BIT 7 6 5 4 3 2 1 0
CROSS_VS CROSS_VS
Field – CROSS_VS[4:0]
_I _F
Reset – 0x0 0x0 0x19
Access
Type

CROSS_VS_ 0b0: Do not invert bit
6 Inverts CrossX
I 0b1: Invert bit
CROSS_VS_ 0b0: Do not force bit to zero
CROSS_VS 4:0 Maps selected internal signal to Cross X 0bXXXXX: Incoming bit position
CROSS_DE (0x1DA, 0x1FA, 0x21A, 0x23A)
BIT 7 6 5 4 3 2 1 0
CROSS_DE CROSS_DE
Field – CROSS_DE[4:0]
_I _F
Reset – 0x0 0x0 0x1A
Access
Type

CROSS_DE_ 0b0: Do not invert bit
6 Inverts CrossX
I 0b1: Invert bit
CROSS_DE_ 0b0: Do not force bit to zero
CROSS_DE 4:0 Maps selected internal signal to Cross X 0bXXXXX: Incoming bit position

PRBS_ERR (0x1DB, 0x1FB, 0x21B, 0x23B)
BIT 7 6 5 4 3 2 1 0
Field VPRBS_ERR[7:0]
Reset 0x00
Access
Read Clears All
Type

0xXX: Number of video PRBS errors since last
VPRBS_ERR 7:0 Video PRBS error counter, clears on read
read
VPRBS (0x1DC, 0x1FC, 0x21C, 0x23C)
BIT 7 6 5 4 3 2 1 0
VPRBS24_
PATGEN_C VPRBS_CH VPRBS_FAI VPRBS7_G VPRBS9_G DIS_GLITC VIDEO_LO
Field GENCHK_E
LK_SRC ECK L ENCHK_EN ENCHK_EN H_FILT CK
N
Reset 0x1 0b0 0b0 0b0 0b0 0b0 0x0 0b0
Access
Write, Read Read Only Read Only Write, Read Write, Read Write, Read Write, Read Read Only
Type

Pattern generator clock source for video
PATGEN_CL PRBS7, PRBS9, PRBS24, checkerboard, 0b0: 150MHz
7
K_SRC and gradient patterns. 0 = 150MHz, 1 = 0b1: 375MHz (default)
375MHz (default).
Indicates when PRBS checker has
VPRBS_CHE 0: PRBS Checker has not started checking
6 synchronized and is checking received PRBS
CK 1: PRBS Checker started checking
data.
Indicates when PRBS checker could not
0: PRBS Checker synchronized and test passed
synchronize and PRBS test failed.
VPRBS_FAIL 5 1: PRBS Checker could not synchronize and test
failed
VPRBS24_G 0b0: Video PRBS24 generator/checker disabled

4 Enables video PRBS24 generator/checker
ENCHK_EN 0b1: Video PRBS24 generator/checker enabled
VPRBS7_GE 0b0: Video PRBS7 generator/checker disabled
NCHK_EN 0b1: Video PRBS7 generator/checker enabled
VPRBS9_GE 0b0: Video PRBS9 generator/checker disabled
NCHK_EN 0b1: Video PRBS9 generator/checker enabled
DIS_GLITCH 0b0: Glitch filter enabled
1 Disables HS, VS, and DE glitch filtering
_FILT 0b1: Glitch filter disabled
VIDEO_LOC Video channel is locked and outputting valid 0b0: Video channel is not locked
0
K video data 0b1: Video channel is locked
POLARITY_A_L (0x2E0)
BIT 7 6 5 4 3 2 1 0
Field POLARITY_A_L[7:0]
Reset 0x0
Access
Write, Read
Type


POLARITY_ Packet GPIO[7:0] RX Aggregation Polarity/ 0x0: Acitve Low (True State, default)
7:0
A_L Inversion Function 0x1: Active High (Invert State)
POLARITY_B_L (0x2E1)
BIT 7 6 5 4 3 2 1 0
Field POLARITY_B_L[7:0]
Reset 0x0
Access
Write, Read
Type

7:0
B_L Inversion Function 0x1: Active High (Invert State)
POLARITY_C_L (0x2E2)
BIT 7 6 5 4 3 2 1 0
Field POLARITY_C_L[7:0]
Reset 0x0
Access
Write, Read
Type

7:0
C_L Inversion Function 0x1: Active High (Invert State)
POLARITY_D_L (0x2E3)
BIT 7 6 5 4 3 2 1 0
Field POLARITY_D_L[7:0]
Reset 0x0
Access
Write, Read
Type

7:0
D_L Inversion Function 0x1: Active High (Invert State)
POLARITY_AB_H (0x2E4)
BIT 7 6 5 4 3 2 1 0
Field – POLARITY_B_H[2:0] – POLARITY_A_H[2:0]
Access
– Write, Read – Write, Read
Type

6:4
B_H Inversion Function 0x1: Active High (Invert State)


2:0
A_H Inversion Function 0x1: Active High (Invert State)
POLARITY_CD_H (0x2E5)
BIT 7 6 5 4 3 2 1 0
Field – POLARITY_D_H[2:0] – POLARITY_C_H[2:0]
Access
Type

6:4
D_H Inversion Function 0x1: Active High (Invert State)
2:0
C_H Inversion Function 0x1: Active High (Invert State)
ENABLE_A_L (0x2E6)
BIT 7 6 5 4 3 2 1 0
Field ENABLE_A_L[7:0]
Reset 0x0
Access
Write, Read
Type

0x0: Disabled (GPIO RX data bit set high to
ENABLE_A_ aggregator or AND function, default)
7:0 Packet GPIO[7:0] RX Aggregation Enable
L 0x1: Enabled (GPIO RX data bit passed to
aggregator or AND function)
ENABLE_B_L (0x2E7)
BIT 7 6 5 4 3 2 1 0
Field ENABLE_B_L[7:0]
Reset 0x0
Access
Write, Read
Type

ENABLE_B_ aggregator or AND function, default)

ENABLE_C_L (0x2E8)
BIT 7 6 5 4 3 2 1 0
Field ENABLE_C_L[7:0]
Reset 0x0
Access
Write, Read
Type

ENABLE_C_ aggregator or AND function, default)
ENABLE_D_L (0x2E9)
BIT 7 6 5 4 3 2 1 0
Field ENABLE_D_L[7:0]
Reset 0x0
Access
Write, Read
Type

ENABLE_D_ aggregator or AND function, default)
ENABLE_AB_H (0x2EA)
BIT 7 6 5 4 3 2 1 0
Field – ENABLE_B_H[2:0] – ENABLE_A_H[2:0]
Access
Type

ENABLE_B_ aggregator or AND function, default)
H 0x1: Enabled (GPIO RX data bit passed to
ENABLE_A_ aggregator or AND function, default)

ENABLE_CD_H (0x2EB)
BIT 7 6 5 4 3 2 1 0
Field – ENABLE_D_H[2:0] – ENABLE_C_H[2:0]
Access
Type

ENABLE_D_ aggregator or AND function, default)
ENABLE_C_ aggregator or AND function, default)
READ_A_L (0x2EC)
BIT 7 6 5 4 3 2 1 0
Field READ_A_L[7:0]
Reset 0x0
Access
Read Only
Type

READ_A_L 7:0 Packet GPIO[7:0] RX Aggregation Read State
READ_B_L (0x2ED)
BIT 7 6 5 4 3 2 1 0
Field READ_B_L[7:0]
Reset 0x0
Access
Read Only
Type

READ_B_L 7:0 Packet GPIO[7:0] RX Aggregation Read State
READ_C_L (0x2EE)
BIT 7 6 5 4 3 2 1 0
Field READ_C_L[7:0]
Reset 0x0
Access
Read Only
Type

READ_C_L 7:0 Packet GPIO[7:0] RX Aggregation Read State

READ_D_L (0x2EF)
BIT 7 6 5 4 3 2 1 0
Field READ_D_L[7:0]
Reset 0x0
Access
Read Only
Type

READ_D_L 7:0 Packet GPIO[7:0] RX Aggregation Read State
READ_AB_H (0x2F0)
BIT 7 6 5 4 3 2 1 0
Field – READ_B_H[2:0] – READ_A_H[2:0]
Access
Type

READ_B_H 6:4 Packet GPIO[10:8] RX Aggregation Read State
READ_A_H 2:0 Packet GPIO[10:8] RX Aggregation Read State
READ_CD_H (0x2F1)
BIT 7 6 5 4 3 2 1 0
Field – READ_D_H[2:0] – READ_C_H[2:0]
Access
Type

READ_D_H 6:4 Packet GPIO[10:8] RX Aggregation Read State
READ_C_H 2:0 Packet GPIO[10:8] RX Aggregation Read State
OUTPUT (0x2F2)
BIT 7 6 5 4 3 2 1 0
OUTPUT_I OUTPUT_E DESTINATI READ_FLA
Field – – – –
NVERT NABLE ON G
Reset – – – – 0x0 0x0 0x0 0x0
Access
– – – – Write, Read Write, Read Write, Read Read Only
Type

OUTPUT_IN 0x0: Aggregation Output True
3 Packet GPIO RX Aggregation Output Invert
VERT 0x1: Aggregation Output Inverted
OUTPUT_EN Packet GPIO RX Aggregation Output Enable 0x0: Disabled (default)
2
ABLE to ERRB Pin 0x1: Enabled
DESTINATIO Packet GPIO RX Aggregation Output 0x0: Disabled to MFP6
1
N destination or output enable to MFP6 0x1: Enabled to MFP6


Packet GPIO RX Aggregation Output, Active 0x0: Aggregation Error
READ_FLAG 0
Low 0x1: Aggregation No Error
GPIO_A (0x300)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_RX_ GPIO_TX_ GPIO_OUT
Field RES_CFG RSVD GPIO_OUT GPIO_IN
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Write, Read Write, Read Write, Read Read Only Write, Read Write, Read Write, Read
Type

0b0: 40kΩ
RES_CFG 7 Resistor pullup/pulldown strength
0b1: 1MΩ
TX_COMP_E 0b0: Jitter compensation disabled
5 Jitter minimization compensation enable
N 0b1: Jitter compensation enabled
GPIO pin output drive value when 0b0: This GPIO pin output is driven to 0
GPIO_OUT 4
GPIO_RX_EN = 0 0b1: This GPIO pin output is driven to 1
0b0: This GPIO pin value is 0
GPIO_IN 3 GPIO pin input level
0b0: This GPIO source disabled for GMSL2
GPIO_RX_E reception
2 GPIO out source control
N 0b1: This GPIO source enabled for GMSL2
reception
GPIO_TX_E transmission
1 GPIO Tx source control
transmission
GPIO_OUT_ 0b0: Output driver enabled
0 Enable/disable GPIO output driver
DIS 0b1: Output driver disabled
GPIO_B (0x301)
BIT 7 6 5 4 3 2 1 0
Field PULL_UPDN_SEL[1:0] OUT_TYPE GPIO_TX_ID[4:0]
Reset 0x2 0b1 0x00
Access
Type

0b00: None
PULL_UPDN 0b01: Pullup
7:6 Buffer pullup/pulldown configuration
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
OUT_TYPE 5 Driver type selection
0b1: Push-pull
GPIO_TX_ID 4:0 GPIO ID for pin while transmitting 0bXXXXX: This GPIO transmit ID

GPIO_C (0x302)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
Field RSVD GPIO_RX_ID[4:0]
CFG VED
Reset 0x0 0b1 0b0 0x00
Access
Type

Override non-GPIO port function IO setting.
When set, RES_CFG (0x300) and 0b0: Non-GPIO function determines IO type when
OVR_RES_C PULL_UPDN_SEL (0x301) are effective alternate function is selected
7
FG when pin is configured as non-GPIO. When 0b1: RES_CFG and PULL_UPDN_SEL determine
cleared, non-GPIO pin function determines IO IO type for non-GPIO configuration
type.
GPIO_RECV
6 Received GPIO value
ED
GPIO_RX_ID 4:0 GPIO ID for pin while receiving 0bXXXXX: This GPIO receive ID
GPIO_A (0x303)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission

GPIO_B (0x304)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x01
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x305)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

7
type.
GPIO_RECV
ED
GPIO_A (0x306)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ


GPIO_OUT 4
GPIO_RX_E reception
reception
transmission
GPIO_B (0x307)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x02
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x308)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

7
type.
GPIO_RECV
ED

GPIO_A (0x309)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission
GPIO_B (0x30A)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x03
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull

GPIO_C (0x30B)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

OVR_RES_C PULL_UPDN_SEL (0x30A) are effective alternate function is selected
7
type.
GPIO_RECV
ED
GPIO_A (0x30C)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission

GPIO_B (0x30D)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x04
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x30E)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

When set, RES_CFG (0x30C) and 0b0: Non-GPIO function determines IO type when
OVR_RES_C PULL_UPDN_SEL (0x30D) are effective alternate function is selected
7
type.
GPIO_RECV
ED
GPIO_A (0x310)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ


GPIO_OUT 4
GPIO_RX_E reception
reception
transmission
GPIO_B (0x311)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x05
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x312)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

7
type.
GPIO_RECV
ED

GPIO_A (0x313)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission
GPIO_B (0x314)
BIT 7 6 5 4 3 2 1 0
Reset 0x0 0b1 0x06
Access
Type

0b00: None
Buffer pullup/pulldown configuration
7:6 by default MFP6 does not have a pull down
_SEL 0b10: Pulldown
selection like the other MFPs.
0b11: Reserved
0b0: Open-drain
0b1: Push-pull

GPIO_C (0x315)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

7
type.
GPIO_RECV
ED
GPIO_A (0x316)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission

GPIO_B (0x317)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x07
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x318)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

7
type.
GPIO_RECV
ED
GPIO_A (0x319)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ


GPIO_OUT 4
GPIO_RX_E reception
reception
transmission
GPIO_B (0x31A)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x08
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x31B)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

OVR_RES_C PULL_UPDN_SEL (0x31A) are effective alternate function is selected
7
type.
GPIO_RECV
ED

GPIO_A (0x31C)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission
GPIO_B (0x31D)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x09
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull

GPIO_C (0x31E)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Access
Type

When set, RES_CFG (0x31C) and 0b0: Non-GPIO function determines IO type when
OVR_RES_C PULL_UPDN_SEL (0x31D) are effective alternate function is selected
7
type.
GPIO_RECV
ED
GPIO_A (0x320)
BIT 7 6 5 4 3 2 1 0
EN EN EN _DIS
Reset 0b1 0x0 0x0 0b0 0b0 0b0 0b0 0b1
Access
Type

0b0: 40kΩ
0b1: 1MΩ
GPIO_OUT 4
GPIO_RX_E reception
reception
transmission

GPIO_B (0x321)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0b1 0x0A
Access
Type

0b00: None
_SEL 0b10: Pulldown
0b11: Reserved
0b0: Open-drain
0b1: Push-pull
GPIO_C (0x322)
BIT 7 6 5 4 3 2 1 0
OVR_RES_ GPIO_REC
CFG VED
Reset 0x0 0b1 0b0 0x0A
Access
Type

7
type.
GPIO_RECV
ED
GPIO_B (0x337)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
Field RSVD GPIO_TX_ID_B[4:0]
EN_B EN_B
Reset 0x0 0x0 0b0 0x00
Access
Type

N_B 0b1: Jitter compensation enabled


N_B 0b1: This GPIO source enabled for GMSL2
transmission
GPIO_TX_ID
4:0 GPIO ID for pin while transmitting 0bXXXXX: This GPIO transmit ID
_B
GPIO_C (0x338)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
Field – GPIO_RX_ID_B[4:0]
VED_B EN_B
Reset – 0b1 0b0 0x00
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
4:0 GPIO ID for pin while receiving 0bXXXXX: This GPIO receive ID
_B
GPIO_B (0x33A)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B

GPIO_C (0x33B)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x33D)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B
GPIO_C (0x33E)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B


GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x341)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B
GPIO_C (0x342)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B

GPIO_B (0x344)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B
GPIO_C (0x345)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x347)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type



transmission
GPIO_TX_ID
_B
GPIO_C (0x348)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x34A)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B

GPIO_C (0x34B)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x34D)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B
GPIO_C (0x34E)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B


GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x351)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B
GPIO_C (0x352)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B

GPIO_B (0x354)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Access
Type

transmission
GPIO_TX_ID
_B
GPIO_C (0x355)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x357)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_B EN_B
Reset 0x0 0x0 0b0 0x0a
Access
Type



transmission
GPIO_TX_ID
_B
GPIO_C (0x358)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_B EN_B
Reset – 0b1 0b0 0x0a
Access
Type

GPIO_RECV
ED_B
GPIO_RX_E reception
reception
GPIO_RX_ID
_B
GPIO_B (0x36D)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
Field RSVD GPIO_TX_ID_C[4:0]
EN_C EN_C
Access
Type

N_C 0b1: Jitter compensation enabled
N_C 0b1: This GPIO source enabled for GMSL2
transmission
GPIO_TX_ID
_C

GPIO_C (0x36E)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
Field – GPIO_RX_ID_C[4:0]
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x371)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C
GPIO_C (0x372)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C


GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x374)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C
GPIO_C (0x375)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C

GPIO_B (0x377)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C
GPIO_C (0x378)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x37A)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type



transmission
GPIO_TX_ID
_C
GPIO_C (0x37B)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x37D)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C

GPIO_C (0x37E)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x381)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C
GPIO_C (0x382)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C


GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x384)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C
GPIO_C (0x385)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C

GPIO_B (0x387)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C
GPIO_C (0x388)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x38A)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type



transmission
GPIO_TX_ID
_C
GPIO_C (0x38B)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x38D)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_C EN_C
Access
Type

transmission
GPIO_TX_ID
_C

GPIO_C (0x38E)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_C EN_C
Access
Type

GPIO_RECV
ED_C
GPIO_RX_E reception
reception
GPIO_RX_ID
_C
GPIO_B (0x3A4)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
Field RSVD GPIO_TX_ID_D[4:0]
EN_D EN_D
Access
Type

N_D 0b1: Jitter compensation enabled
N_D 0b1: This GPIO source enabled for GMSL2
transmission
GPIO_TX_ID
_D
GPIO_C (0x3A5)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
Field – GPIO_RX_ID_D[4:0]
VED_D EN_D
Access
Type

GPIO_RECV
ED_D


GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3A7)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D
GPIO_C (0x3A8)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D

GPIO_B (0x3AA)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D
GPIO_C (0x3AB)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3AD)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type



transmission
GPIO_TX_ID
_D
GPIO_C (0x3AE)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3B1)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D

GPIO_C (0x3B2)
BIT 7 6 5 4 3 2 1 0
GPIO_RX_
Field – RSVD GPIO_RX_ID_D[4:0]
EN_D
Access
– Write, Read Write, Read
Type

GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3B4)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D
GPIO_C (0x3B5)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception


GPIO_RX_ID
_D
GPIO_B (0x3B7)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D
GPIO_C (0x3B8)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3BA)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type


transmission
GPIO_TX_ID
_D
GPIO_C (0x3BB)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3BD)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D

GPIO_C (0x3BE)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3C1)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D
GPIO_C (0x3C2)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D


GPIO_RX_E reception
reception
GPIO_RX_ID
_D
GPIO_B (0x3C4)
BIT 7 6 5 4 3 2 1 0
TX_COMP_ GPIO_TX_
EN_D EN_D
Access
Type

transmission
GPIO_TX_ID
_D
GPIO_C (0x3C5)
BIT 7 6 5 4 3 2 1 0
GPIO_REC GPIO_RX_
VED_D EN_D
Access
Type

GPIO_RECV
ED_D
GPIO_RX_E reception
reception
GPIO_RX_ID
_D

BACKTOP1 (0x400)
BIT 7 6 5 4 3 2 1 0
CSIPLL3_L CSIPLL2_L CSIPLL1_L CSIPLL0_L
OCK OCK OCK OCK
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b1
Access
Type

CSIPLL3_LO 0b0: PLL not locked
7 CSIPLL1 lock
CK 0b1: PLL locked
CSIPLL2_LO 0b0: CSI2 0 PLL not locked
6 CSIPLL0 lock
CK 0b1: CSI2 0 PLL locked
CSIPLL1_LO 0b0: PLL not locked
5 CSIPLL1 lock
CK 0b1: PLL locked
CSIPLL0_LO 0b0: CSI2 0 PLL not locked
4 CSIPLL0 lock
CK 0b1: CSI2 0 PLL locked
BACKTOP2 (0x401)
BIT 7 6 5 4 3 2 1 0
Field VS_VC0_L[7:0]
Reset 0x00
Access
Write, Read
Type

0x0: Default behavior
0xXXXXXXX1: Virtual Channel 0 enabled
0xXXXXXX1X: Virtual Channel 1 enabled
Override Frame Start-End short packet VC
0xXXXXX1XX: Virtual Channel 2 enabled
enable.
VS_VC0_L 7:0 0xXXXX1XXX: Virtual Channel 3 enabled
Each bit corresponds to a Virtual Channel
0xXXX1XXXX: Virtual Channel 4 enabled
number enable
0xXX1XXXXX: Virtual Channel 5 enabled
0xX1XXXXXX: Virtual Channel 6 enabled
0x1XXXXXXX: Virtual Channel 7 enabled
BACKTOP3 (0x402)
BIT 7 6 5 4 3 2 1 0
Field VS_VC0_H[7:0]
Reset 0x00
Access
Write, Read
Type


enable.
VS_VC0_H 7:0 0xXXXX1XXX: Virtual Channel 11 enabled
number enable
BACKTOP4 (0x403)
BIT 7 6 5 4 3 2 1 0
Field VS_VC1_L[7:0]
Reset 0x00
Access
Write, Read
Type

enable.
number enable
BACKTOP5 (0x404)
BIT 7 6 5 4 3 2 1 0
Field VS_VC1_H[7:0]
Reset 0x00
Access
Write, Read
Type

enable.
number enable

BACKTOP6 (0x405)
BIT 7 6 5 4 3 2 1 0
Field VS_VC2_L[7:0]
Reset 0x00
Access
Write, Read
Type

enable.
number enable
BACKTOP7 (0x406)
BIT 7 6 5 4 3 2 1 0
Field VS_VC2_H[7:0]
Reset 0x00
Access
Write, Read
Type

enable.
number enable
BACKTOP8 (0x407)
BIT 7 6 5 4 3 2 1 0
Field VS_VC3_L[7:0]
Reset 0x00
Access
Write, Read
Type


enable.
number enable
BACKTOP9 (0x408)
BIT 7 6 5 4 3 2 1 0
Field VS_VC3_H[7:0]
Reset 0x00
Access
Write, Read
Type

enable.
number enable
BACKTOP10 (0x409)
BIT 7 6 5 4 3 2 1 0
Field DE_SEL3 DE_SEL2 DE_SEL1 DE_SEL0 RSVD RSVD RSVD RSVD
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type

Use HS for creation of long packets instead 0x0: Use DE for creation of long packets
DE_SEL3 7
of DE 0x1: Use HS for creation of long packets
DE_SEL2 6
DE_SEL1 5
DE_SEL0 4

BACKTOP11 (0x40A)
BIT 7 6 5 4 3 2 1 0
cmd_overflo cmd_overflo cmd_overflo cmd_overflo
Field LMO_3 LMO_2 LMO_1 LMO_0
w3 w2 w1 w0
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type

Pipe 3 command FIFO overflow.
cmd_overflo Cleared on read. 0b0: No overflow
7
w3 See the CMD_OVFL_3_ERRB_OEN register 0b1: Overflow
to enable output of this status on ERRB pin.
6
5
4
Pipe 3 line memory overflow sticky register. 0b0: No overflow
LMO_3 3
Cleared on read. 0b1: Overflow
LMO_2 2
LMO_1 1
Pipe 0 line memory overflow sticky register.
Cleared on read. 0b0: No overflow
LMO_0 0
See LMO_0_ERRB_EN to enable output of 0b1: Overflow
this status to the ERRB pin
BACKTOP12 (0x40B)
BIT 7 6 5 4 3 2 1 0
CSI_OUT_
Field soft_bpp_0[4:0] – RSVD
EN
Reset 0x00 – 0b1 0b0
Access
Write, Read – Write, Read
Type


0x8: Data types = 0x2A, 0x10-12, 0x31-37
0xA: Data types = 0x2B
0xC: Data types = 0x2C
0xE: Data types = 0x2D
Pipe 0 BPP software-override:
soft_bpp_0 7:3 0x10: Data types = 0x22, 0x1E, 0x2E
Software-override video data BPP.
0x12: Data types = 0x23
0x14: Data types = 0x1F, 0x2F
0x18: Data types = 0x24, 0x30
All other values: Reserved
CSI_OUT_E 0b0: CSI output disabled
1 Enables MIPI CSI output
N 0x1: CSI output enabled
BACKTOP13 (0x40C)
BIT 7 6 5 4 3 2 1 0
Field soft_vc_1[3:0] soft_vc_0[3:0]
Reset 0x0 0x0
Access
Type

soft_vc_1 7:4 Pipe 1 VC software-override 0xX: Software-defined virtual channel for Pipe 1
BACKTOP14 (0x40D)
BIT 7 6 5 4 3 2 1 0
Field soft_vc_3[3:0] soft_vc_2[3:0]
Reset 0x0 0x0
Access
Type

BACKTOP15 (0x40E)
BIT 7 6 5 4 3 2 1 0
Field soft_dt_1_h[1:0] soft_dt_0[5:0]
Reset 0x0 0x00
Access
Type


0x10: GENERIC8
0x11: GENERIC8
0x12: EMBEDDED
0x1E: YUV422 8-bit
0x1F: YUV422 10-bit
0x22: RGB565
0x23: RGB666
0x24: RGB888
0x2A: RAW8
0x2B: RAW10
Pipe 1 DT (high bits) software-override
0x2C: RAW12
soft_dt_1_h 7:6 bitfield. Works together with soft_dt_1_l in
0x2D: RAW14
BACKTOP16 register (0x40F).
0x2E: RAW16
0x2F: RAW20
0x30: YUV422 12-bit
0x31: UDP8
0x32: UDP8
0x33: UDP8
0x34: UDP8
0x35: UDP8
0x36: UDP8
0x37: UDP8
0x10: GENERIC8
0x11: GENERIC8
0x12: EMBEDDED
0x1E: YUV422 8-bit
0x1F: YUV422 10-bit
0x22: RGB565
0x23: RGB666
0x24: RGB888
0x2A: RAW8
0x2B: RAW10
0x2C: RAW12
soft_dt_0 5:0 Pipe 0 DT software-override.
0x2D: RAW14
0x2E: RAW16
0x2F: RAW20
0x30: YUV422 12-bit
0x31: UDP8
0x32: UDP8
0x33: UDP8
0x34: UDP8
0x35: UDP8
0x36: UDP8
0x37: UDP8
BACKTOP16 (0x40F)
BIT 7 6 5 4 3 2 1 0
Field soft_dt_2_h[3:0] soft_dt_1_l[3:0]
Reset 0x0 0x0
Access
Type


0x10: GENERIC8
0x11: GENERIC8
0x12: EMBEDDED
0x1E: YUV422 8-bit
0x1F: YUV422 10-bit
0x22: RGB565
0x23: RGB666
0x24: RGB888
0x2A: RAW8
0x2B: RAW10
Pipe 2 DT (high bits) software-override
0x2C: RAW12
soft_dt_2_h 7:4 bitfield. Works together with soft_dt_2_l in
0x2D: RAW14
BACKTOP17 register (0x410).
0x2E: RAW16
0x2F: RAW20
0x30: YUV422 12-bit
0x31: UDP8
0x32: UDP8
0x33: UDP8
0x34: UDP8
0x35: UDP8
0x36: UDP8
0x37: UDP8
0x10: GENERIC8
0x11: GENERIC8
0x12: EMBEDDED
0x1E: YUV422 8-bit
0x1F: YUV422 10-bit
0x22: RGB565
0x23: RGB666
0x24: RGB888
0x2A: RAW8
0x2B: RAW10
Pipe 1 DT (low bits) software-override bitfield.
0x2C: RAW12
soft_dt_1_l 3:0 Works together with soft_dt_1_h in
0x2D: RAW14
BACKTOP16 register (0x40E).
0x2E: RAW16
0x2F: RAW20
0x30: YUV422 12-bit
0x31: UDP8
0x32: UDP8
0x33: UDP8
0x34: UDP8
0x35: UDP8
0x36: UDP8
0x37: UDP8
BACKTOP17 (0x410)
BIT 7 6 5 4 3 2 1 0
Field soft_dt_3[5:0] soft_dt_2_l[1:0]
Reset 0x00 0x0
Access
Type


0x10: GENERIC8
0x11: GENERIC8
0x12: EMBEDDED
0x1E: YUV422 8-bit
0x1F: YUV422 10-bit
0x22: RGB565
0x23: RGB666
0x24: RGB888
0x2A: RAW8
0x2B: RAW10
0x2C: RAW12
soft_dt_3 7:2 Pipe 3 DT software-override
0x2D: RAW14
0x2E: RAW16
0x2F: RAW20
0x30: YUV422 12-bit
0x31: UDP8
0x32: UDP8
0x33: UDP8
0x34: UDP8
0x35: UDP8
0x36: UDP8
0x37: UDP8
0x10: GENERIC8
0x11: GENERIC8
0x12: EMBEDDED
0x1E: YUV422 8-bit
0x1F: YUV422 10-bit
0x22: RGB565
0x23: RGB666
0x24: RGB888
0x2A: RAW8
0x2B: RAW10
Pipe 2 DT (low bits) software-override. Works
0x2C: RAW12
soft_dt_2_l 1:0 together with soft_dt_2_h in BACKTOP16
0x2D: RAW14
register (0x40F).
0x2E: RAW16
0x2F: RAW20
0x30: YUV422 12-bit
0x31: UDP8
0x32: UDP8
0x33: UDP8
0x34: UDP8
0x35: UDP8
0x36: UDP8
0x37: UDP8
BACKTOP18 (0x411)
BIT 7 6 5 4 3 2 1 0
Field soft_bpp_2_h[2:0] soft_bpp_1[4:0]
Reset 0x0 0x00
Access
Type


Pipe 2 BPP (high bits) software-override
bitfield:
soft_bpp_2_h 7:5 0bXX: High bits of software-defined BPP for Pipe 2
Works together with soft_bpp_2_l in
0x8: Data types = 0x2A, 0x10-12, 0x31-37
Pipe 1 BPP software-override bitfield: 0xE: Data types = 0x2D
soft_bpp_1 4:0
Software override video data BPP. 0x10: Data types = 0x22, 0x1E, 0x2E
BACKTOP19 (0x412)
BIT 7 6 5 4 3 2 1 0
Field – soft_bpp_3[4:0] soft_bpp_2_l[1:0]
Reset – 0x00 0x0
Access
Type

0x8: Data types = 0x2A, 0x10-12, 0x31-37
0xE: Data types = 0x2D
Pipe 3 BPP software-override bitfield:
soft_bpp_3 6:2 0x10: Data types = 0x22, 0x1E, 0x2E
Software override video data BPP.
0bXX: New BPP for Pipe 4
Pipe 2 BPP software-override register:
Software override video data BPP (low bits).
soft_bpp_2_l 1:0 0bXX: Low bits of software-defined BPP for Pipe 2
Works together with soft_bpp_2_h in
BACKTOP20 (0x413)
BIT 7 6 5 4 3 2 1 0
Field phy0_csi_tx_dpll_fb_fraction_in_l[7:0]
Reset 0x00
Access
Write, Read
Type

phy0_csi_tx_
Low byte of software-override value for CSI
dpll_fb_fracti 7:0 0xXX: PHY frequency fine tuning override low byte
PHY0 frequency fine tuning
on_in_l

BACKTOP21 (0x414)
BIT 7 6 5 4 3 2 1 0
Field bpp8dbl3 bpp8dbl2 bpp8dbl1 bpp8dbl0 phy0_csi_tx_dpll_fb_fraction_in_h[3:0]
Access
Write, Read Write, Read Write, Read Write, Read Write, Read
Type

Pipe 3 BPP8 double-pixel register: 0b0: Disable process BPP = 8 as 16-bit color
bpp8dbl3 7
BPP = 8 processed as 16-bit color 0b1: Enable process BPP = 8 as 16-bit color
bpp8dbl2 6
bpp8dbl1 5
bpp8dbl0 4
phy0_csi_tx_
High nibble of software-override value for CSI 0xX: PHY0 frequency fine tuning override high
dpll_fb_fracti 3:0
PHY0 frequency fine tuning nibble
on_in_h
BACKTOP22 (0x415)
BIT 7 6 5 4 3 2 1 0
phy0_csi_tx
override_bp override_bp _dpll_fb_fra
Field phy0_csi_tx_dpll_predef_freq[4:0]
p_vc_dt_1 p_vc_dt_0 ction_predef
_en
Reset 0b0 0b0 0b1 0x0F
Access
Type

Pipe 1 software-override enable bitfield
Note:
• Control registers, override_bpp_vc_dt_#
and/or OVERRIDE_VC_# have priority over
the OVERRIDE_VC_BITS_2_AND_3
override_bpp 0b0: Disable
7 register.
_vc_dt_1 0b1: Enable
• RRB_PKT_VC_OVRD_EN has priority over
override_bpp_vc_dt_#, OVERRIDE_VC _#,
and/or OVERRIDE_VC_BITS_2_AND_3 for
errb_pkts


Note:
override_bpp the OVERRIDE_VC_BITS_2_AND_3 0b0: Disable
6
_vc_dt_0 register. 0b1: Enable
• ERRB_PKT_VC_OVRD_EN has priority

over override_bpp_vc_dt_#, OVERRIDE_VC
_#, and/or OVERRIDE_VC_BITS_2_AND_3
for errb_pkts
phy0_csi_tx_ 0b0: Enable software override for frequency fine
dpll_fb_fracti MIPI PHY0 software-override disable for tuning
5
on_predef_e frequency fine tuning 0b1: Disable software override for frequency fine
n tuning
DPHY data rate/lane
MIPI PHY0 DPLL frequency bitfield. 0x02: 200MHz DPLL, 200Mbps/lane
Set DPLL frequency on multiple of 100MHz. ...
phy0_csi_tx_ 0x19: 2500MHz DPLL, 2.5Gbps/lane
dpll_predef_f 4:0 DPHY: Clock frequency is half, data rate is
req equivalent bps/lane. CPHY data rate/trio
0x02: 200MHz DPLL, 456Mbps/lane
CPHY: 2.28bits/symbol. ...
0x19: 2500MHz DPLL, 5.7Gbps/lane
BACKTOP23 (0x416)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

phy1_csi_tx_
Low byte of software-override value for CSI 0xXX: PHY1 frequency fine tuning override low
dpll_fb_fracti 7:0
PHY1 frequency fine tuning byte
on_in_l
BACKTOP24 (0x417)
BIT 7 6 5 4 3 2 1 0
bpp8dbl3_m bpp8dbl2_m bpp8dbl1_m bpp8dbl0_m
Field phy1_csi_tx_dpll_fb_fraction_in_h[3:0]
ode ode ode ode
Access
Type

bpp8dbl3_mo Pipe 3 BPP8 double-pixel mode register: 0b0: Alternative bit mapping not selected
7
de 8-bit alternate bit mapping to rams 0b1: Alternative bit mapping selected
6


5
4
phy1_csi_tx_
dpll_fb_fracti 3:0
on_in_h
BACKTOP25 (0x418)
BIT 7 6 5 4 3 2 1 0
phy1_csi_tx
override_bp override_bp _dpll_fb_fra
Field phy1_csi_tx_dpll_predef_freq[4:0]
p_vc_dt_3 p_vc_dt_2 ction_predef
_en
Access
Type

Note:
7

for errb_pkts
Note:
6

for errb_pkts
5
n tuning


DPHY data rate/lane
MIPI PHY1 DPLL frequency bitfield: 0x02: 200MHz DPLL, 200Mbps/lane
dpll_predef_f 4:0 DPHY: Clock frequency is half; data rate is
0x02: 200MHz DPLL,456Mbps/lane
BACKTOP26 (0x419)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

phy2_csi_tx_
dpll_fb_fracti 7:0
on_in_l
BACKTOP27 (0x41A)
BIT 7 6 5 4 3 2 1 0
yuv_8_10_ yuv_8_10_ yuv_8_10_ yuv_8_10_
Field phy2_csi_tx_dpll_fb_fraction_in_h[3:0]
mux_mode3 mux_mode2 mux_mode1 mux_mode0
Reset 0x0 0x0 0x0 0x0 0x0
Access
Type

yuv_8_10_m 0b0: Disable 8-/10-bit mux
7 Pipe 3 YUV422 8-bit and 10-bit mux
ux_mode3 0b1: Enable 8-/10-bit mux
phy2_csi_tx_
dpll_fb_fracti 3:0
on_in_h

BACKTOP28 (0x41B)
BIT 7 6 5 4 3 2 1 0
phy2_csi_tx
_dpll_fb_fra
Field – – phy2_csi_tx_dpll_predef_freq[4:0]
ction_predef
_en
Reset – – 0b1 0x0F
Access
– – Write, Read Write, Read
Type

5
n tuning
DPHY data rate/lane
BACKTOP29 (0x41C)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

phy3_csi_tx_
dpll_fb_fracti 7:0
on_in_l
BACKTOP30 (0x41D)
BIT 7 6 5 4 3 2 1 0
bpp10dbl3_
Field – – bpp10dbl3 phy3_csi_tx_dpll_fb_fraction_in_h[3:0]
mode
Reset – – 0b0 0b0 0x0
Access
– – Write, Read Write, Read Write, Read
Type

bpp10dbl3_m Pipe 3 BPP10 double-pixel mode register: 0b0: Alternative bit mapping not selected
5
ode 10-bit alternate bit mapping to rams 0b1: Alternative bit mapping selected
bpp10dbl3 4


phy3_csi_tx_
dpll_fb_fracti 3:0
on_in_h
BACKTOP31 (0x41E)
BIT 7 6 5 4 3 2 1 0
phy3_csi_tx
bpp10dbl2_ _dpll_fb_fra
Field bpp10dbl2 phy3_csi_tx_dpll_predef_freq[4:0]
mode ction_predef
_en
Access
Type

7
bpp10dbl2 6
5
n tuning
DPHY data rate/lane
BACKTOP32 (0x41F)
BIT 7 6 5 4 3 2 1 0
bpp10dbl1_ bpp10dbl0_
Field bpp10dbl1 bpp10dbl0 bpp12dbl3 bpp12dbl2 bpp12dbl1 bpp12dbl0
mode mode
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type

7
bpp10dbl1 6
5
bpp10dbl0 4


bpp12dbl3 3
bpp12dbl2 2
bpp12dbl1 1
BPP = 12 processed as 24-bit color 0b1: Enable process BP P= 12 as 24-bit color
bpp12dbl0 0
BACKTOP1 (0x420)
BIT 7 6 5 4 3 2 1 0
Field ERRB_PKT_EN[3:0] – – RSVD[1:0]
Reset 0b0000 – – 0x01
Access
Write, Read – –
Type

0bxxx0: Disable ERRB packet out to video pipe 0
0bxxx1: Enable ERRB packet out to video pipe 0
0bxx0x: Disable ERRB packet out to video pipe 1
ERRB_PKT_ 0bxx1x: Enable ERRB packet out to video pipe 1
7:4 Enable the ERRB packet to each video pipe.
EN 0bx0xx: Disable ERRB packet out to video pipe 2
0bx1xx: Enable ERRB packet out to video pipe 2
0b0xxx: Disable ERRB packet out to video pipe 3
0b1xxx: Enable ERRB packet out to video pipe 3
BACKTOP2 (0x421)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT_Insert_Mode_ ERRB_PKT_Insert_Mode_ ERRB_PKT_Insert_Mode_ ERRB_PKT_Insert_Mode_
Field
4[1:0] 3[1:0] 2[1:0] 1[1:0]
Reset 0b01 0b01 0b01 0b01
Access
Type

Specify where the ERRB packet is inserted.
0b00: No insertion
Specify if ERRB_PKT comes out before or
0b01: ERRB packet inserted before the Frame
ERRB_PKT_ after the "Frame Start/End short packet".
Start/End Packet
Insert_Mode 7:6
0b10: ERRB packet inserted after the Frame Start/
_4 Used in conjuction with
End Packet
ERRB_PKT_EDGE_SEL which is used to
0b11: Reserved
select Frame Start or Frame End.
0b00: No insertion
Start/End Packet
Insert_Mode 5:4
End Packet
0b11: Reserved


0b00: No insertion
Start/End Packet
Insert_Mode 3:2
End Packet
0b11: Reserved
0b00: No insertion
Start/End Packet
Insert_Mode 1:0
End Packet
0b11: Reserved
BACKTOP3 (0x422)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT ERRB_PKT ERRB_PKT ERRB_PKT
Field – _EDGE_SE – _EDGE_SE – _EDGE_SE – _EDGE_SE
L_4 L_3 L_2 L_1
Reset – – – –
Access
– Write, Read – Write, Read – Write, Read – Write, Read
Type

ERRB_PKT_
0 = ERRB_PKT comes out at Frame End 0x0: 0 = ERRB_PKT comes out at Frame End
EDGE_SEL_ 6
1 = ERRB_PKT comes out at Frame Start 0x1: 1 = ERRB_PKT comes out at Frame Start
4
ERRB_PKT_
EDGE_SEL_ 4
3
ERRB_PKT_
EDGE_SEL_ 2
2
ERRB_PKT_
EDGE_SEL_ 0
1
BACKTOP4 (0x423)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
Field _DBL_MOD – ERRB_PKT_DT_1[5:0]
E_1
Reset 0x0 – 0x12
Access
Type


0 = Double mode disabled
1 = Double mode enabled
For pixel mode only. Double mode allows the
ERRB packet to be packed more efficiently
ERRB_PKT_
into memory. Must be used for data types 0x0: Double mode disabled
DBL_MODE_ 7
with bpp > 16 and pixels per line count over 0x1: Double mode enabled
1
2700.
Note: Double mode can only be used if the
word count of the incoming video is an even
number.
ERRB_PKT_ Specify the data type for ERRB packet, 0x12
5:0 0xxX: Data type of ERRB packet
DT_1 or 0x31-37
BACKTOP5 (0x424)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
E_2
Reset 0x0 – 0x12
Access
Type

ERRB_PKT_
DBL_MODE_ 7
2
2700.
number.
DT_2 or 0x31-37
BACKTOP6 (0x425)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
E_3
Reset 0x0 – 0x12
Access
Type


ERRB_PKT_
DBL_MODE_ 7
3
2700.
number.
DT_3 or 0x31-37
BACKTOP7 (0x426)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
E_4
Reset 0x0 – 0x12
Access
Type

ERRB_PKT_
DBL_MODE_ 7
4
2700.
number.
DT_4 or 0x31-37
BACKTOP8 (0x427)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
Field _VC_OVRD – – ERRB_PKT_VC_OVRD_1[4:0]
_EN_1
Reset 0x0 – – 0xF
Access
Type


0 = Pick random VC from video source in
pipe 1 as the VC for ERRB packets
1 = Use VC specified in
ERRB_PKT_VC_OVRD_1 register as the VC
for ERRB packets
0x0: Pick random VC from video source in pipe 0
Notes:
ERRB_PKT_ as the VC for ERRB packets
VC_OVRD_E 7 0x1: Use VC specified in
N_1 ERRB_PKT_VC_OVRD_0 register as the VC for
ERRB packets
register.

over override_bpp_vc_dt_#,OVERRIDE_VC
for errb_pkts
Specify Virtual Channel number for ERRB
ERRB_PKT_
4:0 Packet when ERRB_PKT_VC_OVRD_EN is 0xX: Virtual channel number of ERRB packet
VC_OVRD_1
set
BACKTOP9 (0x428)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
_EN_2
Access
Type

for ERRB packets
Notes:
ERRB packets
register.

for errb_pkts
ERRB_PKT_
VC_OVRD_2
set

BACKTOP10 (0x429)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
_EN_3
Access
Type

for ERRB packets
Notes:
ERRB packets
register.

for errb_pkts
ERRB_PKT_
VC_OVRD_3
set
BACKTOP11 (0x42A)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT
_EN_4
Access
Type


for ERRB packets
Notes:
ERRB packets
register.

for errb_pkts
ERRB_PKT_
VC_OVRD_4
set
BACKTOP12 (0x42B)
BIT 7 6 5 4 3 2 1 0
Field – – – ERRB_PKT_VC_1[4:0]
Reset – – – 0x0
Access
– – – Read Only
Type

ERRB_PKT_ Virtual Channel number used by ERRB
4:0 0xX: Virtual channel number of ERRB packet
VC_1 Packet
BACKTOP13 (0x42C)
BIT 7 6 5 4 3 2 1 0
Access
Type

VC_2 Packet
BACKTOP14 (0x42D)
BIT 7 6 5 4 3 2 1 0
Access
Type


VC_3 Packet
BACKTOP15 (0x42E)
BIT 7 6 5 4 3 2 1 0
Access
Type

VC_4 Packet
BACKTOP22 (0x435)
BIT 7 6 5 4 3 2 1 0
Field – – – – n_vs_block[3:0]
Reset – – – – 0x1
Access
Type

0x0: All frames out
0x1: Block the first frame
Frame block: ...
n_vs_block 3:0
Block the first 1-15 frames after video lock ...
...
0xF: Block the first 15 frames
BACKTOP23 (0x436)
BIT 7 6 5 4 3 2 1 0
Field – – – – dis_vs3 dis_vs2 dis_vs1 dis_vs0
Reset – – – – 0b0 0b0 0b0 0b0
Access
Type

Pipe 3 disable VS:
0b0: Enable VS out
dis_vs3 3 Disable the transmission of VS to MIPI
0b1: Disable VS out
output.
Pipe 2 disable VS:
0b0: Enable VS out
0b1: Disable VS out
output.
Pipe 1 disable VS:
0b0: Enable VS out
0b1: Disable VS out
output.


Pipe 0 disable VS:
0b0: Enable VS out
0b1: Disable VS out
output.
BACKTOP24 (0x437)
BIT 7 6 5 4 3 2 1 0
ERRB_PKT ERRB_PKT ERRB_PKT ERRB_PKT
Field _WC_OVR _WC_OVR _WC_OVR _WC_OVR – – – –
D_EN_4 D_EN_3 D_EN_2 D_EN_1
Reset 0x0 0x0 0x0 0x0 – – – –
Access
Write, Read Write, Read Write, Read Write, Read – – – –
Type

0 = Pick random word count from video
source in pipe 4 as the word count for ERRB
ERRB_PKT_
packets 0x0
WC_OVRD_ 7
1 = Use word count specified in 0x1: See Description
EN_4
ERRB_PKT_WC_4_H/L register as the word
count for ERRB packets
ERRB_PKT_
packets 0x0
WC_OVRD_ 6
EN_3
ERRB_PKT_
packets 0x0
WC_OVRD_ 5
EN_2
ERRB_PKT_
packets 0x0
WC_OVRD_ 4
EN_1
BACKTOP25 (0x438)
BIT 7 6 5 4 3 2 1 0
Field ERRB_PKT_WC_1_H[7:0]
Reset 0x0
Access
Write, Read
Type

If ERRB_PKT_WC_OVRD_EN_1 is set, this register sets the word count for
ERRB_PKT_WC_1_H 7:0 ERRB packet. When not in WC override mode, this register reads back
detected word count from incoming video used for ERRB packet.

BACKTOP26 (0x439)
BIT 7 6 5 4 3 2 1 0
Field ERRB_PKT_WC_1_L[7:0]
Reset 0x0
Access
Write, Read
Type

ERRB_PKT_WC_1_L 7:0 ERRB packet. When not in WC override mode, this register reads back
BACKTOP27 (0x43A)
BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BACKTOP28 (0x43B)
BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BACKTOP29 (0x43C)
BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type


BACKTOP30 (0x43D)
BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BACKTOP31 (0x43E)
BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BACKTOP32 (0x43F)
BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BACKTOP33 (0x440)
BIT 7 6 5 4 3 2 1 0
FIFO_EMP FIFO_EMP FIFO_EMP FIFO_EMP
Field – – – –
TY_3 TY_2 TY_1 TY_0
Reset – – – – 0x0 0x0 0x0 0x0
Access
– – – – Read Only Read Only Read Only Read Only
Type

FIFO_EMPTY_3 3 Pipe 3 FIFO empty


BACKTOP1_HDR_ERR (0x442)
BIT 7 6 5 4 3 2 1 0
TUN_HDR_ TUN_HDR_ TUN_HDR_ TUN_HDR_ TUN_HDR_ TUN_HDR_ TUN_HDR_ TUN_HDR_
Field ERR_FLAG ERR_FLAG CRC_ERR_ CRC_ERR_ CRC_ERR_ CRC_ERR_ ECC_ERR_ ECC_FLAG
_0_OEN _0 3_FLAG_0 2_FLAG_0 1_FLAG_0 0_FLAG_0 FLAG_0 _0
Reset 0b1 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Write, Read Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Type

0b0: Disable reporting of header error flag
TUN_HDR_E
Pipe 0 tunneling mode header error flag (TUN_HDR_ERR_FLAG_1) at ERRB pin
RR_FLAG_0 7
going to ERRB pin output enable. 0b1: Enable reporting of header error flag
_OEN
(TUN_HDR_ERR_FLAG_1) at ERRB pin
Pipe 0 tunneling mode header error flag
going to ERRB pin. This error flag takes 2-bit
ECC error (bit 1 of same register) when in
DPHY mode, logic AND of CPHY header 1
TUN_HDR_E 0x0: no error detected
6 and 2 (bits 2 and 3 in same register) in 1-lane
RR_FLAG_0 0x1: Error Detected
CPHY mode, and logic AND of CPHY header
1, 2, 3 and 4 (bits 2, 3, 4 and 5 in same
register) in 2-lane CPHY mode. This flag is
sticky (i.e., clear on read).
TUN_HDR_C Pipe 0 tunneling mode CPHY fourth header
0x0: no error detected
RC_ERR_3_ 5 CRC error flag. Obsolete when SER is in
0x1: Error Detected
FLAG_0 1-lane CPHY mode.
TUN_HDR_C Pipe 0 tunneling mode CPHY third header
0x1: Error Detected
TUN_HDR_C
Pipe 0 tunneling mode CPHY second header 0x0: no error detected
RC_ERR_1_ 3
CRC error flag 0x1: Error Detected
FLAG_0
TUN_HDR_C
Pipe 0 tunneling mode CPHY first header 0x0: no error detected
RC_ERR_0_ 2
FLAG_0
TUN_HDR_E
Pipe 0 tunneling mode DPHY header 2-bit 0x0: no error detected
CC_ERR_FL 1
(uncorrectable) ECC error flag 0x1: Error Detected
AG_0
TUN_HDR_E Pipe 0 tunneling mode DPHY header 1-bit 0x0: no error detected
0
CC_FLAG_0 (correctable) ECC error flag 0x1: Error Detected

BIT 7 6 5 4 3 2 1 0
Reset 0b1 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type

TUN_HDR_E
RR_FLAG_1 7
_OEN
0x1: Error Detected
0x1: Error Detected
TUN_HDR_C
RC_ERR_1_ 3
FLAG_1
TUN_HDR_C
RC_ERR_0_ 2
FLAG_1
TUN_HDR_E
CC_ERR_FL 1
AG_1
0
BIT 7 6 5 4 3 2 1 0
Reset 0b1 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type


TUN_HDR_E
RR_FLAG_2 7
_OEN
0x1: Error Detected
0x1: Error Detected
TUN_HDR_C
RC_ERR_1_ 3
FLAG_2
TUN_HDR_C
RC_ERR_0_ 2
FLAG_2
TUN_HDR_E
CC_ERR_FL 1
AG_2
0
BIT 7 6 5 4 3 2 1 0
Reset 0b1 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type

TUN_HDR_E
RR_FLAG_3 7
_OEN


0x1: Error Detected
0x1: Error Detected
TUN_HDR_C
RC_ERR_1_ 3
FLAG_3
TUN_HDR_C
RC_ERR_0_ 2
FLAG_3
TUN_HDR_E
CC_ERR_FL 1
AG_3
0
BACKTOP39 (0x446)
BIT 7 6 5 4 3 2 1 0
BKTP3_LIN BKTP3_LIN BKTP3_LIN BKTP3_LIN BKTP3_LIN BKTP2_LIN BKTP1_LIN BKTP0_LIN
Field E_LEN_OV E_LEN_OV E_LEN_OV E_LEN_OV E_LEN_OV E_LEN_OV E_LEN_OV E_LEN_OV
RD RD RD RD RD RD RD RD
Reset 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
Access
Type

Enable use of timeout timer for video
masking. By default, the timer is set to wait 1/
8th of a line. The time for a line is
autodetected.
BKTP3_LINE 0x0: Disabled
7 Use BKTPx_VM_TIMEOUT_DIV to select
_LEN_OVRD 0x1: Enabled
between 1, 1/2, 1/4, or 1/8th of a line.
Use BKTPx_VM_TIMEOUT_OVRD and
BKTPx_VM_TIMEOUT registers to override
timeout value in 3ns increments.
6 Enable use of timeout timer for video masking


Enable use of BKTPx_VM_TIMEOUT_H/L
3 registers to assert video timeout masking in
synchronous aggregation mode.
BACKTOP40 (0x447)
BIT 7 6 5 4 3 2 1 0
Field BKTP0_LINE_LEN_H[7:0]
Reset 0x7
Access
Write, Read
Type

Used to assert video timeout masking in tunneling mode in synchronous
aggregation (Wx4H) mode. If video is detected in other aggregated pipes and
BKTP0_LINE_LEN_H 7:0 current pipe does not receive video in the specified timeout time, current pipe
will be masked until video resumes at the beginning of a frame. Value
specified in this register is in 2.67ns increments.
BACKTOP41 (0x448)
BIT 7 6 5 4 3 2 1 0
Field BKTP0_LINE_LEN_L[7:0]
Reset 0x53
Access
Write, Read
Type

BKTP0_LINE_LEN_L 7:0 current pipe does not receive video in the specified timeout time, current pipe
BACKTOP42 (0x449)
BIT 7 6 5 4 3 2 1 0
Reset 0x7
Access
Write, Read
Type


BACKTOP43 (0x44A)
BIT 7 6 5 4 3 2 1 0
Reset 0x53
Access
Write, Read
Type

BACKTOP44 (0x44B)
BIT 7 6 5 4 3 2 1 0
Reset 0x7
Access
Write, Read
Type

BACKTOP45 (0x44C)
BIT 7 6 5 4 3 2 1 0
Reset 0x53
Access
Write, Read
Type


BACKTOP46 (0x44D)
BIT 7 6 5 4 3 2 1 0
Reset 0x7
Access
Write, Read
Type

BACKTOP47 (0x44E)
BIT 7 6 5 4 3 2 1 0
Reset 0x53
Access
Write, Read
Type

BACKTOP48 (0x44F)
BIT 7 6 5 4 3 2 1 0
BKTP4_VM_TIMEOUT_DI BKTP3_VM_TIMEOUT_DI BKTP2_VM_TIMEOUT_DI BKTP1_VM_TIMEOUT_DI
Field
V[1:0] V[1:0] V[1:0] V[1:0]
Access
Type

0x0: 1/4 of a line
BKTP4_VM_
0x1: 1/2 of a line
TIMEOUT_DI 7:6 Selects between 1, 3/4, 1/2, or 1/4 of a line.
0x2: 3/4 of a line
V
0x3: 1 line
0x0: 1/4 of a line
BKTP3_VM_
0x1: 1/2 of a line
0x2: 3/4 of a line
V
0x3: 1 line
0x0: 1/4 of a line
BKTP2_VM_
0x1: 1/2 of a line
0x2: 3/4 of a line
V
0x3: 1 line


0x0: 1/4 of a line
BKTP1_VM_
0x1: 1/2 of a line
0x2: 3/4 of a line
V
0x3: 1 line
BACKTOP_EMBED0 (0x450)
BIT 7 6 5 4 3 2 1 0
EMBED_LL EMBED_FL
EMBED_LL_NUM_BKTP0 EMBED_FL_NUM_BKTP0
Field _EN_BKTP – _EN_BKTP –
[1:0] [1:0]
0 0
Reset 0b0 – 0b0 0b0 – 0b0
Access
Write, Read – Write, Read Write, Read – Write, Read
Type

Enable conversion of last few pixel lines of
each frame into MIPI embedded data type.
EMBED_LL_ 0x0: Disabled
7 Applies to MIPI BACKTOP0 only.
EN_BKTP0 0x1: Enabled
0: Disable
1: Enable
When the embedded packet type is enabled
to be located in the last few lines of each
frame, this register field sets the line number
to be used for the converted embedded data
type.
EMBED_LL_ 0x0
5:4 Applies to MIPI BACKTOP0 only.
NUM_BKTP0 0x1: See Description
See the EMBED_LL_EN_BKTP0 register bit.
2'b00 - Use Last Line
2'b01- Use Second from Last Line
2'b10 - Use Third from Last Line
2'b11 - Use Fourth from Last Line
Enable conversion of first few pixel lines of
EMBED_FL_ 0x0: Disabled
0: Disable
1: Enable
to be located in the first few lines of each
type.
EMBED_FL_ 0x0
See the EMBED_FL_EN_BKTP0 register bit.
2'b00- Use first line.
2'b01- Use second line.
2'b10- Use third line
2'b11- Use fourth line

BIT 7 6 5 4 3 2 1 0
EMBED_LL EMBED_FL
[1:0] [1:0]
1 1
Reset 0b0 – 0b0 0b0 – 0b0
Access
Type

0: Disable
1: Enable
type.
EMBED_LL_ 0x0
0: Disable
1: Enable
type.
EMBED_FL_ 0x0
BIT 7 6 5 4 3 2 1 0
EMBED_LL EMBED_FL
[1:0] [1:0]
2 2
Reset 0b0 – 0b0 0b0 – 0b0
Access
Type


0: Disable
1: Enable
type.
EMBED_LL_ 0x0
3 Applies to MIPI BACKTOP02only.
0: Disable
1: Enable
type.
EMBED_FL_ 0x0
BIT 7 6 5 4 3 2 1 0
EMBED_LL EMBED_FL
[1:0] [1:0]
3 3
Reset 0b0 – 0b0 0b0 – 0b0
Access
Type

0: Disable
1: Enable


type.
EMBED_LL_ 0x0
0: Disable
1: Enable
type.
EMBED_FL_ 0x0
2'b10- Use third line.
2'b11- Use fourth line.
CMD_LMO_ERRB_EN (0x454)
BIT 7 6 5 4 3 2 1 0
CMD_OVFL CMD_OVFL CMD_OVFL CMD_OVFL
LMO_3_ER LMO_2_ER LMO_1_ER LMO_0_ER
Field _3_ERRB_ _2_ERRB_ _1_ERRB_ _0_ERRB_
RB_OEN RB_OEN RB_OEN RB_OEN
OEN OEN OEN OEN
Reset 0b1 0b1 0b1 0b1 0b1 0b1 0b1 0b1
Access
Type

CMD_OVFL_
Enable Pipe 3 command FIFO overflow 0x0: Disabled
3_ERRB_OE 7
Status on ERRB output 0x1: Enabled
N
CMD_OVFL_
2_ERRB_OE 6
N
CMD_OVFL_
1_ERRB_OE 5
N
CMD_OVFL_
0_ERRB_OE 4
N
Enable Pipe 3 line memory overflow status on
LMO_3_ERR ERRB output. 0x0: Disabled
3
B_OEN See the LMO_3_ERRB_EN to enable output 0x1: Enabled
of this status to the ERRB pin


LMO_2_ERR ERRB output. 0x0: Disabled
2
LMO_1_ERR ERRB output 0x0: Disabled
1
LMO_0_ERR Enable Pipe 0 line memory overflow status on 0x0: Disabled
0
B_OEN ERRB output. 0x1: Enabled
DPLL_ERRB_OEN (0x455)
BIT 7 6 5 4 3 2 1 0
CSIPLL3_L CSIPLL2_L CSIPLL1_L CSIPLL0_L CSI_DPLL3 CSI_DPLL2 CSI_DPLL1 CSI_DPLL0
Field OL_STICKY OL_STICKY OL_STICKY OL_STICKY _ERRB_OE _ERRB_OE _ERRB_OE _ERRB_OE
_FLAG _FLAG _FLAG _FLAG N N N N
Reset 0x0 0x0 0x0 0x0 0b1 0b1 0b1 0b1
Access
Read Only Read Only Read Only Read Only Write, Read Write, Read Write, Read Write, Read
Type

CSIPLL3 Loss of lock ERRB Flag.
This flag is the sticky bit output for the
CSIPLL3 Loss of Lock and is directly
associated with the CSIPLL3_LOCK register
bit.
The CSIPLL3_LOCK status data is live data,
CSIPLL3_LO
however, this bit is intended to catch a loss of 0x0: no error detected
L_STICKY_F 7
lock event and will maintain that information 0x1: Error Detected
LAG
until this register bit is cleared.
This register bit is cleared upon reading.
This register information is also reflected onto
the ERRB pin unless otherwise disabled from
doing so.
See the CSI_DPLL3_ERRB_OEN register.
CSIPLL2 Loss of Lock ERRB Flag.
bit.
The CSIPLL2_LOCK status data is live data;
CSIPLL2_LO
L_STICKY_F 6
LAG
doing so.


bit.
CSIPLL1_LO
L_STICKY_F 5
LAG
doing so.
bit.
CSIPLL0_LO
L_STICKY_F 4
LAG
doing so.
Enable CSI DPLL 3 Loss of Lock status on
ERRB output.
CSI_DPLL3_ 0x0: Disabled
3 See the CSIPLL3_LOCK status output
ERRB_OEN 0x1: Enabled
register bit and the
CSIPLL3_LOL_STICKY_FLAG register bit.
ERRB output.
ERRB output.
ERRB output.

BACKTOP_OVERRIDE_BPP_DT (0x456)
BIT 7 6 5 4 3 2 1 0
OVERRIDE OVERRIDE OVERRIDE OVERRIDE
OVERRIDE OVERRIDE OVERRIDE OVERRIDE
Field _BPP_DT_ _BPP_DT_ _BPP_DT_ _BPP_DT_
_VC_3 _VC_2 _VC_1 _VC_0
3 2 1 0
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type

This register allows software override of VC
only, similar to override_bpp_vc_dt_#.
Notes:
OVERRIDE_ 0x0: Disable
7 the OVERRIDE_VC_BITS_2_AND_3
VC_3 0x1: Enable
register.

for errb_pkts
Notes:
VC_2 0x1: Enable
register.

for errb_pkts
Notes:
VC_1 0x1: Enable
register.

for errb_pkts


Notes:
VC_0 0x1: Enable
register.

for errb_pkts
This register allows software override of BPP
3 and DT only, similar to
BPP_DT_3 0x1: Enable
override_bpp_vc_dt_#.
BACKTOP_OVERRIDE_VC (0x457)
BIT 7 6 5 4 3 2 1 0
OVERRIDE
Field – – – – – – – _VC_BITS_
2_AND_3
Reset – – – – – – – 0x0
Access
– – – – – – – Write, Read
Type

Override VC [3:2] such that VCs for each pipe
start with 4'h0, 4'h4,4'h8, and 4'hC
respectively. VC bits [1:0] are still passed
through.
Notes:
OVERRIDE_
and/or OVERRIDE_VC_# have priority over 0x0: Disable
VC_BITS_2_ 0
this OVERRIDE_VC_BITS_2_AND_3 0x1: Enable
AND_3
register.

for errb_pkts

SRAM_LCRC_ERR (0x458)
BIT 7 6 5 4 3 2 1 0
SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR
Field C_ERR_OE C_ERR_OE C_ERR_OE C_ERR_OE
C_ERR_3 C_ERR_2 C_ERR_1 C_ERR_0
N_3 N_2 N_1 N_0
Reset 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
Access
Write, Read Write, Read Write, Read Write, Read Read Only Read Only Read Only Read Only
Type

SRAM_LCRC_ERR_OE
7 SRAM Line CRC Error Ouput Enable.
N_3
SRAM_LCRC_ERR_OE
N_2
SRAM_LCRC_ERR_OE
N_1
SRAM_LCRC_ERR_OE
N_0
SRAM Line CRC Error Detection. Compares CRC value of data written to the
SRAM_LCRC_ERR_3 3
Video Line SRAM vs CRC value of data read out of the Video Line SRAM.
SRAM_LCRC_ERR_2 2
SRAM_LCRC_ERR_1 1
SRAM_LCRC_ERR_0 0
SRAM_LCRC_EN (0x459)
BIT 7 6 5 4 3 2 1 0
SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR
Field C_TUN_CH C_TUN_CH C_TUN_CH C_TUN_CH C_PIXEL_C C_PIXEL_C C_PIXEL_C C_PIXEL_C
K_DIS_3 K_DIS_2 K_DIS_1 K_DIS_0 HK_DIS_3 HK_DIS_2 HK_DIS_1 HK_DIS_0
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type

SRAM_LCRC_TUN_CH
7 SRAM Line CRC Tunnel Mode Check Disable
K_DIS_3
SRAM_LCRC_TUN_CH
K_DIS_2
SRAM_LCRC_TUN_CH
K_DIS_1
SRAM_LCRC_TUN_CH
K_DIS_0
SRAM_LCRC_PIXEL_C
3 SRAM Line CRC Pixel Mode Check Disable
HK_DIS_3
SRAM_LCRC_PIXEL_C
HK_DIS_2


SRAM_LCRC_PIXEL_C
HK_DIS_1
SRAM_LCRC_PIXEL_C
HK_DIS_0
SRAM_LCRC_RESET (0x45A)
BIT 7 6 5 4 3 2 1 0
INIT_SRAM INIT_SRAM INIT_SRAM INIT_SRAM SRAM_LCR SRAM_LCR SRAM_LCR SRAM_LCR
Field _LCRC_ER _LCRC_ER _LCRC_ER _LCRC_ER C_MATCH_ C_MATCH_ C_MATCH_ C_MATCH_
R_DIS_3 R_DIS_2 R_DIS_1 R_DIS_0 RESET_3 RESET_2 RESET_1 RESET_0
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access Write Clears Write Clears Write Clears Write Clears
Type All, Read All, Read All, Read All, Read

INIT_SRAM_LCRC_ER Initial SRAM Line CRC Error Disable. Disables requirement for SRAM Line
7
R_DIS_3 CRC Match within first 3 lines written to memory.
6
5
4
SRAM Line CRC Match Reset. Setting this bit to a logic 1 will reset internal
SRAM_LCRC_MATCH_ register such that if another LCRC Match does not occur within 3 video lines,
3
RESET_3 an SRAM LCRC Error will occur. Orthogonal Safety Check. Self-clearing
register.
2
register.
1
register.
0
register.
BKTOP_ERR_INJ_1 (0x480)
BIT 7 6 5 4 3 2 1 0
Field – – – – C_ERR_INJ C_ERR_INJ C_ERR_INJ C_ERR_INJ
_DIS_3 _DIS_2 _DIS_1 _DIS_0
Reset – – – – 0x0 0x0 0x0 0x0
Access
Type


SRAM_LCRC_ERR_IN
3 SRAM Line CRC Error Injection Disable
J_DIS_3
SRAM_LCRC_ERR_IN
J_DIS_2
SRAM_LCRC_ERR_IN
J_DIS_1
SRAM_LCRC_ERR_IN
J_DIS_0
MEM_ERR_INJ_1BIT (0x481)
BIT 7 6 5 4 3 2 1 0
MEM_ERR MEM_ERR MEM_ERR MEM_ERR
Field – – – – _INJ_1BIT_ _INJ_1BIT_ _INJ_1BIT_ _INJ_1BIT_
BKTP4 BKTP3 BKTP2 BKTP1
Reset – – – – 0x0 0x0 0x0 0x0
Access
Type

Inject one 1-bit error into each word
(MEM_ERR_INJ_WORD_LOC and
MEM_ERR_I
MEM_ERR_INJ_WORD2_LOC) when word 0x0: Normal operation
NJ_1BIT_BK 3
locations are enabled. Errors are injected 0x1: Inject error
TP4
one-time into the packet number specified in
MEM_ERR_INJ_PKT_NUM.
MEM_ERR_I
NJ_1BIT_BK 2
locations are enabled. Errors are injected one 0x1: Inject error
TP3
time into the packet number specified in
MEM_ERR_I
NJ_1BIT_BK 1
TP2
MEM_ERR_I
NJ_1BIT_BK 0
TP1

MEM_ERR_INJ_2BIT (0x482)
BIT 7 6 5 4 3 2 1 0
MEM_ERR MEM_ERR MEM_ERR MEM_ERR
Field – – – – _INJ_2BIT_ _INJ_2BIT_ _INJ_2BIT_ _INJ_2BIT_
BKTP4 BKTP3 BKTP2 BKTP1
Reset – – – – 0x0 0x0 0x0 0x0
Access
Type

Inject 2-bits of error into each word
MEM_ERR_I
NJ_2BIT_BK 3
TP4
MEM_ERR_I
NJ_2BIT_BK 2
TP3
MEM_ERR_I
NJ_2BIT_BK 1
TP2
MEM_ERR_I
NJ_2BIT_BK 0
TP1
MEM_ERR_INJ_WORD_LOC_EN (0x483)
BIT 7 6 5 4 3 2 1 0
MEM_ERR MEM_ERR
_INJ_WOR _INJ_WOR
Field – – – – – –
D_LOC_2_ D_LOC_1_
EN EN
Reset – – – – – – 0x0 0x1
Access
– – – – – – Write, Read Write, Read
Type

MEM_ERR_I
Enables second memory error injection word 0x0: Injection Disabled
NJ_WORD_L 1
location 0x1: Injection Enabled
OC_2_EN
MEM_ERR_I
0x0: Injection Disabled
NJ_WORD_L 0 Enables memory error injection word location
0x1: Injection Enabled
OC_1_EN

MEM_ERR_INJ_WORD_LOC_1 (0x484)
BIT 7 6 5 4 3 2 1 0
Field MEM_ERR_INJ_WORD_LOC_1[7:0]
Reset 0x00
Access
Write, Read
Type

Set word (24-bits) count location to inject 1-bit or 2-bit errors. Errors are
injected on bit locations specified by MEM_ERR_INJ_BIT_LOC and
MEM_ERR_INJ_BIT2_LOC.
In pixel mode, errors can only be injected into pixel data.

MEM_ERR_INJ_WORD
7:0 In tunnel mode:
_LOC_1
Inject Header Error Inject Pixel Error
DPHY <2 ≥2
CPHY 1-lane <4 ≥4
CPHY 2-lanes <8 ≥8
MEM_ERR_INJ_WORD_LOC_2 (0x485)
BIT 7 6 5 4 3 2 1 0
Field MEM_ERR_INJ_WORD_LOC_2[7:0]
Reset 0x00
Access
Write, Read
Type

Set second word (24-bits) count location to inject 1-bit or 2-bit errors. Errors
are injected on bit locations specified in MEM_ERR_INJ_BIT_LOC and
MEM_ERR_INJ_BIT2_LOC.
In pixel mode, errors can only be injected into pixel data.
In tunnel mode:
MEM_ERR_INJ_WORD
7:0 Inject Header Error Inject Pixel Error
_LOC_2
DPHY <2 ≥2
CPHY 1-lane <4 ≥4
CPHY 2-lanes <8 ≥8
Enabling word2_loc can result in a total of 4-bits of errors injected.
MEM_ERR_INJ_PKT_NUM (0x486)
BIT 7 6 5 4 3 2 1 0
Field – – – – MEM_ERR_INJ_PKT_NUM[3:0]
Reset – – – – 0x0
Access
Type


MEM_ERR_INJ_PKT_N Sets the packet to inject 1-bit or 2-bit errors. Packet is counted from the next
3:0
UM frame-start packet after MEM_ERR_INJ_1/2_BIT_BKTPx is set .
MEM_ERR_INJ_BIT1_LOC (0x487)
BIT 7 6 5 4 3 2 1 0
Field – – – MEM_ERR_INJ_BIT1_LOC[4:0]
Reset – – – 0x03
Access
– – – Write, Read
Type

Specify bit location to inject 1-bit error on a 24-bit bus. Min = 0, Max = 23. If
MEM_ERR_INJ_BIT1_L set to more than 23, no error will be injected.
4:0
OC
Bit and Bit 2 locations are used by both word locations.
MEM_ERR_INJ_BIT2_LOC (0x488)
BIT 7 6 5 4 3 2 1 0
Field – – – MEM_ERR_INJ_BIT2_LOC[4:0]
Reset – – – 0x00
Access
Type

Specify second bit location to inject 2-bit error on a 24-bit bus. Min = 0, Max =
MEM_ERR_INJ_BIT2_L 23. If set to more than 23, no error will be injected.
4:0
OC
Bit and bit 2 locations are used by both word locations.
FSYNC_0 (0x4A0)
BIT 7 6 5 4 3 2 1 0
FSYNC_OU EN_VS_GE
Field RSVD RSVD FSYNC_MODE[1:0] FSYNC_METH[1:0]
T_PIN N
Reset 0x0 0x0 0b0 0x0 0x3 0x0
Access
Type

FSYNC_OUT Selects pin to output frame sync signal 0b0: MFP0
5
_PIN (effective only when FSYNC_METH = 01) 0b1: MFP7
0b0: VS is not generated internally by the frame
Selects whether or not VS is generated
sync generator
EN_VS_GEN 4 internally by the frame sync generator
0b1: VS is generated internally by the frame sync
(not effective when FSYNC_MODE = 11)
generator


0b00: Frame sync generation is on. GPIO is not
used as FSYNC input or output
0b01: Frame sync generation is on. GPIO is used
as FSYNC output and drives a slave device
FSYNC_MO 0b10: Frame sync generation is off.
3:2 Frame Synchronization Mode
DE GPIO is used as FSYNC input driven by a master
device for GMSL1 links. Any enabled GPIO input
can be used as FSYNC input for GMSL2 links.
0b11: Frame sync generation is off.
GPIO is not used as FSYNC input or output
0b00: Manual
FSYNC_MET 0b01: Semi-auto
1:0 Frame Synchronization Method
H 0b10: Auto
0b11: Reserved
FSYNC_1 (0x4A1)
BIT 7 6 5 4 3 2 1 0
Field RSVD[1:0] RSVD[1:0] FSYNC_PER_DIV[3:0]
Reset 0x0 0x0 0x0
Access
Write, Read
Type

0x0: 1
0x1: 2
0x2: 3
0x3: 6
0x4: 8
0x5: 10
0x6: 12
FSYNC_PER Frame sync transmission period in terms of 0x7: 16
3:0
_DIV VSYNC periods 0x8: 20
0x9: 24
0xA: 32
0xB: 48
0xC: 64
0xD: 80
0xE: 96
0xF: 128
FSYNC_2 (0x4A2)
BIT 7 6 5 4 3 2 1 0
K_VAL_SIG
Field MST_LINK_SEL[2:0] K_VAL[3:0]
N
Reset 0x4 0x0 0x1
Access
Type


0b000: Video 0
0b001: Video 1
0b010: Video 2
MST_LINK_ 0b011: Video 3
7:5 Master link select for frame sync generation
SEL 0b100: Auto select
0b101: Auto select
0b110: Auto select
0b111: Auto select
K_VAL_SIG 0b0: K_VAL is positive
4 Sign bit of K_VAL
N 0b1: K_VAL is negative
0x0: 0.85μs
0x1: 1.71μs
0x2: 2.56μs
0x3: 3.41μs
0x4: 4.27μs
0x5: 5.12μs
Desired frame sync margin with respect to 0x6: 5.97μs
either the VSYNC of the slowest link in 0x7: 6.83μs
K_VAL 3:0
automatic mode or the VSYNC of the master 0x8: 8.53μs
link in semi-automatic mode. 0x9: 10.24μs
0xA: 11.95μs
0xB: 13.65μs
0xC: 17.07μs
0xD: 20.48μs
0xE: 23.89μs
0xF: 27.31μs
FSYNC_3 (0x4A3)
BIT 7 6 5 4 3 2 1 0
Field P_VAL_L[7:0]
Reset 0x00
Access
Write, Read
Type

Low byte of desired frame sync margin in
terms of PCLK cycles with respect to the
0bXXXXXXXX: Low byte of desired frame sync
P_VAL_L 7:0 VSYNC of the slowest link in automatic mode
margin
or with respect to the VSYNC of the master
link in semi-automatic mode
FSYNC_4 (0x4A4)
BIT 7 6 5 4 3 2 1 0
P_VAL_SIG
Field – – P_VAL_H[4:0]
N
Reset – – 0x0 0x00
Access
Type

P_VAL_SIG 0b0: P_VAL is positive
5 Sign bit of P_VAL
N 0b1: P_VAL is negative


High bits of desired frame sync margin in
terms of PCLK cycles with respect to the
P_VAL_H 4:0 VSYNC of the slowest link in automatic mode 0bXXXXX: High bits of desired frame sync margin
or with respect to the VSYNC of the master
link in semi-automatic mode
FSYNC_5 (0x4A5)
BIT 7 6 5 4 3 2 1 0
Field FSYNC_PERIOD_L[7:0]
Reset 0x00
Access
Write, Read
Type

Low byte of frame sync period in terms of
FSYNC_PER
7:0 pixel clock (effective when FSYNC_METH = 0xXX: Low byte of number of PLCK cycles in
IOD_L
00 and FSYNC_MODE = 0x) FSYNC period
FSYNC_6 (0x4A6)
BIT 7 6 5 4 3 2 1 0
Field FSYNC_PERIOD_M[7:0]
Reset 0x00
Access
Write, Read
Type

Middle byte of frame sync period in terms of
FSYNC_PER 0xXX: Middle byte of number of PLCK cycles in
7:0 pixel clock (effective when FSYNC_METH =
IOD_M FSYNC period
00 and FSYNC_MODE = 0x)
FSYNC_7 (0x4A7)
BIT 7 6 5 4 3 2 1 0
Field FSYNC_PERIOD_H[7:0]
Reset 0x00
Access
Write, Read
Type

High byte of frame sync period in terms of
FSYNC_PER 0xXX: High byte of number of PLCK cycles in
7:0 pixel clock (effective when FSYNC_METH =
IOD_H FSYNC period
00 and FSYNC_MODE = 0x)

FSYNC_8 (0x4A8)
BIT 7 6 5 4 3 2 1 0
Field FRM_DIFF_ERR_THR_L[7:0]
Reset 0x00
Access
Write, Read
Type

Low byte of the error threshold for the
difference between the earliest and latest
FRM_DIFF_ 0xXX: Low byte of number of PLCK cycles in
7:0 VSYNCs in terms of PCLK cycles
ERR_THR_L VSYNC error threshold
(default is 40μs for 96MHz PCLK)
(disabled when all 13 bits are 0’s)
FSYNC_9 (0x4A9)
BIT 7 6 5 4 3 2 1 0
Field – – – FRM_DIFF_ERR_THR_H[4:0]
Reset – – – 0x0F
Access
Type

High bits of the error threshold for the
difference between the earliest and latest
FRM_DIFF_ 0bXXXXX: High bits of number of PLCK cycles in
4:0 VSYNCs in terms of PCLK cycles
ERR_THR_H VSYNC error threshold
(default is 40μs for 96MHz PCLK)
FSYNC_10 (0x4AA)
BIT 7 6 5 4 3 2 1 0
Field OVLP_WINDOW_L[7:0]
Reset 0x00
Access
Write, Read
Type

Low byte of the overlap window value in
OVLP_WIND terms of PCLK cycles 0xXX: Low byte of number of PCLK cycles in the
7:0
OW_L (default is 60μs for 96MHz PCLK) VSYNC-FSYNC overlap window
FSYNC_11 (0x4AB)
BIT 7 6 5 4 3 2 1 0
EN_FSIN_L
Field – – OVLP_WINDOW_H[4:0]
AST
Reset 0x0 – – 0x00
Access
Type


When set to 0, FSIN can occur anywhere with
0b0: FSIN can occur anywhere with respect to VS
EN_FSIN_LA respect to VS rising edges
7 rising edges
ST When set to 1, FSIN should occur after all VS
0b1: FSIN occurs after all rising edges
rising edges
High bits of the overlap window value in
OVLP_WIND terms of PCLK cycles 0bXXXXX: High bits of number of PCLK cycles in
4:0
OW_H (default is 60μs for 96MHz PCLK) the VSYNC-FSYNC overlap window
FSYNC_15 (0x4AF)
BIT 7 6 5 4 3 2 1 0
FS_GPIO_T FS_USE_X AUTO_FS_
Field – FS_LINK_3 FS_LINK_2 FS_LINK_1 FS_LINK_0
YPE TAL LINKS
Reset 0x1 0x1 – 0x0 0x1 0x1 0x1 0x1
Access
Write, Read Write, Read – Write, Read Write, Read Write, Read Write, Read Write, Read
Type

FS_GPIO_T Selects the type of FSYNC signal to output 0b0: GSML1 type
7
YPE from GPIO 0b1: GMSL2 type
FS_USE_XT Uses crystal oscillator clock for generating 0b0: Disabled
6
AL frame sync signal 0b1: Enabled
0b0: Include links selected by FS_LINK_x register
AUTO_FS_LI Selects how links are selected for frame sync bits in frame sync generation
4
NKS generation 0b1: Include all enabled links in frame sync
generation
Includes Video Pipe 3 in frame sync 0b0: Do not include Video Pipe 3 in frame sync
FS_LINK_3 3 generation generation
This is used only if AUTO_FS_LINKS = 0 0b1: Include Video Pipe 3 in frame sync generation
FSYNC_16 (0x4B0)
BIT 7 6 5 4 3 2 1 0
Field FSYNC_ERR_CNT[7:0]
Reset 0x00
Access
Read Clears All
Type

Frame Sync Error Counter (resets to 0 when
FSYNC_ERR 0xXX: Number of frame sync errors detected since
7:0 read or when FSYNC_LOCKED (0x4B6)
_CNT last error counter reset
goes high)

FSYNC_17 (0x4B1)
BIT 7 6 5 4 3 2 1 0
Field FSYNC_TX_ID[4:0] FSYNC_ERR_THR[2:0]
Reset 0x1E 0x0
Access
Type

FSYNC_TX_I 0bXXXXX: GPIO ID associated with FSYNC
7:3 GPIO ID used for transmitting FSYNC signal
D transmission
0b000: 1 error
0b001: 2 errors
0b010: 4 errors
Frame sync error reporting threshold.
FSYNC_ERR 0b011: 8 errors
2:0 FSYNC_ERR_FLAG is asserted when
_THR 0b100: 16 errors
FSYNC_ERR_CNT ≥ FSYNC_ERR_THR.
0b101: 32 errors
0b110: 64 errors
0b111: 128 errors
FSYNC_18 (0x4B2)
BIT 7 6 5 4 3 2 1 0
Field CALC_FRM_LEN_L[7:0]
Reset 0x00
Access
Read Only
Type

Low byte of calculated VS period of master
link in terms of pixel clock in automatic or 0xXX: Low byte of number of PCLKs in VS period
CALC_FRM_
7:0 semi-automatic synchronization mode in master link auto or semi-auto synchronization
LEN_L
(Use when FSYNC_METH = 10 and mode.
FSYNC_MODE = 0x)
FSYNC_19 (0x4B3)
BIT 7 6 5 4 3 2 1 0
Field CALC_FRM_LEN_M[7:0]
Reset 0x00
Access
Read Only
Type

Middle byte of calculated VS period of master
link in terms of pixel clock in automatic or 0xXX: Middle byte of number of PCLKs in VS
CALC_FRM_
7:0 semi-automatic synchronization mode period in master link auto or semi-auto
LEN_M
(Use when FSYNC_METH = 10 and synchronization mode
FSYNC_MODE = 0x)

FSYNC_20 (0x4B4)
BIT 7 6 5 4 3 2 1 0
Field CALC_FRM_LEN_H[7:0]
Reset 0x00
Access
Read Only
Type

High byte of calculated VS period of master
link in terms of pixel clock in automatic or 0xXX: High byte of number of PCLKs in VS period
CALC_FRM_
7:0 semi-automatic synchronization mode in master link auto or semi-auto synchronization
LEN_H
(Use when FSYNC_METH = 10 and mode
FSYNC_MODE = 0x)
FSYNC_21 (0x4B5)
BIT 7 6 5 4 3 2 1 0
Field FRM_DIFF_L[7:0]
Reset 0x00
Access
Read Only
Type

Low byte of the difference between the
0xXX: Low byte of the difference between the
FRM_DIFF_L 7:0 fastest and the slowest frame in terms of
fastest and the slowest frame
master PCLK cycles
FSYNC_22 (0x4B6)
BIT 7 6 5 4 3 2 1 0
FSYNC_LO
FSYNC_LO
Field SS_OF_LO FRM_DIFF_H[5:0]
CKED
CK
Reset 0x0 0x0 0x00
Access Read
Read Only Read Only
Type Clears All

Frame Synchronization Lost Lock 0b0: Frame synchronization loss of lock has not
been detected or has been cleared by a previous
FSYNC_LOS
7 This bit is set to 1 when frame read operation
S_OF_LOCK
synchronization loses lock. It is cleared when 0b1: Frame synchronization loss of lock has been
read. detected
FSYNC_LOC 0b0: Frame synchronization is not locked
6 Frame Synchronization Lock
KED 0b1: Frame synchronization is locked
High bits of the difference between the fastest
FRM_DIFF_ 0bXXXXX: High bits of the difference between the
5:0 and the slowest frame in terms of master
H fastest and the slowest frame
PCLK cycles

FSYNC_23 (0x4B7)
BIT 7 6 5 4 3 2 1 0
FSYNC_RS
Field RSVD RSVD – RSVD RSVD RSVD RSVD
T_MODE
Reset 0x0 0x0 0b0 – 0x0 0x0 0x0 0x0
Access
Write, Read –
Type

0x0: Legacy
FSYNC_RST
5 0x1: Start frame sync state machine regardless of
_MODE
video locks.
TR0 (0x500, 0x560)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL[1:0] PRIO_CFG[1:0]
N N
Access
Type

0b0: Do not calculate and append CRC to each
When set, calculates and appends CRC to
TX_CRC_EN 7 packet
each packet transmitted from this port
0b1: Calculate and append CRC to each packet
0b0: Do not perform CRC check at each packet
0b1: Perform CRC check at each packet
0b00: Low priority
PRIO_VAL 3:2
requests 0b10: High priority
0b00: Priority from Tx adapter is used
Adjusts the priority to be used for requests 0b01: Priority from Tx adapter is increased
PRIO_CFG 1:0
from this channel 0b10: Priority from Tx adapter is decreased
0b11: Priority in PRIO_VAL register is used
TR1 (0x501, 0x561)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

BW_MULT 7:6
factor 0b10: Multiply BW_VAL by 16


BW_VAL 5:0 bandwidth use ratio = BW_VAL x BW_MULT/ 0bXXXXXX: Channel base-bandwidth value
10 as a percentage of total link bandwidth
TR3 (0x503, 0x563)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

pin.
TR4 (0x504, 0x564)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

packets with source ID equal to 0 and 3 will ...
be received. ...
ARQ1 (0x506, 0x566)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
Field – MAX_RT[2:0] RSVD RSVD
RR_OEN EN
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

Maximum retransmission limit. ARQ will stop
MAX_RT 6:4 retransmission after reaching the limit for a
single packet.


Enables reporting of ARQ maximum 0b0: Disable reporting of ARQ maximum
MAX_RT_ER retransmission limit errors retransmission limit errors
1
R_OEN (MAX_RT_ERR—ARQ2 register) for this 0b1: Enable reporting of ARQ maximum
channel at ERRB pin retransmission limit errors
Enables reporting of ARQ retransmission
0b0: Disable reporting of ARQ retransmission
RT_CNT_OE event for this channel at ERRB pin. When
0 event
N enabled, ERRB is asserted when RT_CNT of
0b1: Enable reporting of ARQ retransmission event
this channel is greater than 0.
ARQ2 (0x507, 0x567)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT[6:0]
RR
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT—ARQ1) for one packet in this
R 0b1: Maximum retransmission limit reached
channel
0bXXXXXXX: Count of retransmission for this
RT_CNT 6:0 Total retransmission count in this channel
channel
TR0 (0x510)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_B[1:0] PRIO_CFG_B[1:0]
N_B N_B
Access
Type

TX_CRC_EN When set, calculates and appends CRC to
7 packet
_B each packet transmitted from this port
RX_CRC_EN 0b0: Do not perform CRC check at each packet
_B 0b1: Perform CRC check at each packet
0b00: Low priority
3:2
00: Priority from Tx adapter is used
PRIO_CFG_ Adjusts the priority to be used for requests 01: Priority from Tx adapter is increased
1:0
B from this channel 10: Priority from Tx adapter is decreased
11: Priority in PRIO_VAL register is used

TR1 (0x511)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
B factor 0b10: Multiply BW_VAL_B by 16
bandwidth
TR3 (0x513)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
B
pin.
TR4 (0x514)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

Received packets from selected sources 0x01: Packets from source ID 0 received
00001001, packets with source ID equal to 0 ...
and 3 will be received. ...

ARQ1 (0x516)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
RR_OEN_B EN_B
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_B 6:4 retransmission after reaching the limit for a
single packet.
0b0: Disable reporting of ARQ maximum
Enables reporting of ARQ maximum
MAX_RT_ER retransmission limit errors
1 retransmission limit errors (MAX_RT_ERR_B
R_OEN_B 0b1: Enable reporting of ARQ maximum
(0x517)) for this channel at ERRB pin
retransmission limit errors
0 event
N_B enabled, ERRB is asserted when RT_CNT_B
(0x517) of this channel is greater than 0.
ARQ2 (0x517)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_B[6:0]
RR_B
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_B (0x516)) for one packet in this
channel
RT_CNT_B 6:0 Total retransmission count in this channel
channel
TR0 (0x520)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_C[1:0] PRIO_CFG_C[1:0]
N_C N_C
Access
Type

7 packet
_C each packet transmitted from this port


_C 0b1: Perform CRC check at each packet
0b00: Low priority
3:2
C requests 0b10: High priority
PRIO_CFG_ Adjusts the priority to be used for requests 0b01: Priority from Tx adapter is increased
1:0
C from this channel 0b10: Priority from Tx adapter is decreased
TR1 (0x521)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
bandwidth
TR3 (0x523)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
C
pin.
TR4 (0x524)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type


Received packets from selected sources 0x01: Packets from source ID 0 received
ARQ1 (0x526)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
RR_OEN_C EN_C
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_C 6:4 retransmission after reaching the limit for a
single packet.
1 retransmission limit errors (MAX_RT_ERR_C
R_OEN_C 0b1: Enable reporting of ARQ maximum
0 event
N_C enabled, ERRB is asserted when RT_CNT_C
ARQ2 (0x527)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_C[6:0]
RR_C
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_C (0x526)) for one packet in this
channel
RT_CNT_C 6:0 Total retransmission count in this channel
channel

TR0 (0x530)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_D[1:0] PRIO_CFG_D[1:0]
N_D N_D
Access
Type

7 packet
_D each packet transmitted from this port
_D 0b1: Perform CRC check at each packet
0b00: Low priority
3:2
D requests 0b10: High priority
PRIO_CFG_ Adjusts the priority to be used for requests 0b01: Priority from Tx adapter is increased
1:0
D from this channel 0b10: Priority from Tx adapter is decreased
TR1 (0x531)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
bandwidth
TR3 (0x533)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type


TX_SRC_ID_
D
pin.
TR4 (0x534)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

Received packets from selected sources. 0x01: Packets from source ID 0 received
ARQ1 (0x536)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
RR_OEN_D EN_D
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_D 6:4 retransmission after reaching the limit for a
single packet.
1 retransmission limit errors (MAX_RT_ERR_D
R_OEN_D 0b1: Enable reporting of ARQ maximum
0 event
N_D enabled, ERRB is asserted when RT_CNT_D

ARQ2 (0x537)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_D[6:0]
RR_D
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_D (0x536)) for one packet in this
channel
RT_CNT_D 6:0 Total retransmission count in this channel
channel
TR0 (0x570)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_B[1:0] PRIO_CFG_B[1:0]
N_B N_B
Access
Type

7 packet
_B each packet transmitted from this port
_B 0b1: Perform CRC check at each packet
0b00: Low priority
3:2
PRIO_CFG_ Adjust the priority to be used for requests 0b01: Priority from Tx adapter is increased
1:0
B from this channel 0b10: Priority from Tx adapter is decreased
TR1 (0x571)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type


7:6
B factor 0b10: Multiply BW_VAL_B by 16
bandwidth
TR3 (0x573)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
B
pin.
TR4 (0x574)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

ARQ1 (0x576)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
RR_OEN_B EN_B
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type


MAX_RT_B 6:4 retransmission after reaching the limit for a
single packet.
1 retransmission limit errors (MAX_RT_ERR
R_OEN_B 0b1: Enable reporting of ARQ maximum
0 event
N_B enabled, ERRB is asserted when RT_CNT
ARQ2 (0x577)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_B[6:0]
RR_B
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_B (0x576)) for one packet in this
channel
RT_CNT_B 6:0 Total retransmission count in this channel
channel
TR0 (0x580)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_C[1:0] PRIO_CFG_C[1:0]
N_C N_C
Access
Type

TX_CRC_EN When set, calculate and append CRC to each
7 packet
_C packet transmitted from this port
_C 0b1: Perform CRC check at each packet
0b00: Low priority
3:2
C requests 0b10: High priority
1:0
C from this channel 0b10: Priority from Tx adapter is decreased

TR1 (0x581)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
bandwidth
TR3 (0x583)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
C
pin.
TR4 (0x584)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type

Receive packets from selected sources 0x01: Packets from source ID 0 received

ARQ1 (0x586)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
RR_OEN_C EN_C
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_C 6:4 retransmission after reaching the limit for a
single packet.
Enable reporting of ARQ maximum 0b0: Disable reporting of ARQ maximum
MAX_RT_ER retransmission limit errors retransmission limit errors
1
R_OEN_C (MAX_RT_ERR_C—0X587) for this channel 0b1: Enable reporting of ARQ maximum
at ERRB pin retransmission limit errors
Enable reporting of ARQ retransmission
0 event
N_C enabled, ERRB is asserted when RT_CNT_C
ARQ2 (0x587)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_C[6:0]
RR_C
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_C (0x586)) for one packet in this
channel
RT_CNT_C 6:0 Total retransmission count in this channel
channel
TR0 (0x590)
BIT 7 6 5 4 3 2 1 0
TX_CRC_E RX_CRC_E
Field RSVD[1:0] PRIO_VAL_D[1:0] PRIO_CFG_D[1:0]
N_D N_D
Access
Type

TX_CRC_EN When set, calculate and append CRC to each
7 packet
_D packet transmitted from this port


_D 0b1: Perform CRC check at each packet
0b00: Low priority
3:2
D requests 0b10: High priority
1:0
D from this channel 0b10: Priority from Tx adapter is decreased
TR1 (0x591)
BIT 7 6 5 4 3 2 1 0
Reset 0x2 0x30
Access
Type

7:6
bandwidth
TR3 (0x593)
BIT 7 6 5 4 3 2 1 0
Reset – – – – – 0x0
Access
Type

TX_SRC_ID_
D
pin.
TR4 (0x594)
BIT 7 6 5 4 3 2 1 0
Reset 0xFF
Access
Write, Read
Type


Received packets from selected sources. 0x01: Packets from source ID 0 received
ARQ1 (0x596)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E RT_CNT_O
RR_OEN_D EN_D
Reset – 0x7 0x0 0x0 0b1 0b0
Access
Type

MAX_RT_D 6:4 retransmission after reaching the limit for a
single packet.
1 retransmission limit errors (MAX_RT_ERR
R_OEN_D 0b1: Enable reporting of ARQ maximum
0 event
N_D enabled, ERRB is asserted when RT_CNT_D
ARQ2 (0x597)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E
Field RT_CNT_D[6:0]
RR_D
Reset 0b0 0x0
Access Read
Read Clears All
Type Clears All

7 (MAX_RT_D (0x596)) for one packet in this
channel
RT_CNT_D 6:0 Total retransmission count in this channel
channel

I2C_0 (0x640)
BIT 7 6 5 4 3 2 1 0
Field – RSVD SLV_SH_P0_A[1:0] – SLV_TO_P0_A[2:0]
Reset – 0x0 0x2 – 0x6
Access
Type

Link A GMSL1 and GMSL2 I2C-to-I2C Slave
Setup and Hold Time Setting (setup, hold).
Configures the interval between SDA and

SCL transitions when driven by the internal
0b00: Fast-mode Plus
I2C slave.
SLV_SH_P0 0b01: Fast-mode
5:4
_A 0b10: Standard-mode
Set this according to the I2C speed mode.
0b11: Reserved
This setting applies only to I2C Port 0 for
GMSL2.
This setting applies to all I2C Ports for

GMSL1.
Link A GMSL1 and GMSL2 I2C-to-I2C Slave
Timeout Setting.
0b000: 16μs
Internal I2C slave times out after the
0b001: 1ms
configured duration if it does not receive any
0b010: 2ms
response while waiting for a packet from
SLV_TO_P0 0b011: 4ms
2:0 remote device.
_A 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_1 (0x641)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P0_A[2:0] – MST_TO_P0_A[2:0]
Reset 0x0 0x5 – 0x6
Access
Type


Link A GMSL1 and GMSL2 I2C-to-I2C Master
Bit Rate Setting.
3b000: 9.92Kbps - Set for I2C Standard-mode
speed
Configures the I2C bit rate used by the
internal I2C master (in the device on remote
speed
side from the external I2C master).
3b010: 99.2Kbps - Set for I2C Standard or Fast-
mode speed
MST_BT_P0 3b011: 123Kbps - Set for I2C Fast-mode speed
6:4 GMSL2 Link A.
_A 3b100: 203Kbps - Set for I2C Fast-mode speed
3b101: 397Kbps - Set for I2C Fast or Fast-mode
Plus speed
GMSL1 Link A.
Plus speed
Set this according to the I2C speed mode:
3b111: 980Kbps - Set for I2C Fast-mode Plus
Fast-mode Plus = 101 to 111
speed
Fast-mode = 010 to 101
Standard-mode = 000 to 010
Link A GMSL1 and GMSL2 I2C-to-I2C Master
Timeout Setting.
0b000: 16μs
Internal I2C master times out after the
0b001: 1ms
0b010: 2ms
response while waiting for a packet from the
MST_TO_P0 0b011: 4ms
2:0 remote device.
_A 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_2 (0x642)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P0_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Link A GMSL1 and GMSL2 I2C Address
Translator Source A.
0b0000000: Write/read device address is 0x00/
When I2C device address matches 0x01
SRC_A_P0_A, internal I2C master (on 0b0000001: Write/read device address is 0x02/
remote side) replaces the device address by 0x03
SRC_A_P0_
7:1 DST_A_P0_A. ...
A
...
This setting applies only to I2C Port 0 for ...
GMSL2. 0b1111111: Write/read device address is 0xFE/
0xFF
GMSL1.

I2C_3 (0x643)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P0_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Destination A.
0x01
0x03
DST_A_P0_ GMSL2.
7:1 ...
A
...
...
GMSL1.
0b1111111: Write/read device address is 0xFE/
0xFF
See the description of SRC_A_P0_A.
I2C_4 (0x644)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P0_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Source B.
SRC_B_P0_A, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_B_P0_
7:1 DST_B_P0_A. ...
A
...
0xFF
GMSL1.
I2C_5 (0x645)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P0_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


Translator Destination B.
0x01
0x03
DST_B_P0_ GMSL2.
7:1 ...
A
...
...
GMSL1.
0xFF
See the description of SRC_B_P0_A.
I2C_0 (0x650)
BIT 7 6 5 4 3 2 1 0
Field – – SLV_SH_P0_B[1:0] – SLV_TO_P0_B[2:0]
Reset – – 0x2 – 0x6
Access
– – Write, Read – Write, Read
Type

Link B GMSL1 and GMSL2 I2C-to-I2C Slave
Setup and Hold Time Setting (setup, hold)

I2C slave. 0b00: Fast-mode Plus
5:4
_B Set this according to the I2C speed mode. 0b10: Standard-mode
0b11: Reserved
GMSL2.

GMSL1.
Link B GMSL1 and GMSL2 I2C-to-I2C Slave
Timeout Setting
0b000: 16μs
Internal I2C slave times out after the 0b001: 1ms
configured duration if it does not receive any 0b010: 2ms
SLV_TO_P0 response while waiting for a packet from 0b011: 4ms
2:0
_B remote device. 0b100: 8ms
0b101: 16ms
This setting applies only to I2C Port 0 for 0b110: 32ms
GMSL2. 0b111: Disabled
GMSL1.
I2C_1 (0x651)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P0_B[2:0] – MST_TO_P0_B[2:0]
Access
Type


Link B GMSL1 and GMSL2 I2C-to-I2C Master
Bit Rate Setting
speed
speed
mode speed
6:4 GMSL2 Link B.
_B 3b100: 203Kbps - Set for I2C Fast-mode speed
Plus speed
GMSL1 Link B.
Plus speed
speed
Link B GMSL1 and GMSL2 I2C-to-I2C Master
Timeout Setting
0b000: 16μs
0b001: 1ms
0b010: 2ms
2:0 remote device.
_B 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_2 (0x652)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P0_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Link B GMSL1 and GMSL2 I2C Address
Translator Source A
SRC_A_P0_B, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_A_P0_
7:1 DST_A_P0_B. ...
B
...
0xFF
GMSL1.

I2C_3 (0x653)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P0_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Link B GMSL1 and GMSL2 I2C Address 0b0000000: Write/read device address is 0x00/
Translator Destination A. 0x01
This setting applies only to I2C Port 0 for 0x03
DST_A_P0_
7:1 GMSL2. ...
B
This setting applies to all I2C Ports for ...
GMSL1. ...
See the description of SRC_A_P0_B. 0xFF
I2C_4 (0x654)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P0_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Source B
SRC_B_P0_B, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_B_P0_
7:1 DST_B_P0_B. ...
B
...
0xFF
GMSL1.
I2C_5 (0x655)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P0_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


Translator Destination B
0x01
0x03
DST_B_P0_ GMSL2.
7:1 ...
B
...
...
GMSL1.
0xFF
See the description of SRC_B_P0_B.
I2C_0 (0x660)
BIT 7 6 5 4 3 2 1 0
Field – – SLV_SH_P0_C[1:0] – SLV_TO_P0_C[2:0]
Reset – – 0x2 – 0x6
Access
Type

Link C GMSL1 and GMSL2 I2C-to-I2C Slave
Setup and Hold Time Setting (setup, hold).

I2C slave.
5:4
_C 0b10: Standard-mode
0b11: Reserved
GMSL2.

GMSL1.
Link C GMSL1 and GMSL2 I2C-to-I2C Slave
Timeout Setting
0b000: 16μs
0b001: 1ms
0b010: 2ms
2:0 remote device.
_C 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_1 (0x661)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P0_C[2:0] – MST_TO_P0_C[2:0]
Access
Type


Link C GMSL1 and GMSL2 I2C-to-I2C Master
Bit Rate Setting
speed
speed
mode speed
6:4 GMSL2 Link C.
_C 3b100: 203Kbps - Set for I2C Fast-mode speed
Plus speed
GMSL1 Link C.
Plus speed
speed
Link C GMSL1 AND GMSL2 I2C-to-I2C
Master Timeout Setting
0b000: 16μs
0b001: 1ms
0b010: 2ms
2:0 remote device.
_C 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_2 (0x662)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P0_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Link C GMSL1 and GMSL2 I2C Address
Translator Source A
SRC_A_P0_C, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_A_P0_
7:1 DST_A_P0_C. ...
C
...
0xFF
GMSL1.

I2C_3 (0x663)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P0_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Destination A
0x01
0x03
DST_A_P0_ GMSL2.
7:1 ...
C
...
...
GMSL1.
0xFF
See the description of SRC_A_P0_C.
I2C_4 (0x664)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P0_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Source B
SRC_B_P0_C, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_B_P0_
7:1 DST_B_P0_C. ...
C
...
0xFF
GMSL1.
I2C_5 (0x665)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P0_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


Translator Destination B
0x01
0x03
DST_B_P0_ GMSL2.
7:1 ...
C
...
...
GMSL1.
0xFF
See the description of SRC_B_P0_C.
I2C_0 (0x670)
BIT 7 6 5 4 3 2 1 0
Field – – SLV_SH_P0_D[1:0] – SLV_TO_P0_D[2:0]
Reset – – 0x2 – 0x6
Access
Type

Link D GMSL1 and GMSL2 I2C-to-I2C Slave
Setup and Hold Time Setting (setup, hold)

I2C slave. 0b00: Fast-mode Plus
5:4
_D Set this according to the I2C speed mode. 0b10: Standard-mode
0b11: Reserved
GMSL2.

GMSL1.
Link D GMSL1 and GMSL2 I2C-to-I2C Slave
Timeout Setting
0b000: 16μs
0b001: 1ms
0b010: 2ms
2:0 remote device.
_D 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_1 (0x671)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P0_D[2:0] – MST_TO_P0_D[2:0]
Access
Type


Link D GMSL1 and GMSL2 I2C-to-I2C Master
Bit Rate Setting
speed
speed
mode speed
6:4 GMSL2 Link D.
_D 3b100: 203Kbps - Set for I2C Fast-mode speed
Plus speed
GMSL1 Link D.
Plus speed
speed
Link D GMSL1 and GMSL2 I2C-to-I2C Master
Timeout Setting
0b000: 16μs
0b001: 1ms
0b010: 2ms
2:0 remote device.
_D 0b100: 8ms
0b101: 16ms
0b110: 32ms
GMSL2.
0b111: Disabled
GMSL1.
I2C_2 (0x672)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P0_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Link D GMSL1 and GMSL2 I2C Address
Translator Source A.
SRC_A_P0_D, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_A_P0_
7:1 DST_A_P0_D. ...
D
...
0xFF
GMSL1.

I2C_3 (0x673)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P0_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Destination A
0x01
0x03
DST_A_P0_ GMSL2.
7:1 ...
D
...
...
GMSL1.
0xFF
See the description of SRC_A_P0_D.
I2C_4 (0x674)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P0_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

Translator Source B
SRC_B_P0_D, internal I2C master (on 0b0000001: Write/read device address is 0x02/
SRC_B_P0_
7:1 DST_B_P0_D. ...
D
...
0xFF
GMSL1.
I2C_5 (0x675)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P0_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


Link D GMSL1 and GMSL2 I2C address
translator destination B.
0x01
0x03
DST_B_P0_ GMSL2.
7:1 ...
D
...
...
GMSL1.
0xFF
See the description of SRC_B_P0_D.
I2C_0 (0x680)
BIT 7 6 5 4 3 2 1 0
I2C_HSM_
Field – SLV_SH_P1_A[1:0] – SLV_TO_P1_A[2:0]
P1
Reset – 0x0 0x2 – 0x6
Access
– Write, Read Write, Read – Write, Read
Type

I2C High-Speed Mode Enable for Port 1 ALL
GMSL2 links.
I2C_HSM_P
6
1
Set this to run I2C at up to 5Mbps on local
side and 3.4Mbps on remote side
GMSL2 I2C-to-I2C Slave Setup and Hold
Time Setting (setup, hold)

5:4 I2C slave.
_A 0b10: Standard-mode
0b11: Reserved

GMSL2 Link A.
GMSL2 I2C-to-I2C Slave Timeout Setting
0b000: 16μs
0b001: 1ms
Internal GMSL2 I2C slave times out after the
0b010: 2ms
2:0 response while waiting for a packet from
_A 0b100: 8ms
remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link A.
I2C_1 (0x681)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P1_A[2:0] – MST_TO_P1_A[2:0]
Access
Type


GMSL2 I2C-to-I2C Master Bit Rate Setting
speed
speed
mode speed
6:4 This setting applies only to I2C Port 1 for
_A 3b100: 203Kbps - Set for I2C Fast-mode speed
GMSL2 Link A.
Plus speed
Plus speed
speed
GMSL2 I2C-to-I2C Master Timeout Setting
0b000: 16μs
0b001: 1ms
Internal GMSL2 I2C master times out after
0b010: 2ms
the configured duration if it does not receive
2:0 any response while waiting for a packet from
_A 0b100: 8ms
the remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link A.
I2C_2 (0x682)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P1_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

GMSL2 I2C Address Translator Source A. 0b0000000: Write/read device address is 0x00/
0x01
When I2C device address matches 0b0000001: Write/read device address is 0x02/
SRC_A_P1_A, internal I2C master (on 0x03
SRC_A_P1_
7:1 remote side) replaces the device address by ...
A
DST_A_P1_A. ...
...
This setting applies only to I2C Port 1 for 0b1111111: Write/read device address is 0xFE/
GMSL2 Link A. 0xFF
I2C_3 (0x683)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P1_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


GMSL2 I2C Address Translator Destination 0x01
A. 0b0000001: Write/read device address is 0x02/
0x03
DST_A_P1_
7:1 This setting applies only to I2C Port 1 for ...
A
GMSL2 Link A. ...
...
See the description of SRC_A_P1_A 0b1111111: Write/read device address is 0xFE/
0xFF
I2C_4 (0x684)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P1_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

GMSL2 I2C Address Translator Source B 0b0000000: Write/read device address is 0x00/
0x01
SRC_B_P1_A, internal I2C master (on 0x03
SRC_B_P1_
A
DST_B_P1_A. ...
...
GMSL2 Link A. 0xFF
I2C_5 (0x685)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P1_A[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

B. 0b0000001: Write/read device address is 0x02/
0x03
DST_B_P1_
A
GMSL2 Link A. ...
...
See the description of SRC_B_P1_A. 0b1111111: Write/read device address is 0xFE/
0xFF

I2C_0 (0x690)
BIT 7 6 5 4 3 2 1 0
Field – – SLV_SH_P1_B[1:0] – SLV_TO_P1_B[2:0]
Reset – – 0x2 – 0x6
Access
Type


5:4 I2C slave.
_B 0b10: Standard-mode
0b11: Reserved

GMSL2 Link B.
0b000: 16μs
0b001: 1ms
0b010: 2ms
_B 0b100: 8ms
remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link B.
I2C_1 (0x691)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P1_B[2:0] – MST_TO_P1_B[2:0]
Access
Type

speed
speed
mode speed
_B 3b100: 203Kbps - Set for I2C Fast-mode speed
GMSL2 Link B.
Plus speed
Plus speed
speed


0b000: 16μs
0b001: 1ms
0b010: 2ms
_B 0b100: 8ms
the remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link B.
I2C_2 (0x692)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P1_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

0x01
SRC_A_P1_B, internal I2C master (on 0x03
SRC_A_P1_
B
DST_A_P1_B ...
...
GMSL2 Link B. 0xFF
I2C_3 (0x693)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P1_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

0x03
DST_A_P1_
B
GMSL2 Link B. ...
...
See the description of SRC_A_P1_B. 0b1111111: Write/read device address is 0xFE/
0xFF

I2C_4 (0x694)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P1_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

GMSL2 I2C Address Translator Source B. 0b0000000: Write/read device address is 0x00/
0x01
SRC_B_P1_B, internal I2C master (on 0x03
SRC_B_P1_
B
DST_B_P1_B. ...
...
GMSL2 Link B. 0xFF
I2C_5 (0x695)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P1_B[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

B. 0b0000001: Write/read device address is 0x02/
0x03
DST_B_P1_
B
GMSL2 Link B. ...
...
See the description of SRC_B_P1_B. 0b1111111: Write/read device address is 0xFE/
0xFF
I2C_0 (0x6A0)
BIT 7 6 5 4 3 2 1 0
Field – – SLV_SH_P1_C[1:0] – SLV_TO_P1_C[2:0]
Reset – – 0x2 – 0x6
Access
Type



5:4 I2C slave.
_C 0b10: Standard-mode
0b11: Reserved

GMSL2 Link C.
0b000: 16μs
0b001: 1ms
0b010: 2ms
_C 0b100: 8ms
remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link C.
I2C_1 (0x6A1)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P1_C[2:0] – MST_TO_P1_C[2:0]
Access
Type

speed
speed
mode speed
_C 3b100: 203Kbps - Set for I2C Fast-mode speed
GMSL2 Link C.
Plus speed
Plus speed
speed
0b000: 16μs
0b001: 1ms
0b010: 2ms
_C 0b100: 8ms
the remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link C.

I2C_2 (0x6A2)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P1_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

0x01
SRC_A_P1_C, internal I2C master (on 0x03
SRC_A_P1_
C
DST_A_P1_C. ...
...
GMSL2 Link C. 0xFF
I2C_3 (0x6A3)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P1_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

0x03
DST_A_P1_
C
GMSL2 Link C. ...
...
See the description of SRC_A_P1_C. 0b1111111: Write/read device address is 0xFE/
0xFF
I2C_4 (0x6A4)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P1_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


GMSL2 I2C Address Translator Source B. 0b0000000: Write/read device address is 0x00/
0x01
SRC_B_P1_C, internal I2C master (on 0x03
SRC_B_P1_
C
DST_B_P1_C. ...
...
GMSL2 Link C. 0xFF
I2C_5 (0x6A5)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P1_C[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

GMSL2 I2C Address Translator Destination
0x01
B.
0x03
DST_B_P1_ This setting applies only to I2C Port 1 for
7:1 ...
C GMSL2 Link C.
...
...
See the description of SRC_B_P1_C.
0xFF
I2C_0 (0x6B0)
BIT 7 6 5 4 3 2 1 0
Field – – SLV_SH_P1_D[1:0] – SLV_TO_P1_D[2:0]
Reset – – 0x2 – 0x6
Access
Type


5:4 I2C slave.
_D 0b10: Standard-mode
0b11: Reserved

GMSL2 Link D.


0b000: 16μs
0b001: 1ms
0b010: 2ms
_D 0b100: 8ms
remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link D.
I2C_1 (0x6B1)
BIT 7 6 5 4 3 2 1 0
Field RSVD MST_BT_P1_D[2:0] – MST_TO_P1_D[2:0]
Access
Type

speed
speed
mode speed
_D 3b100: 203Kbps - Set for I2C Fast-mode speed
GMSL2 Link D.
Plus speed
Plus speed
speed
0b000: 16μs
0b001: 1ms
0b010: 2ms
_D 0b100: 8ms
the remote device.
0b101: 16ms
0b110: 32ms
0b111: Disabled
GMSL2 Link D.
I2C_2 (0x6B2)
BIT 7 6 5 4 3 2 1 0
Field SRC_A_P1_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type


GMSL2 I2C Address Translator Source A 0b0000000: Write/read device address is 0x00/
0x01
SRC_A_P1_D, internal I2C master (on 0x03
SRC_A_P1_
D
DST_A_P1_D. ...
...
GMSL2 Link D. 0xFF
I2C_3 (0x6B3)
BIT 7 6 5 4 3 2 1 0
Field DST_A_P1_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

0x01
GMSL2 I2C Address Translator Destination A
0x03
DST_A_P1_ This setting applies only to I2C Port 1 for
7:1 ...
D GMSL2 Link D.
...
...
See the description of SRC_A_P1_D.
0xFF
I2C_4 (0x6B4)
BIT 7 6 5 4 3 2 1 0
Field SRC_B_P1_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

GMSL2 I2C Address Translator Source B 0b0000000: Write/read device address is 0x00/
0x01
SRC_B_P1_D, internal I2C master (on 0x03
SRC_B_P1_
D
DST_B_P1_D. ...
...
GMSL2 Link D. 0xFF

I2C_5 (0x6B5)
BIT 7 6 5 4 3 2 1 0
Field DST_B_P1_D[6:0] –
Reset 0x0 –
Access
Write, Read –
Type

0x01
GMSL2 I2C Address Translator Destination B
0x03
DST_B_P1_ This setting applies only to I2C Port 1 for
7:1 ...
D GMSL2 Link D.
...
...
See the description of SRC_B_P1_D.
0xFF
PROFILE_MIPI_SEL (0x6E1)
BIT 7 6 5 4 3 2 1 0
Field – – PROFILE_MIPI_SEL[5:0]
Reset – – 0x0
Access
– – Write, Read
Type

Changing PROFILE_SEL automatically
implements the selected profile.
0x0: Default - no configuration registers modified if
Use PROFILE_DISABLE to prevent profiles written to 0
from being implemented. Disables profiles 0x1: Implement profile 1
PROFILE_MI from executing. 0x2: Implement profile 2
5:0
PI_SEL ...
For GMSL1 profiles that use YUV, the ...
yuv_8_10_mux_mode# registers are set to 1. ...
0x10: Implement profile 16
To know exactly which registers are written,
refer to the MAX96724 User Guide.
PROFILE_GMSL_1_0 (0x6EA)
BIT 7 6 5 4 3 2 1 0
Field – PROFILE_GMSL_1[2:0] – PROFILE_GMSL_0[2:0]
Access
Type

PROFILE_GMSL_1 6:4


Register version of the CFG1/MFP6 pin. Configures each GMSL PHY
individually. Directly affects the following registers:
CXTP_A
PROFILE_GMSL_0 2:0 GMSL2_A
RX_RATE_A
HIGHIMM_A
(TERM_CAL_OFFSET)
PROFILE_GMSL_3_2 (0x6EB)
BIT 7 6 5 4 3 2 1 0
Field – PROFILE_GMSL_3[2:0] – PROFILE_GMSL_2[2:0]
Access
Type

PROFILE_GMSL_3 6:4
PROFILE_GMSL_2 2:0
MIPI_TX_EXT0 (0x800, 0x810, 0x820, 0x830)
BIT 7 6 5 4 3 2 1 0
Field MAP_SRC_0_H[2:0] MAP_DST_0_H[2:0] – –
Reset 0x0 0x0 – –
Access
Write, Read Write, Read – –
Type

Video Pipe Extended VC Source Mapping
register 0:
Most Significant 3 bits of Virtual Channel (VC)
Source Mapping register, MAP_SRC_0, for
use in VC extended mode. See MAP_SRC_0
register associated with this Video Pipe.
MAP_SRC_0
7:5 Incoming Video streams whose VC and Data 0bXXX: MS 3 bits of VC mapping for MAP_SRC_0
_H
Type match this setting are mapped to the
VC and Data Type programmed in
MAP_DST_0_H.
Note: Each Video Pipe has 16 distinct

source-to-destination mappings. This register
is the source part of the 0th mapping pair.


Video Pipe Extended VC Destination
Mapping register 0:

Destination mapping register, MAP_DST_0,
for use in VC extended mode. See
MAP_DST_0 register associated with this
MAP_DST_0 Video Pipe. 0bXXX: MS 3 bits of VC destination mapping for
4:2
_H MAP_DST_0
This setting provides the corresponding
destination map associated with the
MAP_SRC_0_H register.

is the destination part of the 0th mapping pair.
MIPI_TX_EXT1 (0x801, 0x811, 0x821, 0x831)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 1:
MAP_SRC_1
_H
MAP_DST_1_H.

is the source part of the 1st mapping pair.


Mapping register 1:
Most significant 3 bits of Virtual Channel (VC)

Video Pipe.
MAP_DST_1 0bXXX: MS 3 bits of VC destination mapping for
4:2
_H MAP_DST_1

is the destination part of the first mapping
pair.
MIPI_TX_EXT2 (0x802, 0x812, 0x822, 0x832)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 2:
MAP_SRC_2
_H
MAP_DST_2_H.

is the source part of the 2nd mapping pair.


Mapping register 2:

Video Pipe.
4:2
_H MAP_DST_2

is the destination part of the second mapping
pair.
MIPI_TX_EXT3 (0x803, 0x813, 0x823, 0x833)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 3:
MAP_SRC_3
_H
MAP_DST_3_H.

is the source part of the 3rd mapping pair.


Mapping register 3:

Video Pipe.
4:2
_H MAP_DST_3

is the destination part of the third mapping
pair.
MIPI_TX_EXT4 (0x804, 0x814, 0x824, 0x834)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 4:
MAP_SRC_4
_H
MAP_DST_4_H.

is the source part of the fourth mapping pair.


Mapping register 4:

Video Pipe.
4:2
_H MAP_DST_4

is the destination part of the fourth mapping
pair.
MIPI_TX_EXT5 (0x805, 0x815, 0x825, 0x835)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 5:
MAP_SRC_5
_H
MAP_DST_5_H.

is the source part of the fifth mapping pair.


Mapping register 5:

Video Pipe.
4:2
_H MAP_DST_5

is the destination part of the fifth mapping
pair.
MIPI_TX_EXT6 (0x806, 0x816, 0x826, 0x836)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 6:
MAP_SRC_6
_H
MAP_DST_6_H.

is the source part of the sixth mapping pair.


Mapping register 6:

Video Pipe.
4:2
_H MAP_DST_6

is the destination part of the sixth mapping
pair.
MIPI_TX_EXT7 (0x807, 0x817, 0x827, 0x837)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 7:
MAP_SRC_7 Incoming Video streams whose VC and Data

7:5 0bXXX: MS 3 bits of VC mapping for MAP_SRC_7
_H Type match this setting are mapped to the
MAP_DST_7_H.

is the source part of the seventh mapping
pair.


Mapping register 7:

Video Pipe.
4:2
_H MAP_DST_7

is the destination part of the seventh mapping
pair.
MIPI_TX_EXT8 (0x808, 0x818, 0x828, 0x838)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 8:
MAP_SRC_8
_H
MAP_DST_8_H.

is the source part of the eighth mapping pair.


Mapping register 8:

Video Pipe.
MAP_DST_8 0XXX: MS 3 bits of VC destination mapping for
4:2
_H MAP_DST_8

is the destination part of the eighth mapping
pair.
MIPI_TX_EXT9 (0x809, 0x819, 0x829, 0x839)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 9:
MAP_SRC_9
_H
MAP_DST_9_H.

is the source part of the ninth mapping pair.


Mapping register 9:

Video Pipe.
4:2
_H MAP_DST_9

is the destination part of the ninth mapping
pair.
MIPI_TX_EXT10 (0x80A, 0x81A, 0x82A, 0x83A)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 10:
use in VC extended mode. See
MAP_SRC_10 register associated with this
Video Pipe.
MAP_SRC_1 0bXXX: MS 3 bits of VC mapping for
7:5
0_H Incoming Video streams whose VC and Data MAP_SRC_10
MAP_DST_10_H.

is the source part of the tenth mapping pair.


Mapping register 10:

Video Pipe.
4:2
0_H MAP_DST_10

is the destination part of the tenth mapping
pair.
MIPI_TX_EXT11 (0x80B, 0x81B, 0x82B, 0x83B)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 11:
Video Pipe.
7:5 Incoming Video streams whose VC and Data
1_H MAP_SRC_11
MAP_DST_11_H.

is the source part of the eleventh mapping
pair.



Video Pipe.
4:2
1_H MAP_DST_11

is the destination part of the eleventh
mapping pair.
MIPI_TX_EXT12 (0x80C, 0x81C, 0x82C, 0x83C)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 12:
Video Pipe.
7:5
2_H Incoming Video streams whose VC and Data MAP_SRC_12
MAP_DST_12_H.

is the source part of the twelfth mapping pair.



Video Pipe.
4:2
2_H MAP_DST_12

is the destination part of the twelfth mapping
pair.
MIPI_TX_EXT13 (0x80D, 0x81D, 0x82D, 0x83D)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 13:
Video Pipe.
3_H MAP_SRC_13
MAP_DST_13_H.

is the source part of the thirteenth mapping
pair.



Video Pipe.
4:2
3_H MAP_DST_13

is the destination part of the thirteenth
mapping pair.
MIPI_TX_EXT14 (0x80E, 0x81E, 0x82E, 0x83E)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 14:
Video Pipe.
4_H MAP_SRC_14
MAP_DST_14_H.

is the source part of the fourteenth mapping
pair.



Video Pipe.
4:2
4_H MAP_DST_14

is the destination part of the fourteenth
mapping pair.
MIPI_TX_EXT15 (0x80F, 0x81F, 0x82F, 0x83F)
BIT 7 6 5 4 3 2 1 0
Access
Type

register 15:
Video Pipe.
5_H MAP_SRC_15
MAP_DST_15_H.

is the source part of the fifteenth mapping
pair.



Video Pipe.
4:2
5_H MAP_DST_15

is the destination part of the fifteenth mapping
pair.
MIPI_PHY0 (0x8A0)
BIT 7 6 5 4 3 2 1 0
force_csi_o force_clk3_ force_clk0_ phy_1x4b_2 phy_1x4a_2
Field phy_2x4 RSVD phy_4x2
ut_en en en 2 2
Reset 0b0 0b0 0b0 0b0 0b0 0b1 0b0 0b0
Access
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Type

force_csi_out 0b0: Normal mode
7 Set to force all MIPI clocks running.
_en 0b1: Force all MIPI clocks running
force_clk3_e 0b0: DPHY0 not enabled as clock
6 Set to force PHY3 MIPI clock running.
n 0b1: DPHY0 not enabled as clock
force_clk0_e 0b0: DPHY0 not enabled as clock
5 Set to force PHY0 MIPI clock running.
n 0b1: DPHY0 not enabled as clock
MIPI PHY 1x4b + 2x2 mode:
MIPI output configured as one 4-lane port
0b0: 2x4 not selected
phy_1x4b_22 4 and two 2-lane ports. PHY2 and PHY3
0b1: 2x4 selected
combined as 4-lane. PHY0 and PHY1 are
2-lane ports
MIPI PHY 1x4a + 2x2 mode:
MIPI output configured as one 4-lane port
0b0: 2x4 not selected
phy_1x4a_22 3 and two 2-lane ports. PHY0 and PHY1
0b1: 2x4 selected
combined as 4-lane. PHY2 and PHY3 are
2-lane ports
MIPI PHY 2x4 mode:
MIPI output configured as two ports with four 0b0: 2x4 not selected
phy_2x4 2
data lanes each. PHY0 and PHY1 combined, 0b1: 2x4 selected
and PHY2 and PHY3 combined.
MIPI PHY 4x2 mode:
0b0: 4x2 configuration not selected
phy_4x2 0 MIPI output configured as four 2-lane MIPI
0b1: 4x2 configuration selected
ports.

MIPI_PHY1 (0x8A1)
BIT 7 6 5 4 3 2 1 0
Field t_hs_przero[1:0] t_hs_prep[1:0] t_clk_trail[1:0] t_clk_przero[1:0]
Access
Type

0b00: 146ns + 24UI
Typical DPHY data lane HS_prep + HS_zero 0b01: 160ns + 24UI
t_hs_przero 7:6
timing 0b10: 173ns + 24UI
0b11: 200ns + 24UI
0b00: 46.7ns + 4UI
Typical DPHY data lane HS_prepare 0b01: 53.4ns + 4UI
t_hs_prep 5:4
timing 0b10: 60.0ns + 4UI
0b11: 66.7ns + 4UI
0b00: 160ns
0b01: 167ns
t_clk_trail 3:2 Typical DPHY clock HS_trail timing
0b10: 173ns
0b11: 180ns
0b00: 306ns
Typical DPHY clock lane HS_prepare + 0b01: 600ns
t_clk_przero 1:0
HS_zero timing 0b10: 900ns
0b11: 1200ns
MIPI_PHY2 (0x8A2)
BIT 7 6 5 4 3 2 1 0
Field phy_Stdby_n[3:0] t_lpx[1:0] t_hs_trail[1:0]
Reset 0xF 0x1 0x0
Access
Type

0bXXX0: Put MIPI PHY0 in standby mode
MIPI PHY Enable
0bXXX1: Enable MIPI PHY0
0bXX0X: Put MIPI PHY1 in standby mode
bit [7]: Enable MIPI PHY3
0bXX1X: Enable MIPI PHY1
phy_Stdby_n 7:4 bit [6]: Enable MIPI PHY2
0bX0XX: Put MIPI PHY2 in standby mode
0bX1XX: Enable MIPI PHY2
0b0XXX: Put MIPI PHY3 in standby mode
0b1XXX: Enable MIPI PHY3
0b00: 53.4ns
0b01: 106.7ns
t_lpx 3:2 Typical DPHY tLPX timing
0b10: 160ns
0b11: 213.4ns
0b00: 66.7ns + 8UI
0b01: 80ns + 8UI
t_hs_trail 1:0 Typical DPHY data lane HS_trail timing
0b10: 93.4ns + 8UI
0b11: 106.7ns + 8UI

MIPI_PHY3 (0x8A3)
BIT 7 6 5 4 3 2 1 0
Field phy1_lane_map[3:0] phy0_lane_map[3:0]
Reset 0xE 0x4
Access
Type

MIPI PHY1 lane mapping register:
bits [5:4]: Set PHY1 D0 Output mapping
The settings for these bit fields are dependent

upon the settings for the MIPI configuration.
See register fields in MIPI_PHY0 (0x8A0).
For MIPI configurations 4x2 and (1x4b+2x2),

the following mappings apply:
2’b00 = Map PHY Output to data lane D0
0bXX00: Map D0 to data lane D0
Note: CSI-2 Controller 1 is mapped to PHY1
phy1_lane_m 0bXX11: Map D0 to data lane D3
7:4 for MIPI configurations 4x2 and (1x4b+2x2).
ap 0b00XX: Map D1 to data lane D0
0b01XX: Map D1 to data lane D1
For MIPI configurations 2x4 and (1x4a+2x2),
Note: CSI-2 Controller 1 is mapped to both
PHY0 and PHY1 for MIPI configurations 2x4
and (1x4a+2x2). CSI-2 Controller 0 is
unused.
In 4x2 mode, phy#_lane_map register bits [3]

and [1] will always read back 1'b0 since
hardware will mask them to 1'b0 in this mode.




2’b10 = RSVD, do not use
3:0 2’b11 = RSVD, do not use
for MIPI configurations 4x2 and (1x4b+2x2).
and (1x4a+2x2). CSI-2 Controller 0 is
unused.
MIPI_PHY4 (0x8A4)
BIT 7 6 5 4 3 2 1 0
Field phy3_lane_map[3:0] phy2_lane_map[3:0]
Reset 0xE 0x4
Access
Type




2’b10 = RSVD, do not use
7:4 2’b11 = RSVD, do not use
for MIPI configurations 4x2 and (1x4a+2x2).
and (1x4b+2x2). CSI-2 Controller 3 is
unused.


2’b00 = Map PHY Output to data lane D0 0bXX00: Map D0 to data lane D0
phy2_lane_m 2’b11 = Map PHY Output to data lane D3 0bXX11: Map D0 to data lane D3
3:0
ap Note: CSI-2 Controller 2 is mapped to PHY2 0b00XX: Map D1 to data lane D0
for MIPI configurations 4x2 and (1x4a+2x2). 0b01XX: Map D1 to data lane D1
For MIPI configurations 2x4 and (1x4b+2x2), 0b11XX: Map D1 to data lane D3
and (1x4b+2x2). CSI-2 Controller 3 is
unused.

MIPI_PHY5 (0x8A5)
BIT 7 6 5 4 3 2 1 0
Field t_clk_prep[1:0] phy1_pol_map[2:0] phy0_pol_map[2:0]
Reset 0x0 0x0 0x0
Access
Type

0b00: 40ns
0b01: 46.7ns
t_clk_prep 7:6 Typical DPHY clock lane HS_prepare timing
0b10: 53.4ns
0b11: 60ns
0bXX0: D0 normal polarity, P is positive, N is
negative
0bXX1: D0 inverse polarity, P is negative, N is
MIPI PHY1 lane polarity register: positive
bit [5]: Set polarity on PHY1 CLK lane 0bX0X: D1 normal polarity, P is positive, N is
phy1_pol_ma bit [4]: Set polarity on PHY1 D1 lane negative
5:3
p bit [3]: Set polarity on PHY1 D0 lane 0bX1X: D1 inverse polarity, P is negative, N is
1’b0 = normal polarity, 1’b1 = inversed positive
polarity 0b0XX: CK normal polarity, P is positive, N is
negative
0b1XX: CK inverse polarity, P is negative, N is
positive
negative
2:0
negative
positive
MIPI_PHY6 (0x8A6)
BIT 7 6 5 4 3 2 1 0
Field – – phy3_pol_map[2:0] phy2_pol_map[2:0]
Reset – – 0x0 0x0
Access
Type


negative
5:3
negative
positive
negative
2:0
negative
positive
MIPI_PHY8 (0x8A8)
BIT 7 6 5 4 3 2 1 0
Field t_lpxesc[2:0] RSVD RSVD RSVD RSVD RSVD
Reset 0x0 0b0 0b0 0b0 0b0
Access
Write, Read
Type

0b000: 66.67ns
0b001: 80ns
0b010: 100ns
0b011: 133ns
t_lpxesc 7:5 Typical DPHY tLPX timing in escape mode
0b100: 200ns
0b101: 400ns
0b110: 1000ns
0b111: 2000ns
MIPI_PHY9 (0x8A9)
BIT 7 6 5 4 3 2 1 0
Field phy_cp0[4:0] – RSVD RSVD
Access
Write, Read –
Type


PHY copy 0, replicates data from source PHY [4:3]: PHY copy 0 source
phy_cp0 7:3 to destination PHY (valid source and [6:5]: PHY copy 0 destination
destinations are PHY 0 and 1 only) [7]: PHY copy 0 enable
MIPI_PHY10 (0x8AA)
BIT 7 6 5 4 3 2 1 0
Field phy_cp1[4:0] – RSVD RSVD
Access
Write, Read –
Type

PHY copy 1, replicates data from source PHY [4:3]: PHY copy 0 source
phy_cp1 7:3 to destination PHY (valid source and [6:5]: PHY copy 0 destination
destinations are PHY 2 and 3 only) [7]: PHY copy 0 enable
MIPI_PHY11 (0x8AB)
BIT 7 6 5 4 3 2 1 0
Field phy_cp_err[3:0] – – RSVD –
Reset 0x00 – – 0b0 –
Access
Read Only – – –
Type

0bXXX1: PHY copy 0 FIFO overflow
0bXX1X: PHY copy 0 FIFO underflow
phy_cp_err 7:4
0bX1XX: PHY copy 1 FIFO overflow
0b1XXX: PHY copy 1 FIFO underflow
MIPI_PHY13 (0x8AD)
BIT 7 6 5 4 3 2 1 0
Field – – t_t3_prebegin[5:0]
Reset – – 0x1F
Access
– – Write, Read
Type

0b000000: 7UI
0b000001: 14UI
...
t_t3_prebegi CPHY pre-begin phase of the preamble
5:0 ...
n (t3_prebegin + 1) x 7UI
...
0b111110: 441UI
0B111111: 448UI

MIPI_PHY14 (0x8AE)
BIT 7 6 5 4 3 2 1 0
Field – t_t3_post[4:0] t_t3_prep[1:0]
Reset – 0x17 0x1
Access
Type

CPHY post length after HS data = (t3_post +
t_t3_post 6:2 0bXXXXX: CPHY post length
1) x 7UI
0b00: 40ns
0b01: 55ns
t_t3_prep 1:0 CPHY Ths_prepare timing
0b10: 66.7ns
0b11: 86.7ns
MIPI_PHY16 (0x8B0)
BIT 7 6 5 4 3 2 1 0
TUN_CONV
TUN_DATA TUN_ECC_ TUN_ECC_
_DATA_CR
Field – _CRC_ERR UNCORR_ CORR_ER – – –
C_ERR_OE
_OEN ERR_OEN R_OEN
N
Reset – 0x1 0x1 0b1 0b1 – – –
Access
– Write, Read Write, Read Write, Read Write, Read – – –
Type

TUN_CONV_
For tunneling mode, enable reporting at 0x0: Errorr not forwarded to ERRB pin
DATA_CRC_ 6
ERRB pin of DPHY/CPHY data CRC errors 0x1: Error reporting forwarded to ERRB pin
ERR_OEN
TUN_DATA_
For tunneling mode, enable reporting at 0x0: Errorr not forwarded to ERRB pin
CRC_ERR_ 5
ERRB pin of DPHY/CPHY data CRC errors 0x1: Error reporting forwarded to ERRB pin
OEN
TUN_ECC_U For tunneling mode, enable reporting at
0x0: Errorr not forwarded to ERRB pin
NCORR_ER 4 ERRB pin of uncorrectable errors on DPHY
0x1: Error reporting forwarded to ERRB pin
R_OEN ECC or CPHY header CRC
TUN_ECC_C For tunneling mode, enable reporting at
0x0: Errorr not forwarded to ERRB pin
ORR_ERR_ 3 ERRB pin of correctable errors on DPHY
0x1: Error reporting forwarded to ERRB pin
OEN ECC or CPHY header CRC
MIPI_PHY17 (0x8B1)
BIT 7 6 5 4 3 2 1 0
TUN_CONV TUN_ECC_ TUN_ECC_
TUN_DATA
Field – _DATA_CR UNCORR_ CORR_ER – – –
_CRC_ERR
C_ERR ERR R
Reset – 0b0 0b0 0b0 0b0 – – –
Access
– Read Only Read Only Read Only Read Only – – –
Type


For tunneling mode, DPHY to CPHY
TUN_CONV_ conversion (header) data CRC errors
0x0: no Error Detected
DATA_CRC_ 6
0x1: Error Detected
ERR Combined for all MIPI PHYs. Read individual
MIPI_TX STATUS registers to clear.
For tunneling mode, DPHY/CPHY data CRC
errors
TUN_DATA_ 0x0: no Error Detected
5
CRC_ERR 0x1: Error Detected
Combined for all MIPI PHYs. Read individual
For tunneling mode, uncorrectable errors on
TUN_ECC_U DPHY ECC or CPHY header CRC
0x0: no Error Detected
NCORR_ER 4
0x1: Error Detected
R Combined for all MIPI PHYs. Read individual
For tunneling mode, correctable errors on
DPHY ECC or CPHY header CRC.
TUN_ECC_C 0x0: no Error Detected
3
ORR_ERR 0x1: Error Detected
Combined for all MIPI PHYs. Read individual
MIPI_PHY18 (0x8B2)
BIT 7 6 5 4 3 2 1 0
csipll3_PLL csipll3_PLL csipll2_PLL csipll2_PLL csipll1_PLL csipll1_PLL csipll0_PLL csipll0_PLL
Field
ORangeH ORangeL ORangeH ORangeL ORangeH ORangeL ORangeH ORangeL
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type

csipll3_PLLO Live status bit that indicates csipll3 is above 0x0: within range
7
RangeH range. 0x1: indicates csipll is above range
csipll3_PLLO Live status bit that indicates csipll3 is below 0x0: within range
6
RangeL range. 0x1: indicates csipll is below range.
5
4
3
2
1
0

MIPI_PHY19 (0x8B3)
BIT 7 6 5 4 3 2 1 0
Field ORangeH_fl ORangeL_fl ORangeH_fl ORangeL_fl ORangeH_fl ORangeL_fl ORangeH_fl ORangeL_fl
ag ag ag ag ag ag ag ag
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access Read Read Read Read Read Read Read Read
Type Clears All Clears All Clears All Clears All Clears All Clears All Clears All Clears All

Sticky flag that indicates csipll3 was above 0x0: within range
csipll3_PLLO
7 range at some point since last cleared (or 0x1: Sticky flag that indicates csipll was above
RangeH_flag
since device was reset). Read clears the flag. range. Read clears.
Sticky flag that indicates csipll3 was below 0x0: within range
csipll3_PLLO
6 range at some point since last cleared (or 0x1: Sticky flag that indicates csipll was below
RangeL_flag
csipll2_PLLO
RangeH_flag
csipll2_PLLO
RangeL_flag
csipll1_PLLO
RangeH_flag
csipll1_PLLO
RangeL_flag
csipll0_PLLO
RangeH_flag
csipll0_PLLO
RangeL_flag
MIPI_PHY20 (0x8B4)
BIT 7 6 5 4 3 2 1 0
Field ORangeH_ ORangeL_o ORangeH_ ORangeL_o ORangeH_ ORangeL_o ORangeH_ ORangeL_o
oen en oen en oen en oen en
Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1
Access
Type

0x0: csipll3_PLLORangeH_flag does NOT
This register controls whether
csipll3_PLLO contribute to ERROR condition
7 csipll3_PLLORangeH_flag contributes to the
RangeH_oen 0x1: csipll3_PLLORangeH_flag is ORed with other
setting of ERROR.
flags to set ERROR condition


0x0: csipll3_PLLORangeL_flag does NOT
6 csipll3_PLLORangeL_flag contributes to the
RangeL_oen 0x1: csipll3_PLLORangeL_flag is ORed with other
setting of ERROR.
setting of ERROR.
setting of ERROR.
setting of ERROR.
setting of ERROR.
setting of ERROR.
setting of ERROR.
MIPI_PRBS_0 (0x8C0)
BIT 7 6 5 4 3 2 1 0
MIPI_PRBS_EN_P1_LN1[ MIPI_PRBS_EN_P1_LN0[ MIPI_PRBS_EN_P0_LN1[ MIPI_PRBS_EN_P0_LN0[
Field
1:0] 1:0] 1:0] 1:0]
Access
Type

0b00: Disabled
MIPI_PRBS_ PRBS enable for PHY1 lane 1 eye diagram. 0b01: PRBS 9 enabled
7:6
EN_P1_LN1 Set CPHY enable for CPHY symbols. 0b10: PRBS 11 enabled
0b11: PRBS 18 enabled
0b00: Disabled
5:4
0b00: Disabled
3:2


0b00: Disabled
1:0
MIPI_PRBS_1 (0x8C1)
BIT 7 6 5 4 3 2 1 0
MIPI_PRBS_EN_P3_LN1[ MIPI_PRBS_EN_P3_LN0[ MIPI_PRBS_EN_P2_LN1[ MIPI_PRBS_EN_P2_LN0[
Field
1:0] 1:0] 1:0] 1:0]
Access
Type

0b00: Disabled
7:6
0b00: Disabled
5:4
0b00: Disabled
3:2
0b00: Disabled
1:0
MIPI_PRBS_2 (0x8C2)
BIT 7 6 5 4 3 2 1 0
MIPI_CUST MIPI_CUST MIPI_CUST MIPI_CUST MIPI_CUST MIPI_CUST MIPI_CUST MIPI_CUST
Field _SEED_EN _SEED_EN _SEED_EN _SEED_EN _SEED_EN _SEED_EN _SEED_EN _SEED_EN
_P3_LN1 _P3_LN0 _P2_LN1 _P2_LN0 _P1_LN1 _P1_LN0 _P0_LN1 _P0_LN0
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Type

MIPI_CUST_
Use custom seed for reset value of PRBS 0b0: Disabled
SEED_EN_P 7
generator. 0b1: Enabled
3_LN1
MIPI_CUST_
SEED_EN_P 6
3_LN0
MIPI_CUST_
SEED_EN_P 5
2_LN1


MIPI_CUST_
SEED_EN_P 4
2_LN0
MIPI_CUST_
SEED_EN_P 3
1_LN1
MIPI_CUST_
SEED_EN_P 2
1_LN0
MIPI_CUST_
SEED_EN_P 1
0_LN1
MIPI_CUST_
SEED_EN_P 0
0_LN0
MIPI_PRBS_3 (0x8C3)
BIT 7 6 5 4 3 2 1 0
MIPI_CUSTOM_SEED_2[
Field RSVD RSVD RSVD RSVD – –
1:0]
Reset 0b1 0b1 0b1 0b1 – – 0x2
Access
– – Write, Read
Type

Custom seed [17:16] for MIPI PRBS eye
MIPI_CUST diagrams. Reset value for PRBS if enabled Bits [17:16]: Reset value for PRBS if enabled by
1:0
OM_SEED_2 by MIPI custom seed enable register. Default MIPI custom seed enable register
reset is from CPHY spec.
MIPI_PRBS_4 (0x8C4)
BIT 7 6 5 4 3 2 1 0
Field MIPI_CUSTOM_SEED_1[7:0]
Reset 0x78
Access
Write, Read
Type

MIPI_CUST diagrams. Reset value for PRBS if enabled Bits [15:8]: Reset value for PRBS if enabled by
7:0
OM_SEED_1 by MIPI custom seed enable register. Default MIPI custom seed enable register

MIPI_PRBS_5 (0x8C5)
BIT 7 6 5 4 3 2 1 0
Field MIPI_CUSTOM_SEED_0[7:0]
Reset 0x9a
Access
Write, Read
Type

MIPI_CUST diagrams. Reset value for PRBS if enabled Bits [7:0]: Reset value for PRBS if enabled by MIPI
7:0
OM_SEED_0 by MIPI custom seed enable register. Default custom seed enable register
MIPI_PHY21 (0x8C6)
BIT 7 6 5 4 3 2 1 0
Field Force_Video_Mask[3:0] Auto_Mask_En[3:0]
Reset 0x0 0xF
Access
Type

0bXXX1: Force video from Video Pipe 0 to be
Forces video output to be masked (send all masked.
0's) in 4WxH or Wx4H synchronous 0bXX1X: Force video from Video Pipe 1 to be
Force_Video aggregation modes. masked.
7:4
_Mask 0bX1XX: Force video from Video Pipe 2 to be
Masking impacts video streams from video masked.
pipes 0-3. 0b1XXX: Force video from Video Pipe 3 to be
masked.
0bXXX1: Auto video mask enabled for Video Pipe
Auto Video Mask Enable
0
0bXX1X: Auto video mask enabled for Video Pipe
Automatically insert 0s into synchronized
Auto_Mask_ 1
3:0 aggregated video outputs if a Video Pipe 0-3
En 0bX1XX: Auto video mask enabled for Video Pipe
video lock is lost. This allows the other video
2
streams to continue being transmitted on the
0b1XXX: Auto video mask enabled for Video Pipe
MIPI interface.
3
MIPI_PHY22 (0x8C7)
BIT 7 6 5 4 3 2 1 0
Video_Mask
Field _Latch_Res – – – Video_Mask_Restart_En[3:0]
et
Reset 0b0 – – – 0xF
Access Write Clears
Type All, Read

Reset all Video_Mask_Latched latches. Write
Video_Mask_ 0x0: No action
7 1 to activate reset, bit self clears and
Latch_Reset 0x1: Reset latches


0bXXX1: Restart video from Video Pipe 0
Automatically restarts video streams that
Video_Mask_ 0bXX1X: Restart video from Video Pipe 1
3:0 were previously masked off due to loss of
Restart_En 0bX1XX: Restart video from Video Pipe 2
video lock
0b1XXX: Restart video from Video Pipe 3
MIPI_PHY24 (0x8C9)
BIT 7 6 5 4 3 2 1 0
Field – – – – RST_MIPITX_LOC[3:0]
Reset – – – – 0x0
Access
Type

0bxxx0: Controller 0 reset not asserted
Active high reset to MIPI controllers. Disabled 0bxxx1: Controller 0 reset asserted
by asserting DP_RST_MIPI. 0bxx0x: Controller 1 reset not asserted
RST_MIPITX Bit 0: Controller 0 reset 0bxx1x: Controller 1 reset asserted
3:0
_LOC Bit 1: Controller 1 reset 0bx0xx: Controller 2 reset not asserted
Bit 2: Controller 2 reset 0bx1xx: Controller 2 reset asserted
Bit 3: Controller 3 reset 0b0xxx: Controller 3 reset not asserted
0b1xxx: Controller 3 reset asserted
MIPI_CTRL_SEL (0x8CA)
BIT 7 6 5 4 3 2 1 0
Field MIPI_CTRL_SEL_3[1:0] MIPI_CTRL_SEL_2[1:0] MIPI_CTRL_SEL_1[1:0] MIPI_CTRL_SEL_0[1:0]
Access
Type

Selects target MIPI Controller for video pipe 3
0b0: (Default) Rev B behavior – All MIPI controllers
This can be used in place of the FCFS
will be reset during any one-shot reset or link reset
MAP_SRC and MAP_DST registers to re-
MIPI_CTRL_ 0b1: Rev C behavior – Each MIPI controller can be
7:6 map everything. Using this register will map
SEL_3 reset automatically based on the associated GMSL
everything by default, then the user can re-
PHY and Video Pipe reset during a one-shot reset
map specific data types to other controllers
or link reset
as before.
or link reset
as before.
or link reset
as before.


map everything. Using this register will map
map specific data types to other controllers 0b0: (Default) Rev B behavior – All MIPI controllers
as before. will be reset during any one-shot reset or link reset
MIPI_CTRL_ Note: The MIPI CRTL reset logic from 0b1: Rev C behavior – Each MIPI controller can be
1:0
SEL_0 RESET_LINK uses the mapping registers. If reset automatically based on the associated GMSL
only MIPI_CTRL_SEL is used for mapping, PHY and Video Pipe reset during a one-shot reset
then the reset logic may not work as or link reset
expected because it does not know which
controller to reset. In other words,
RESET_LINK_0 will reset CTRL0 and
RESET_LINK_1 will reset CTRL_1, unless
only the mapping registers are used.
MIPI_PHY25 (0x8D0)
BIT 7 6 5 4 3 2 1 0
Field csi2_tx1_pkt_cnt[3:0] csi2_tx0_pkt_cnt[3:0]
Reset 0x00 0x00
Access
Read Only Read Only
Type

csi2_tx1_pkt_cnt 7:4 Packet count of CSI2 Controller 1
csi2_tx0_pkt_cnt 3:0 Packet count of CSI2 Controller 0
MIPI_PHY26 (0x8D1)
BIT 7 6 5 4 3 2 1 0
Field csi2_tx3_pkt_cnt[3:0] csi2_tx2_pkt_cnt[3:0]
Reset 0x00 0x00
Access
Read Only Read Only
Type

csi2_tx3_pkt 0bXXXX: Toggling bits indicate MIPI data is active
7:4 Packet count of CSI2 Controller 3
_cnt on controller 3
csi2_tx2_pkt 0bXXXX: Toggling bits indicate MIPI data is active
3:0 Packet count of CSI2 Controller 2
_cnt on controller 2
MIPI_PHY27 (0x8D2)
BIT 7 6 5 4 3 2 1 0
Field phy1_pkt_cnt[3:0] phy0_pkt_cnt[3:0]
Reset 0x00 0x00
Access
Read Only Read Only
Type


0bXXXX: Toggling bits indicate MIPI data is active
phy1_pkt_cnt 7:4 Packet count of MIPI PHY1
on PHY 1
on PHY 0
MIPI_PHY28 (0x8D3)
BIT 7 6 5 4 3 2 1 0
Field phy3_pkt_cnt[3:0] phy2_pkt_cnt[3:0]
Reset 0x00 0x00
Access
Read Only Read Only
Type

on PHY 3
on PHY 2
MIPI_PHY_CP_ERR_OE (0x8D4)
BIT 7 6 5 4 3 2 1 0
PHY_CP1_ PHY_CP1_ PHY_CP0_ PHY_CP0_
Field UF_ERR_O OV_ERR_O UF_ERR_O OV_ERR_O – – – –
EN EN EN EN
Reset 0b1 0b1 0b1 0b1 – – – –
Access
Type

Enable Reflection of phy_cp_err[3] onto the
PHY_CP1_U ERRB pin. This corresponds to the PHY copy 0x0: Mask error from ERRB pin
7
F_ERR_OEN 1 FIFO underflow error. See the phy_cp_err 0x1: Enable error onto ERRB pin
register field bit 3. (bit 7 of register byte)
PHY_CP1_O ERRB pin. This corresponds to the PHY copy 0x0: Mask error from ERRB pin
6
V_ERR_OEN 1 FIFO overflow error. See the phy_cp_err 0x1: Enable error onto ERRB pin
PHY_CP0_U ERRB pin. This corresponds to the PHY copy 0x0: Mask error from ERRB pin
5
F_ERR_OEN 0 FIFO underflow error. See the phy_cp_err 0x1: Enable error onto ERRB pin
PHY_CP0_O ERRB pin. This corresponds to the PHY copy 0x0: Mask error from ERRB pin
4
V_ERR_OEN 0 FIFO overflow error. See the phy_cp_err 0x1: Enable error onto ERRB pin

MIPI_PHY_FLAGS (0x8D5)
BIT 7 6 5 4 3 2 1 0
DESKEW_ DESKEW_ DESKEW_ DESKEW_
START_OV START_OV START_OV START_OV
Field – – – –
ERLAP_FL ERLAP_FL ERLAP_FL ERLAP_FL
AG_3 AG_2 AG_1 AG_0
Reset – – – – 0b0 0b0 0b0 0b0
Access Read Read Read Read
– – – –
Type Clears All Clears All Clears All Clears All

Error flag that indicates that the MIPI
controller tried to start outputing data while
DESKEW_S
initial deskew was still running.
TART_OVER 0x0: No error
3
LAP_FLAG_ 0x1: Initial deskew and tx_start overlapped.
Either speed up the MIPI output so the
3
deskew finishes sooner or increase
n_vs_block.
DESKEW_S
2
2
n_vs_block.
DESKEW_S
1
1
n_vs_block.
DESKEW_S
0
0
n_vs_block.
MIPI_PHY_OEN (0x8D6)
BIT 7 6 5 4 3 2 1 0
DESKEW_ DESKEW_ DESKEW_ DESKEW_
START_OV START_OV START_OV START_OV
Field – – – –
ERLAP_OE ERLAP_OE ERLAP_OE ERLAP_OE
N_3 N_2 N_1 N_0
Reset – – – – 0b1 0b1 0b1 0b1
Access
Type


0x0: Does not affect ERRB pin.
DESKEW_S Enable
0x1: Enable
TART_OVER 3 DESKEW_START_OVERLAP_ERR_FLAG
DESKEW_START_OVERLAP_ERR_FLAG to go
LAP_OEN_3 to go to ERRB pin.
to ERRB pin.
DESKEW_S Enable
0x1: Enable
to ERRB pin.
DESKEW_S Enable
0x1: Enable
to ERRB pin.
DESKEW_S Enable
0x1: Enable
to ERRB pin.
MIPI_ERR_PKT_0 (0x8D8)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
Field – ERR_PKT_DT_0[5:0]
EN_0
Reset 0b0 – 0x3E
Access
Type

Enable output of special MIPI Error Packet
when uncorrectable header errors occur in
ERR_PKT_E 0x0: Disabled
7 Tunnel Mode for MIPI controller 0.
N_0 0x1: Enabled
0 = Disabled
1 = Enabled
Specifies the MIPI Data Type for the special
MIPI Error Packet which is output when
uncorrectable header errors occur in Tunnel
ERR_PKT_D 0x0
5:0 Mode.
T_0 0x1: Datatype value
Must be enabled using the ERR_PKT_EN
control.
See the ERR_PKT_EN register field.
MIPI_ERR_PKT_1 (0x8D9)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
EN_1
Reset 0b0 – 0x3E
Access
Type


N_1 0x1: Enabled
0 = Disabled
1 = Enabled
ERR_PKT_D 0x0
5:0 Mode.
control.
MIPI_ERR_PKT_2 (0x8DA)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
EN_2
Reset 0b0 – 0x3E
Access
Type

N_2 0x1: Enabled
0 = Disabled
1 = Enabled
ERR_PKT_D 0x0
5:0 Mode.
control.
MIPI_ERR_PKT_3 (0x8DB)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
EN_3
Reset 0b0 – 0x3E
Access
Type

N_3 0x1: Enabled
0 = Disabled
1 = Enabled


ERR_PKT_D 0x0
5:0 Mode.
control.
MIPI_ERR_PKT_4 (0x8DC)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
Field VC_OVRD_ – – ERR_PKT_VC_OVRD_0[4:0]
EN_0
Access
Type

Enable virtual channel override value for 0x0: Use VC of random video stream in current
ERR_PKT_V
special MIPI Error Packet when uncorrectable controller
C_OVRD_E 7
header errors occur in Tunnel Mode for MIPI 0x1: Use VC specified in ERR_PKT_VC_OVRD_0
N_0
controller 0. register
0x0: 0x0
0x1: 0x1
0x2: 0x2
0x3: 0x3
0x4: 0x0
0x5: 0x1
0x6: 0x2
0x7: 0x3
0x8: 0x0
0x9: 0x1
0xA: 0x2
0xB: 0x3
0xC: 0x0
Specifies the MIPI Virtual Channel for the
0xD: 0x1
special MIPI Error Packet which is output
0xE: 0x2
ERR_PKT_V 0xF: 0x3
4:0 Tunnel Mode.
C_OVRD_0 0x10: 0x0
Must be enabled using the ERR_PKT_EN_0
0x11: 0x1
and ERR_PKT_VC_OVRD_EN_0.
0x12: 0x2
See the ERR_PKT_EN_0 register field.
0x13: 0x3
0x14: 0x0
0x15: 0x1
0x16: 0x2
0x17: 0x3
0x18: 0x0
0x19: 0x1
0x1A: 0x2
0x1B: 0x3
0x1C: 0x0
0x1D: 0x1
0x1E: 0x2
0x1F: 0x3

MIPI_ERR_PKT_5 (0x8DD)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
EN_1
Access
Type

ERR_PKT_V
C_OVRD_E 7
N_1
0x0: 0x0
0x1: 0x1
0x2: 0x2
0x3: 0x3
0x4: 0x0
0x5: 0x1
0x6: 0x2
0x7: 0x3
0x8: 0x0
0x9: 0x1
0xA: 0x2
0xB: 0x3
0xC: 0x0
0xD: 0x1
0xE: 0x2
ERR_PKT_V 0xF: 0x3
4:0 Tunnel Mode.
C_OVRD_1 0x10: 0x0
0x11: 0x1
0x12: 0x2
0x13: 0x3
0x14: 0x0
0x15: 0x1
0x16: 0x2
0x17: 0x3
0x18: 0x0
0x19: 0x1
0x1A: 0x2
0x1B: 0x3
0x1C: 0x0
0x1D: 0x1
0x1E: 0x2
0x1F: 0x3

MIPI_ERR_PKT_6 (0x8DE)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
EN_2
Access
Type

ERR_PKT_V
C_OVRD_E 7
N_2
0x0: 0x0
0x1: 0x1
0x2: 0x2
0x3: 0x3
0x4: 0x0
0x5: 0x1
0x6: 0x2
0x7: 0x3
0x8: 0x0
0x9: 0x1
0xA: 0x2
0xB: 0x3
0xC: 0x0
0xD: 0x1
0xE: 0x2
ERR_PKT_V 0xF: 0x3
4:0 Tunnel Mode.
C_OVRD_2 0x10: 0x0
0x11: 0x1
0x12: 0x2
0x13: 0x3
0x14: 0x0
0x15: 0x1
0x16: 0x2
0x17: 0x3
0x18: 0x0
0x19: 0x1
0x1A: 0x2
0x1B: 0x3
0x1C: 0x0
0x1D: 0x1
0x1E: 0x2
0x1F: 0x3

MIPI_ERR_PKT_7 (0x8E0)
BIT 7 6 5 4 3 2 1 0
ERR_PKT_
EN_3
Access
Type

ERR_PKT_V
C_OVRD_E 7
N_3
0x0: 0x0
0x1: 0x1
0x2: 0x2
0x3: 0x3
0x4: 0x0
0x5: 0x1
0x6: 0x2
0x7: 0x3
0x8: 0x0
0x9: 0x1
0xA: 0x2
0xB: 0x3
0xC: 0x0
0xD: 0x1
0xE: 0x2
ERR_PKT_V 0xF: 0x3
4:0 Tunnel Mode.
C_OVRD_3 0x10: 0x0
0x11: 0x1
0x12: 0x2
0x13: 0x3
0x14: 0x0
0x15: 0x1
0x16: 0x2
0x17: 0x3
0x18: 0x0
0x19: 0x1
0x1A: 0x2
0x1B: 0x3
0x1C: 0x0
0x1D: 0x1
0x1E: 0x2
0x1F: 0x3
BIT 7 6 5 4 3 2 1 0
Field – – – ERR_PKT_VC_0[4:0]
Reset – – –
Access
Type


Reads back the MIPI Virtual Channel value
ERR_PKT_V for special MIPI Error Packet which is output 0x0
4:0
C_0 when uncorrectable header errors occur in 0x1: Virtual Channel value
Tunnel Mode.
BIT 7 6 5 4 3 2 1 0
Reset – – –
Access
Type

4:0
Tunnel Mode.
BIT 7 6 5 4 3 2 1 0
Reset – – –
Access
Type

4:0
Tunnel Mode.
BIT 7 6 5 4 3 2 1 0
Reset – – –
Access
Type

4:0
Tunnel Mode.

BIT 7 6 5 4 3 2 1 0
ERR_PKT_ ERR_PKT_ ERR_PKT_ ERR_PKT_
Field WC_OVRD WC_OVRD WC_OVRD WC_OVRD – – – –
_EN_3 _EN_2 _EN_1 _EN_0
Reset 0x0 0x0 0x0 0x0 – – – –
Access
Type

0 = Pick random word count from video 0x0: 0 = Pick random word count from video
source in MIPI controller 3 as the word count source in MIPI controller 3 as the word count for
ERR_PKT_
for MIPI Error Packets MIPI Error Packets
WC_OVRD_ 7
1 = Use word count specified in 0x1: 1 = Use word count specified in
EN_3
ERR_PKT_WC_3_H/L register as the word ERR_PKT_WC_3_H/L register as the word count
count for MIPI Error Packets for MIPI Error Packets
ERR_PKT_
WC_OVRD_ 6
EN_2
ERR_PKT_
WC_OVRD_ 5
EN_1
ERR_PKT_
WC_OVRD_ 4
EN_0
BIT 7 6 5 4 3 2 1 0
Field ERR_PKT_WC_0_H[7:0]
Reset 0x00
Access
Write, Read
Type

If ERR_PKT_WC_OVRD_EN_0 is set, this
register sets the word count for special MIPI
Error Packet which is output when
ERR_PKT_ 0x0
7:0 Mode. When not in WC override mode, this
WC_0_H 0x1: Word Count value. See register description
register reads back the word count value for
Tunnel Mode.

BIT 7 6 5 4 3 2 1 0
Field ERR_PKT_WC_0_L[7:0]
Reset 0x00
Access
Write, Read
Type

ERR_PKT_ 0x0
WC_0_L 0x1: Word Count value. See register description
Tunnel Mode.
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

ERR_PKT_ 0x0
Tunnel Mode.
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


ERR_PKT_ 0x0
Tunnel Mode.
MIPI_ERR_PKT_17 (0x8EA)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

ERR_PKT_ 0x0
Tunnel Mode.
MIPI_ERR_PKT_18 (0x8EB)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

ERR_PKT_ 0x0
Tunnel Mode.

MIPI_ERR_PKT_19 (0x8EC)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

ERR_PKT_ 0x0
Tunnel Mode.
MIPI_ERR_PKT_20 (0x8ED)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

ERR_PKT_ 0x0
Tunnel Mode.
MIPI_TX1 (0x901, 0x941)
BIT 7 6 5 4 3 2 1 0
Field MODE[7:0]
Reset 0x00
Access
Write, Read
Type

0bXXXXXXX0: Disable MIPI VS short packet
MIPI Tx mode: b0 = 1: Enables MIPI VS counter
MODE 7:0
short packet counter, cyclic 1~16. 0bXXXXXXX1: Enable MIPI VS short packet
counter

MIPI_TX2 (0x902, 0x942)
BIT 7 6 5 4 3 2 1 0
Field STATUS[7:0]
Reset 0x00
Access
Read Only
Type

MIPI Tx Status Register
The register is split into decode segments:

bit[0] SYNC mode enable.
0bXXXXXXX0: SYNC mode disabled
bit[1] Video sync flag
0bXXXXXXX1: SYNC mode enabled
bit[2] Loss of video sync flag
0bXXXXXX0X: Video channels not in-sync
bit[3] Tunneling mode: DPHY ECC or CPHY
STATUS 7:0 0bXXXXXX1X: Video channels in-sync
header CRC error (correctable)
0xXXXXX0XX: No loss of video sync
bit[4] Tunneling mode: DPHY ECC or CPHY
0xXXXXX1XX: Video sync lost after last read of
header CRC error (uncorrectable)
this register or reset.
bit[5] Tunneling mode: DPHY/CPHY data
CRC error
bit[6] Tunneling mode: DPHY to CPHY
conversion data protection CRC error
MIPI_TX3 (0x903, 0x943)
BIT 7 6 5 4 3 2 1 0
Field DESKEW_INIT[7:0]
Reset 0x87
Access
Write, Read
Type

0bXXXXX000: Initial deskew width = 1 x 32k UI
DPHY Deskew Initial Calibration Control
The register is split into six decode segments:
0bXXXX0XXX: Reserved
Bit [7]: Selects auto-initial deskew calibration
on or off
DESKEW_IN 0bXXX0XXXX: Manual initial off
7:0 Bit [6]: Reserved
IT 0bXXX1XXXX: Manual initial on
Bit [5]: Any bit change initiates an initial
0bXX0XXXXX: If bit 4 = 1, triggers one time
calibration if bit 4 = 1
immediate initial skew calibration
Bit [4]: Selects manual initial on or off
Bit [3]: Reserved
Bits [2:0]: Selects initial deskew width
0bX0XXXXXX: Reserved
0b0XXXXXXX: Auto initial deskew off
0b1XXXXXXX: Auto initial deskew on (should be
used only in DPHY mode and PLL greater than or
equal to 1.5G)

MIPI_TX4 (0x904, 0x944)
BIT 7 6 5 4 3 2 1 0
Field DESKEW_PER[7:0]
Reset 0x81
Access
Write, Read
Type

0bXXXXX000: Periodic deskew width = 1k UI
0bXX000XXX: Periodic deskew calibration
generated every frame
DPHY Periodic Deskew Calibration Control
generated every 2 frames
The register is split into four decode
segments:
bit [7]: Selects periodic deskew calibration on
DESKEW_P 0bXX011XXX: Periodic deskew calibration
7:0 or off
ER generated every 8 frames
bit [6]: Selects generation on rising or falling
edge of VS
bits [5:3]: Selects periodic interval
bits [2:0]: Selects periodic deskew width
0bX0XXXXXX: Periodic deskew calibration
generated at rising edge of VS
generated at falling edge of VS
0b0XXXXXXX: Periodic deskew calibration off
0b1XXXXXXX: Periodic deskew calibration on
MIPI_TX5 (0x905, 0x945)
BIT 7 6 5 4 3 2 1 0
Field CSI2_T_PRE[7:0]
Reset 0x71
Access
Write, Read
Type

Number of clock cycles to wait before
CSI2_T_PRE 7:0 0xXX: Number of MIPI byte clocks
enabling HS data

MIPI_TX6 (0x906, 0x946)
BIT 7 6 5 4 3 2 1 0
Field CSI2_T_POST[7:0]
Reset 0x19
Access
Write, Read
Type

CSI2_T_POS Number of byte clocks to hold clock active
7:0 0xXX: Number of MIPI byte clocks
T after data
MIPI_TX7 (0x907, 0x947)
BIT 7 6 5 4 3 2 1 0
Field CSI2_TX_GAP[7:0]
Reset 0x1C
Access
Write, Read
Type

Sets the number of clocks to wait after the HS
CSI2_TX_GA
7:0 CLK has entered LP before enabling it again 0xXX: Number of MIPI byte clocks
P
for the next transmission
MIPI_TX8 (0x908, 0x948)
BIT 7 6 5 4 3 2 1 0
Field CSI2_TWAKEUP_L[7:0]
Reset 0x00
Access
Write, Read
Type

Sets DPHY timing parameter tWAKEUP. Set
CSI2_TWAK
7:0 the number of clock cycles to keep clock and 0xXX: Number of MIPI byte clocks
EUP_L
data in Mark-1 state after exiting ULPS.
MIPI_TX9 (0x909, 0x949)
BIT 7 6 5 4 3 2 1 0
Field CSI2_TWAKEUP_M[7:0]
Reset 0x01
Access
Write, Read
Type

Sets DPHY timing parameter tWAKEUP. Set
CSI2_TWAK
EUP_M

MIPI_TX10 (0x90A, 0x94A)
BIT 7 6 5 4 3 2 1 0
CSI2_CPH
Field CSI2_LANE_CNT[1:0] csi2_vcx_en – CSI2_TWAKEUP_H[2:0]
Y_EN
Reset 0x3 0b0 0x1 – 0x0
Access
Write, Read Write, Read Write, Read – Write, Read
Type

0b00: One data lane
MIPI Lane Count
0b01: Two data lanes
CSI2_LANE_ 0b10: Three data lanes (Reserved for registers
7:6 In 4x2 mode, CSI2_LANE_CNT register bit
CNT 0x90A and 0x9CA)
[1] will always read back 1'b0 since hardware
0b11: Four data lanes (Reserved for registers
will mask this to 1'b0 in this mode.
0x90A and 0x9CA)
CSI2_CPHY 0b0: DPHY mode
5 CPHY Enable
_EN 0b1: CPHY mode
0b0: Select 2-bit VC
csi2_vcx_en 4 Enables virtual channel extension
0b1: Select 5-bit VC (CPHY) or 4-bit VC (DPHY)
High bits of DPHY timing parameter
CSI2_TWAK tWAKEUP. Sets the number of clock cycles to
2:0 0bXXX: Number of MIPI byte clocks
EUP_H keep clock and data in Mark-1 state after
exiting ULPS.
MIPI_TX11 (0x90B, 0x94B)
BIT 7 6 5 4 3 2 1 0
Field MAP_EN_L[7:0]
Reset 0x00
Access
Write, Read
Type

0b00000000: No mapping enabled
Mapping enable low byte [7:0].
0bXXXXXXX1: Map SRC_0 to DES_0
0bXXXXXX1X: Map SRC_1 to DES_1
Each bit enables 1 of 8 mapping and
0bXXXXX1XX: Map SRC_2 to DES_2
distribution entries (defined in MAP_SRC_x,
MAP_EN_L 7:0 0bXXXX1XXX: Map SRC_3 to DES_3
MAP_DST_x, and MAP_DPHY_DST_x) for
0bXXX1XXXX: Map SRC_4 to DES_4
the current video stream. Non-matched virtual
0bXX1XXXXX: Map SRC_5 to DES_5
channel (VC) and data types (DT) pass to the
0bX1XXXXXX: Map SRC_6 to DES_6
corresponding CSI2 controller.
0b1XXXXXXX: Map SRC_7 to DES_7
MIPI_TX12 (0x90C, 0x94C)
BIT 7 6 5 4 3 2 1 0
Field MAP_EN_H[7:0]
Reset 0x00
Access
Write, Read
Type


Mapping enable high byte [15:8].
MAP_EN_H 7:0 0bXXXX1XXX: Map SRC_11 to DES_11
MIPI_TX13 (0x90D, 0x94D)
BIT 7 6 5 4 3 2 1 0
Field MAP_SRC_0[7:0]
Reset 0x00
Access
Write, Read
Type

Video Pipe Source Mapping Register 0 -
Virtual Channel / Data Type
The register is split into two decode

segments:
bits [7:6]: VC - Virtual channel
bits [5:0]: DT - Data type
In addition, the VC field can be extended

using VC extended mode. See register [7:6]: VC – 0bXX
MAP_SRC_0 7:0
MAP_SRC_0_H associated with this Video [5:0]: DT– 0bXXXXXX
Pipe.
The Data Type field decode matches that in

the MIPI specification.

source-to-destination mappings. See register
MAP_DST_0 to program the destination
setting.
MIPI_TX14 (0x90E, 0x94E)
BIT 7 6 5 4 3 2 1 0
Field MAP_DST_0[7:0]
Reset 0x00
Access
Write, Read
Type


Video Pipe Destination Mapping Register 0 -

segments:

[7:6]: VC – 0bXX
MAP_DST_0 7:0 using VC extended mode. See register
[5:0]: DT– 0bXXXXXX
MAP_DST_0_H associated with this Video
Pipe.


MAP_SRC_0 to program the source setting.
MIPI_TX15 (0x90F, 0x94F)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type

Virtual Channel/Data Type

segments:
Bits [7:6]: VC - Virtual channel
Bits [5:0]: DT - Data type

using VC extended mode. See register
[7:6]: VC – 0bXX
MAP_SRC_1 7:0 MAP_SRC_1_H associated with this Video
Pipe.


is the source setting of the first mapping pair.
See register MAP_DST_1 to program the
destination setting.

MIPI_TX16 (0x910, 0x950)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
MAP_DST_1 7:0 MAP_DST_1_H associated with this Video
Pipe.


is the destination setting of the first mapping
pair. See register MAP_SRC_1 to program
the source setting.
MIPI_TX17 (0x911, 0x951)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the second mapping
pair. See register MAP_DST_2 to program
the destination setting.
MIPI_TX18 (0x912, 0x952)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the second
mapping pair. See register MAP_SRC_2 to
program the source setting.

MIPI_TX19 (0x913, 0x953)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the third mapping pair.
MIPI_TX20 (0x914, 0x954)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the third mapping
the source setting.
MIPI_TX21 (0x915, 0x955)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the fourth mapping

MIPI_TX22 (0x916, 0x956)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the fourth
MIPI_TX23 (0x917, 0x957)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the fifth mapping pair.
MIPI_TX24 (0x918, 0x958)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the fifth mapping
the source setting.

MIPI_TX25 (0x919, 0x959)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


source-to-destination mappings. his register
is the source setting of the sixth mapping
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the sixth mapping
the source setting.
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the seventh mapping

BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the seventh
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the eighth mapping
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the eighth

BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the ninth mapping
MIPI_TX32 (0x920, 0x960)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the ninth mapping
the source setting.
MIPI_TX33 (0x921, 0x961)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

MAP_SRC_1 [7:6]: VC – 0bXX
7:0 MAP_SRC_10_H associated with this Video
0 [5:0]: DT– 0bXXXXXX
Pipe.


is the source setting of the tenth mapping

MIPI_TX34 (0x922, 0x962)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

MAP_DST_1 [7:6]: VC – 0bXX
7:0 MAP_DST_10_H associated with this Video
Pipe.


is the destination setting of the tenth mapping
the source setting.
MIPI_TX35 (0x923, 0x963)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the source setting of the eleventh mapping
MIPI_TX36 (0x924, 0x964)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the eleventh

MIPI_TX37 (0x925, 0x965)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the twelfth mapping
MIPI_TX38 (0x926, 0x966)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the destination setting of the twelfth
MIPI_TX39 (0x927, 0x967)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the thirteenth mapping

MIPI_TX40 (0x928, 0x968)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the thirteenth
MIPI_TX41 (0x929, 0x969)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the source setting of the fourteenth
mapping pair. See register MAP_DST_14 to
program the destination setting.
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the fourteenth

BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the fifteenth mapping
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the destination setting of the fifteenth
BIT 7 6 5 4 3 2 1 0
Field MAP_DPHY_DEST_3[1:0] MAP_DPHY_DEST_2[1:0] MAP_DPHY_DEST_1[1:0] MAP_DPHY_DEST_0[1:0]
Access
Type

DPHY and CPHY Mapping destination
0b00: CSI2 controller 0
controller register.
MAP_DPHY_ 0b01: CSI2 controller 1
7:6
DEST_3 0b10: CSI2 controller 2
CSI2 PHY destination for MAP_SRC_3 and
MAP_DST_3 mapping registers.
5:4
3:2
MAP_DST_1 mapping registers
0b00: Map to controller 0
MAP_DPHY_ 0b01: Map to controller 1
1:0
DEST_0 0b10: Map to controller 2

BIT 7 6 5 4 3 2 1 0
Access
Type

7:6
5:4
3:2
1:0
BIT 7 6 5 4 3 2 1 0
MAP_DPHY_DEST_11[1: MAP_DPHY_DEST_10[1:
Field MAP_DPHY_DEST_9[1:0] MAP_DPHY_DEST_8[1:0]
0] 0]
Access
Type

7:6
5:4
3:2


1:0
MIPI_TX48 (0x930, 0x970)
BIT 7 6 5 4 3 2 1 0
MAP_DPHY_DEST_15[1: MAP_DPHY_DEST_14[1: MAP_DPHY_DEST_13[1: MAP_DPHY_DEST_12[1:
Field
0] 0] 0] 0]
Access
Type

7:6
5:4
3:2
1:0
MIPI_TX49 (0x931, 0x971)
BIT 7 6 5 4 3 2 1 0
Field MAP_CON[7:0]
Reset 0x00
Access
Write, Read
Type


MIPI controller SYNC concatenation register.

segments:
bit [7]: 1'b1 = 4WxH, 1'b0 = Wx4H
bit [6]: Reserved 0bXXXXXXX1: Concatenate Video Pipeline 0
bits [5:4]: Select the first line to concatenate. 0bXXXXXX1X: Concatenate Video Pipeline 1
All others follow in order bits [3:0]. 0bXXXXX1XX: Concatenate Video Pipeline 2
2'b00 = Select Pipe 0 to be the master 0bXXXX1XXX: Concatenate Video Pipeline 3
2'b01 = Select Pipe 1 to be the master 0bXX00XXXX: Select Video Pipeline 0 as master
MAP_CON 7:0
bit [3]: 1'b0 = disable, 1'b1 = concatenate 0bXX11XXXX: Select Video Pipeline 3 as master
Video Pipe 3 0b0XXXXXXX: Enable Wx4H mode
bit [2]: 1'b0 = disable, 1'b1 = concatenate 0b1XXXXXXX: Enable 4WxH mode
Video Pipe 2
bit [1]: 1'b0 = disable, 1'b1 = concatenate
Video Pipe 1
bit [0]: 1'b0 = disable, 1'b1 = concatenate
Video Pipe 0
MIPI_TX50 (0x932, 0x972)
BIT 7 6 5 4 3 2 1 0
Field SKEW_PER_SEL[7:0]
Reset 0x00
Access
Write, Read
Type


0b0xxxxxxx: Generate periodic calibration deskew
calibration on all virtual channels
0b1xx00000: Periodic deskew calibration
generated by virtual Channel 0
Periodic deskew select register. The register generated by virtual Channel 5
is split into three decode segments: 0b1xx00110: Periodic deskew calibration
bit [7]: Select periodic deskew calibration for generated by virtual Channel 6
SKEW_PER one or all virtual channels 0b1xx00111: Periodic deskew calibration
7:0
_SEL bits [6:5]: Reserved generated by virtual Channel 7
bits [4:0]: Virtual channel to generate periodic 0b1xx01000: Periodic deskew calibration
deskew calibration when only one channel is generated by virtual Channel 8
selected by bit 7 0b1xx01001: Periodic deskew calibration
MIPI_TX51 (0x933, 0x973)
BIT 7 6 5 4 3 2 1 0
ALT2_MEM ALT_MEM_ ALT_MEM_ ALT_MEM_
Field – – – MODE_DT
_MAP8 MAP10 MAP8 MAP12
Reset – – – 0b0 0b0 0b0 0b0 0b0
Access
– – – Write, Read Write, Read Write, Read Write, Read Write, Read
Type

0b0: Alternative memory read mapping not
Alternative memory read mapping enable for
ALT2_MEM_ enabled for 8-bit DT
4 8-bit DT when sharing the same video pipe
MAP8 0b1: Alternative memory read mapping enabled for
with RAW16
8-bit DT
0b0: 24-bit mode for user-defined data types not
Select 24-bit mode for user-defined data enabled
MODE_DT 3
types 0b1: 24-bit mode for user-defined data types
enabled


ALT_MEM_ Alternative memory read mapping enable for enabled for 10-bit DT
2
MAP10 10-bit DT 0b1: Alternative memory read mapping enabled for
10-bit DT
1
8-bit DT
0
12-bit DT
MIPI_TX52 (0x934, 0x974)
BIT 7 6 5 4 3 2 1 0
Field video_masked_latched[3:0] video_masked[3:0]
Reset 0x0 0x0
Access
Read Only Read Only
Type

0bXXX1: Video pipe 0 previously masked off
Indicates video pipes 0-3 were masked off at
video_maske 0bXX1X: Video pipe 1 previously masked off
7:4 one point while in 4WxH or Wx4H
d_latched 0bX1XX: Video pipe 2 previously masked off
0b1XXX: Video pipe 3 previously masked off
Video pipe currently masked off while in
3:0 4WxH or Wx4H synchronous aggregation
d 0bX1XX: Video pipe 2 previously masked off
mode.
MIPI_TX54 (0x936, 0x976)
BIT 7 6 5 4 3 2 1 0
TUN_NO_C TUN_SER_LANE_NUM[1:
Field DESKEW_TUN[1:0] DESKEW_TUN_SRC[1:0] TUN_EN
ORR 0]
Access
Type

0x0: Automatic correction for correctable header
TUN_NO_C Do not enable header error correction in error
7
ORR tunneling mode 0x1: Turn off correction for correctable header
error
0: Periodic deskew as in HS94 (determined by
deskew_per_* registers).
DESKEW_T 1: Periodic deskew follows SER.
6:5 Deskew Mode for CSI2 Tunneling
UN 2: Periodic deskew START follows SER but width
as register defined.
3: Not used


Tunneling Serializer Lane Number
TUN_SER_L 0x0: 1-lane
4:3
ANE_NUM Used ONLY in tunneling mode when source 0x1: 2-lanes
is in CPHY mode
Tunneling Deskew Source Select
0x0: Pipe 0
DESKEW_T DESKEW_TUN_SRC register must select 0x1: Pipe 1
2:1
UN_SRC one of the mapped pipes for this controller. 0x2: Pipe 2
0x3: Pipe 3
Tunneling Enabled
0b0: Tunneling disabled
TUN_EN 0
This register takes effect only if 0b1: Tunneling enabled
DIS_AUTO_TUN_DET is 1.
MIPI_TX56 (0x938, 0x978)
BIT 7 6 5 4 3 2 1 0
Field PKT_START_ADDR[7:0]
Reset 0x0
Access
Write, Read
Type

Specifies the start address of the long packet.
0: The long packet is sent out when the whole line is filled in line memory.
Not 0: The long packet begins when PKT_START_ADDR x 128 bytes are
filled in the line memory in tunnel mode or when PKT_START_ADDR x 64
pixels are filled in the line memory in pixel mode.
Make sure register n_vs_block is 2 or more

(default = 1).
PKT_START_ADDR 7:0
Notes:
• "Cut-through" only works with 1-3 virtual channels. May increase to 4 VCs in
future revisions.
• Bytes are packed differently into memory when in tunnel mode. For
example, in tunnel mode, a BPP of 24 is equal to 1.33 pixels per address. In
pixel mode, a BPP of 24 is equal to 1 pixel per address.
• When in tunnel mode, the units for PKT_START_ADDR are in bytes. In pixel
mode, the units are in pixels.

MIPI_TX57 (0x939, 0x979)
BIT 7 6 5 4 3 2 1 0
TUN_DPHY
DIS_AUTO TUN_DPHY
DIS_AUTO _TO_CPHY
Field _SER_LAN TUN_DEST[1:0] – _TO_CPHY RSVD
_TUN_DET _CONV_OV
E_DET _CONV
RD
Reset 0x0 0x0 0x1 – 0x0 0x0 0x0
Access
Write, Read Write, Read Write, Read – Write, Read Write, Read
Type

Disable auto SER lane count detect.
DIS_AUTO_ When this register is set to 1 (automatic

SER_LANE_ 7 detection of SER lane count is disabled),
0b1: Tunneling enabled
DET TUN_SER_LANE_NUM register will need to
be set to the SER lane count.
Disable auto tunneling mode detect.
When this register is set to 1 (automatic

DIS_AUTO_ detection of tunneling mode disabled), 0b0: Tunneling disabled
6
TUN_DET TUN_EN registers will set pixel mode 0b1: Tunneling enabled
(TUN_EN = 0) or tunneling mode (TUN_EN
=1).
0x0: Controller 0
TUN_DEST 5:4 Tunneling controller Destination
0x1: Controller 1
Only used when
TUN_DPHY_TO_CPHY_CONV_OVRD bit is
set.
Manual override bit to enable DPHY to CPHY
conversion in tunneling mode (must also
TUN_DPHY_
disable auto tunneling mode detect 0x0: Controller 0
TO_CPHY_C 2
DIS_AUTO_TUN_DET = 1 and manually set 0x1: Controller 1
ONV
tunneling mode TUN_EN = 1). When set to 0,
SER headers are evaluated to detect DPHY/
CPHY mode, if SER is sending DPHY and
the DES MIPI PHY is sent to CPHY mode,
conversion is turn on.
TUN_DPHY_ Enable value in
0x0: Controller 0
TO_CPHY_C 1 TUN_DPHY_TO_CPHY_CONV register to
0x1: Controller 1
ONV_OVRD override automatic detection.
MIPI_ERR_INJ_B1 (0x93A, 0x97A)
BIT 7 6 5 4 3 2 1 0
DCPHY_C
Field ONV_ERR_ – – DCPHY_CONV_ERR_INJ_B1_SITE[4:0]
INJ_B1_EN
Reset 0b0 – – 0x00
Access Write Clears
– – Write, Read
Type All, Read


Enable Error Injection for the first bit error
injection location selection.
DCPHY_CO
See the DCPHY_CONV_ERR_INJ_B1_SITE
NV_ERR_IN 7
register field description.
J_B1_EN
Write 1 to trigger the error injection. This bit
will self clear.
First Bit Error Injection location in the DPHY
header. 0-7: DATA ID (DT)
DCPHY_CO
Used to inject errors into the MIPI DPHY 8-23: DATA FIELD
NV_ERR_IN 4:0
standard output header which is then 24-30: ECC
J_B1_SITE
converted to MIPI CPHY standard output 31-32: VCX
during tunnel mode.
MIPI_ERR_INJ_B2 (0x93B, 0x97B)
BIT 7 6 5 4 3 2 1 0
DCPHY_C
INJ_B2_EN
Reset 0b0 – – 0x00
Access Write Clears
– – Write, Read
Type All, Read

Enable Error Injection for the second bit error
DCPHY_CO
NV_ERR_IN 7
J_B2_EN
will self clear.
Second Bit Error Injection location in the
DPHY header. 0-7: DATA ID (DT)
DCPHY_CO
NV_ERR_IN 4:0
J_B2_SITE
during tunnel mode.
MIPI_ERRB_DESKEW_ORDER (0x93C, 0x97C)
BIT 7 6 5 4 3 2 1 0
DESKEW_ DESKEW_ DESKEW_
BEFORE_E AFTER_ER BEFORE_V
Field – – – – –
RRB_PKT_ RB_PKT_M S_PKT_MO
MODE ODE DE
Reset – – – – 0x0 0x0 0x0 –
Access
– – – – Write, Read Write, Read Write, Read –
Type


This bit can control when the DESKEW
occurs relative to ERRB_PKT.
This register,
DESKEW_BEFORE_ERRB_PKT_MODE,
has priority over
DESKEW_AFTER_ERRB_PKT_MODE
DESKEW_B 0x0: DESKEW may occur before or after
Note: When trying to control the order of
EFORE_ER ERRB_PKT depending on other registers (see
3 DESKEW, VS, and ERRB_PKT, please
RB_PKT_MO complete table)
consider these registers:
DE 0x1: DESKEW occurs before ERRB_PKT
ERRB_PKT_Insert_Mode[1:0]
ERRB_PKT_EDGE_SEL
DESKEW_PER[6]
DESKEW_BEFORE_VS_PKT_MODE
DESKEW_BEFORE_ERRB_PKT_MODE


DESKEW, VS, and ERRB_PKT, please
consider these registers: 0x0: DESKEW may occur before or after
DESKEW_A
ERRB_PKT depending on other registers (see
FTER_ERRB 2
ERRB_PKT_Insert_Mode[1:0] complete table)
_PKT_MODE
ERRB_PKT_EDGE_SEL 0x1: DESKEW occurs after ERRB_PKT
DESKEW_PER[6]

occurs relative to a VS ( frame-start or frame-
end) pkt.

DESKEW_B consider these registers:
0x0: DESKEW occurs after the VS pkt
EFORE_VS_ 1
0x1: DESKEW occurs before the VS pkt
PKT_MODE ERRB_PKT_Insert_Mode[1:0]
ERRB_PKT_EDGE_SEL
DESKEW_PER[6]
MIPI_TX1 (0x981, 0x9C1)
BIT 7 6 5 4 3 2 1 0
Field MODE[7:0]
Reset 0x00
Access
Write, Read
Type


0bXXXXXXX0: Disable MIPI VS short packet
MIPI Tx mode: b0 = 1: Enables MIPI VS counter
MODE 7:0
short packet counter, cyclic 1~16. 0bXXXXXXX1: Enable MIPI VS short packet
counter
MIPI_TX2 (0x982, 0x9C2)
BIT 7 6 5 4 3 2 1 0
Field STATUS[7:0]
Reset 0x00
Access
Read Only
Type

MIPI Tx Status Register
The register is split into decode segments:

Bit[0] SYNC mode enable.
0bXXXXXXX0: SYNC mode disabled
Bit[1] Video sync flag
0bXXXXXXX1: SYNC mode enabled
Bit[2] Loss of video sync flag
0bXXXXXX0X: Video channels not in-sync
Bit[3] Tunneling mode: DPHY ECC or CPHY
STATUS 7:0 0bXXXXXX1X: Video channels in-sync
header CRC error (correctable)
0xXXXXX0XX: No loss of video sync
Bit[4] Tunneling mode: DPHY ECC or CPHY
0xXXXXX1XX: Video sync lost after last read of
header CRC error (uncorrectable)
this register or reset.
Bit[5] Tunneling mode: DPHY/CPHY data
CRC error
Bit[6] Tunneling mode: DPHY to CPHY
conversion data protection CRC error
MIPI_TX3 (0x983, 0x9C3)
BIT 7 6 5 4 3 2 1 0
Field DESKEW_INIT[7:0]
Reset 0x87
Access
Write, Read
Type


DPHY Deskew Initial Calibration Control
The register is split into six decode segments:
Bit [7]: Selects auto-initial deskew calibration
on or off
DESKEW_IN 0bXXX0XXXX: Manual initial off
7:0 Bit [6]: Reserved
IT 0bXXX1XXXX: Manual initial on
Bit [5]: Any bit change initiates an initial
calibration if bit 4 = 1
Bit [4]: Selects manual initial on or off
Bit [3]: Reserved
Bits [2:0]: Selects initial deskew width
0b0XXXXXXX: Auto initial deskew off
0b1XXXXXXX: Auto initial deskew on (should be
used only in DPHY mode and PLL greater than or
equal to 1.5G)
MIPI_TX4 (0x984, 0x9C4)
BIT 7 6 5 4 3 2 1 0
Field DESKEW_PER[7:0]
Reset 0x81
Access
Write, Read
Type


generated every frame
DPHY Periodic Deskew Calibration Control
segments:
Bit [7]: Selects periodic deskew calibration on
DESKEW_P 0bXX011XXX: Periodic deskew calibration
7:0 or off
ER generated every 8 frames
Bit [6]: Selects generation on rising or falling
edge of VS
Bits [5:3]: Selects periodic interval
Bits [2:0]: Selects periodic deskew width
generated at rising edge of VS
generated at falling edge of VS
0b0XXXXXXX: Periodic deskew calibration off
0b1XXXXXXX: Periodic deskew calibration on
MIPI_TX5 (0x985, 0x9C5)
BIT 7 6 5 4 3 2 1 0
Field CSI2_T_PRE[7:0]
Reset 0x71
Access
Write, Read
Type

Number of clock cycles to wait before
CSI2_T_PRE 7:0 0xXX: Number of MIPI byte clocks
enabling HS data
MIPI_TX6 (0x986, 0x9C6)
BIT 7 6 5 4 3 2 1 0
Field CSI2_T_POST[7:0]
Reset 0x19
Access
Write, Read
Type

CSI2_T_POS Number of byte clocks to hold clock active
7:0 0xXX: Number of MIPI byte clocks
T after data

MIPI_TX7 (0x987, 0x9C7)
BIT 7 6 5 4 3 2 1 0
Field CSI2_TX_GAP[7:0]
Reset 0x1C
Access
Write, Read
Type

Sets the number of clocks to wait after the HS
CSI2_TX_GA
7:0 CLK has entered LP before enabling it again 0xXX: Number of MIPI byte clocks
P
for the next transmission
MIPI_TX8 (0x988, 0x9C8)
BIT 7 6 5 4 3 2 1 0
Field CSI2_TWAKEUP_L[7:0]
Reset 0x00
Access
Write, Read
Type

Sets DPHY timing parameter Twakeup. Set
CSI2_TWAK
EUP_L
MIPI_TX9 (0x989, 0x9C9)
BIT 7 6 5 4 3 2 1 0
Field CSI2_TWAKEUP_M[7:0]
Reset 0x01
Access
Write, Read
Type

Sets DPHY timing parameter Twakeup. Set
CSI2_TWAK
EUP_M
MIPI_TX10 (0x98A, 0x9CA)
BIT 7 6 5 4 3 2 1 0
CSI2_CPH
Field CSI2_LANE_CNT[1:0] csi2_vcx_en – CSI2_TWAKEUP_H[2:0]
Y_EN
Reset 0x3 0b0 0x1 – 0x0
Access
Write, Read Write, Read Write, Read – Write, Read
Type


0b00: One data lane
0b01: Two data lanes
CSI2_LANE_ 0b10: Three data lanes (Reserved for registers
7:6 MIPI Lane Count
CNT 0x90A and 0x9CA)
0b11: Four data lanes (Reserved for registers
0x90A and 0x9CA)
CSI2_CPHY 0b0: DPHY mode
5 CPHY Enable
_EN 0b1: CPHY mode
0b0: Select 2-bit VC
csi2_vcx_en 4 Enables virtual channel extension
0b1: Select 5-bit VC (CPHY) or 4-bit VC (DPHY)
High bits of DPHY timing parameter Twakeup.
CSI2_TWAK
2:0 Sets the number of clock cycles to keep clock 0bXXX: Number of MIPI byte clocks
EUP_H
and data in Mark-1 state after exiting ULPS.
MIPI_TX11 (0x98B, 0x9CB)
BIT 7 6 5 4 3 2 1 0
Field MAP_EN_L[7:0]
Reset 0x00
Access
Write, Read
Type

Mapping enable low byte [7:0].
MAP_EN_L 7:0 0bXXXX1XXX: Map SRC_3 to DES_3
MIPI_TX12 (0x98C, 0x9CC)
BIT 7 6 5 4 3 2 1 0
Field MAP_EN_H[7:0]
Reset 0x00
Access
Write, Read
Type

Mapping enable high byte [15:8].
MAP_EN_H 7:0 0bXXXX1XXX: Map SRC_11 to DES_11

MIPI_TX13 (0x98D, 0x9CD)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

MAP_SRC_0 7:0
Pipe.


MAP_DST_0 to program the destination
setting.
MIPI_TX14 (0x98E, 0x9CE)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
MAP_DST_0 7:0 using VC extended mode. See register
MAP_DST_0_H associated with this Video
Pipe.


MAP_SRC_0 to program the source setting.
MIPI_TX15 (0x98F, 0x9CF)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the first mapping pair.

MIPI_TX16 (0x990, 0x9D0)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the first mapping
the source setting
MIPI_TX17 (0x991, 0x9D1)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the second mapping
MIPI_TX18 (0x992, 0x9D2)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the second
program the source setting

MIPI_TX19 (0x993, 0x9D3)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the third mapping pair.
MIPI_TX20 (0x994, 0x9D4)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the third mapping
the source setting
MIPI_TX21 (0x995, 0x9D5)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the fourth mapping

MIPI_TX22 (0x996, 0x9D6)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the fourth
MIPI_TX23 (0x997, 0x9D7)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the fifth mapping pair.
MIPI_TX24 (0x998, 0x9D8)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the fifth mapping
the source setting

MIPI_TX25 (0x999, 0x9D9)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the sixth mapping
MIPI_TX26 (0x99A, 0x9DA)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the sixth mapping
the source setting
MIPI_TX27 (0x99B, 0x9DB)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

MAP_SRC_7 7:0
Pipe.

is the source setting of the seventh mapping

MIPI_TX28 (0x99C, 0x9DC)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the seventh
MIPI_TX29 (0x99D, 0x9DD)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the eighth mapping
MIPI_TX30 (0x99E, 0x9DE)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the eighth

MIPI_TX31 (0x99F, 0x9DF)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

[7:6]: VC – 0bXX
Pipe.


is the source setting of the ninth mapping
MIPI_TX32 (0x9A0, 0x9E0)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

[7:6]: VC – 0bXX
Pipe.


is the destination setting of the ninth mapping
the source setting
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the tenth mapping

BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the tenth mapping
the source setting
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the source setting of the eleventh mapping
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the eleventh

BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the twelfth mapping
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the destination setting of the twelfth
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the thirteenth mapping

BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the thirteenth
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the source setting of the fourteenth
mapping pair. See register MAP_DST_14 to
program the destination setting.
MIPI_TX42 (0x9AA, 0x9EA)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the destination setting of the fourteenth

MIPI_TX43 (0x9AB, 0x9EB)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type


segments:

Pipe.


is the source setting of the fifteenth mapping
MIPI_TX44 (0x9AC, 0x9EC)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Write, Read
Type



segments:

Pipe.


is the destination setting of the fifteenth
MIPI_TX45 (0x9AD, 0x9ED)
BIT 7 6 5 4 3 2 1 0
Access
Type

7:6
5:4
3:2
MAP_DPHY_ 0b01: Map to controller 1
1:0
DEST_0 0b10: Map to controller 2

MIPI_TX46 (0x9AE, 0x9EE)
BIT 7 6 5 4 3 2 1 0
Access
Type

7:6
5:4
3:2
1:0
MIPI_TX47 (0x9AF, 0x9EF)
BIT 7 6 5 4 3 2 1 0
MAP_DPHY_DEST_11[1: MAP_DPHY_DEST_10[1:
Field MAP_DPHY_DEST_9[1:0] MAP_DPHY_DEST_8[1:0]
0] 0]
Access
Type

7:6
5:4
3:2


1:0
MIPI_TX48 (0x9B0, 0x9F0)
BIT 7 6 5 4 3 2 1 0
MAP_DPHY_DEST_15[1: MAP_DPHY_DEST_14[1: MAP_DPHY_DEST_13[1: MAP_DPHY_DEST_12[1:
Field
0] 0] 0] 0]
Access
Type

7:6
5:4
3:2
1:0
BIT 7 6 5 4 3 2 1 0
Field MAP_CON[7:0]
Reset 0x00
Access
Write, Read
Type


MIPI controller SYNC concatenation register.

segments:
Bit [7]: 1'b1 = 4WxH, 1'b0 = Wx4H
Bit [6]: Reserved 0bXXXXXXX1: Concatenate Video Pipeline 0
Bits [5:4]: Select the first line to concatenate. 0bXXXXXX1X: Concatenate Video Pipeline 1
All others follow in order bits [3:0]. 0bXXXXX1XX: Concatenate Video Pipeline 2
2'b00 = Select Pipe 0 to be the master 0bXXXX1XXX: Concatenate Video Pipeline 3
MAP_CON 7:0
Bit [3]: 1'b0 = disable, 1'b1 = concatenate 0bXX11XXXX: Select Video Pipeline 3 as master
Video Pipe 3 0b0XXXXXXX: Enable Wx4H mode
Bit [2]: 1'b0 = disable, 1'b1 = concatenate 0b1XXXXXXX: Enable 4WxH mode
Video Pipe 2
Bit [1]: 1'b0 = disable, 1'b1 = concatenate
Video Pipe 1
Bit [0]: 1'b0 = disable, 1'b1 = concatenate
Video Pipe 0
BIT 7 6 5 4 3 2 1 0
Field SKEW_PER_SEL[7:0]
Reset 0x00
Access
Write, Read
Type


0b0xxxxxxx: Generate periodic calibration deskew
calibration on all virtual channels
Periodic deskew select register. The register generated by virtual Channel 5
is split into three decode segments: 0b1xx00110: Periodic deskew calibration
Bit [7]: Select periodic deskew calibration for generated by virtual Channel 6
SKEW_PER one or all virtual channels 0b1xx00111: Periodic deskew calibration
7:0
_SEL Bits [6:5]: Reserved generated by virtual Channel 7
Bits [4:0]: Virtual channel to generate periodic 0b1xx01000: Periodic deskew calibration
deskew calibration when only one channel is generated by virtual Channel 8
selected by bit 7 0b1xx01001: Periodic deskew calibration
BIT 7 6 5 4 3 2 1 0
ALT2_MEM ALT_MEM_ ALT_MEM_ ALT_MEM_
Field – – – MODE_DT
_MAP8 MAP10 MAP8 MAP12
Reset – – – 0b0 0b0 0b0 0b0 0b0
Access
– – – Write, Read Write, Read Write, Read Write, Read Write, Read
Type

Alternative memory read mapping enable for
ALT2_MEM_ enabled for 8-bit DT
4 8-bit DT when sharing the same video pipe
MAP8 0b1: Alternative memory read mapping enabled for
with RAW16
8-bit DT
0b0: 24-bit mode for user-defined data types not
Select 24-bit mode for user-defined data enabled
MODE_DT 3
types 0b1: 24-bit mode for user-defined data types
enabled


2
10-bit DT
1
8-bit DT
0
12-bit DT
BIT 7 6 5 4 3 2 1 0
Field video_masked_latched[3:0] video_masked[3:0]
Reset 0x0 0x0
Access
Read Only Read Only
Type

Indicates video pipes 0-3 were masked off at
7:4 one point while in 4WxH or Wx4H
d_latched 0bX1XX: Video pipe 2 previously masked off
Video pipe currently masked off while in
3:0 4WxH or Wx4H synchronous aggregation
d 0bX1XX: Video pipe 2 previously masked off
mode.
BIT 7 6 5 4 3 2 1 0
TUN_NO_C TUN_SER_LANE_NUM[1:
Field DESKEW_TUN[1:0] DESKEW_TUN_SRC[1:0] TUN_EN
ORR 0]
Access
Type

0x0: Automatic correction for correctable header
TUN_NO_C Do not enable header error correction in error
7
ORR tunneling mode 0x1: Turn off correction for correctable header
error
0: periodic deskew as in HS94 (determined by
deskew_per_* registers).
DESKEW_T 1: periodic deskew follows SER.
6:5 Deskew Mode for CSI2 Tunneling
UN 2: periodic deskew START follows SER but width
as register defined.
3: not used


Tunneling Serializer Lane Number
TUN_SER_L 0x0: 1-lane
4:3
ANE_NUM Used ONLY in tunneling mode when source 0x1: 2-lanes
is in CPHY mode
Tunneling Deskew Source Select 0x0: Pipe 0
DESKEW_T 0x1: Pipe 1
2:1
UN_SRC DESKEW_TUN_SRC register must select 0x2: Pipe 2
one of the mapped pipes for this controller. 0x3: Pipe 3
Tunneling Enabled
TUN_EN 0
This register takes effect only if 0b1: Tunneling enabled
DIS_AUTO_TUN_DET is 1.
BIT 7 6 5 4 3 2 1 0
Field PKT_START_ADDR[7:0]
Reset 0x0
Access
Write, Read
Type

Specifies the start address of the long packet.
0: The long packet is sent out when the whole line is filled in line memory.
Not 0: The long packet begins when PKT_START_ADDR x 128 bytes are
filled in the line memory in tunnel mode or when PKT_START_ADDR x 64
pixels are filled in the line memory in pixel mode.
Make sure register n_vs_block is 2 or more

(default = 1).
PKT_START_ADDR 7:0
Notes:
• "Cut-through" only works with 1-3 virtual channels. May increase to 4 VCs in
future revisions.
• Bytes are packed differently into memory when in tunnel mode. For
example, in tunnel mode, a BPP of 24 is equal to 1.33 pixels per address. In
pixel mode, a BPP of 24 is equal to 1 pixel per address.
• When in tunnel mode, the units for PKT_START_ADDR are in bytes. In pixel
mode, the units are in pixels.
BIT 7 6 5 4 3 2 1 0
TUN_DPHY
DIS_AUTO TUN_DPHY TUN_NO_C
DIS_AUTO _TO_CPHY
Field _SER_LAN TUN_DEST[1:0] – _TO_CPHY ORR_LENG
_TUN_DET _CONV_OV
E_DET _CONV TH
RD
Reset 0x0 0x0 0x1 – 0x0 0x0 0x0
Access
Write, Read Write, Read Write, Read – Write, Read Write, Read Write, Read
Type


Disable auto SER lane count detect.
DIS_AUTO_
When this register is set to 1 (automatic 0b0: Tunneling disabled
SER_LANE_ 7
detection of SER lane count is disabled), 0b1: Tunneling enabled
DET
TUN_SER_LANE_NUM register will need to
be set to the SER lane count.
Disable auto tunneling mode detect.
When this register is set to 1 (automatic

DIS_AUTO_ 0b0: Tunneling disabled
6 detection of tunneling mode disabled),
TUN_DET 0b1: Tunneling enabled
TUN_EN registers will set pixel mode
(TUN_EN = 0) or tunneling mode (TUN_EN
=1).
0x0: Controller 0
TUN_DEST 5:4 Tunneling Controller Destination
0x1: Controller 1
Only used when
TUN_DPHY_TO_CPHY_CONV_OVRD bit is
set.
Manual override bit to enable DPHY to CPHY
conversion in tunneling mode (must also
TUN_DPHY_
disable auto tunneling mode detect 0x0: Controller 0
TO_CPHY_C 2
DIS_AUTO_TUN_DET = 1 and manually set 0x1: Controller 1
ONV
tunneling mode TUN_EN = 1). When set to 0,
SER headers are evaluated to detect DPHY/
CPHY mode, if SER is sending DPHY and
the DES MIPI PHY is sent to CPHY mode,
conversion is turn on.
TUN_DPHY_ Enable value in
0x0: Controller 0
TO_CPHY_C 1 TUN_DPHY_TO_CPHY_CONV register to
0x1: Controller 1
ONV_OVRD override automatic detection.
TUN_NO_C
Do not enable header error packet length 0b0: Tunneling error correction enabled
ORR_LENG 0
correction in tunneling mode 0b1: Tunneling error correction disabled
TH
MIPI_ERR_INJ_B1 (0x9BA, 0x9FA)
BIT 7 6 5 4 3 2 1 0
DCPHY_C
INJ_B1_EN
Reset 0b0 – – 0x00
Access Write Clears
– – Write, Read
Type All, Read

Enable Error Injection for the first bit error
DCPHY_CO
NV_ERR_IN 7
J_B1_EN
will self clear.


First Bit Error injection location in the DPHY
header. 0-7: DATA ID (DT)
DCPHY_CO
NV_ERR_IN 4:0
J_B1_SITE
during tunnel mode.
MIPI_ERR_INJ_B2 (0x9BB, 0x9FB)
BIT 7 6 5 4 3 2 1 0
DCPHY_C
INJ_B2_EN
Reset 0b0 – – 0x00
Access Write Clears
– – Write, Read
Type All, Read

Enable Error Injection for the second bit error
DCPHY_CO
NV_ERR_IN 7
J_B2_EN
will self clear.
Second Bit Error injection location in the
DPHY header. 0-7: DATA ID (DT)
DCPHY_CO
NV_ERR_IN 4:0
J_B2_SITE
during tunnel mode.
MIPI_DESKEW_ERRB_ORDER (0x9BC, 0x9FC)
BIT 7 6 5 4 3 2 1 0
DESKEW_ DESKEW_ DESKEW_
BEFORE_E AFTER_ER BEFORE_V
Field – – – – –
RRB_PKT_ RB_PKT_M S_PKT_MO
MODE ODE DE
Reset – – – – 0x0 0x0 –
Access
– – – – Write, Read Write, Read Write, Read –
Type


This register,
DESKEW_BEFORE_ERRB_PKT_MODE,
has priority over
DESKEW_B 0x0: DESKEW may occur before or after
EFORE_ER ERRB_PKT depending on other registers (see
3 DESKEW, VS, and ERRB_PKT, please
RB_PKT_MO complete table)
consider these registers:
DE 0x1: DESKEW occurs before ERRB_PKT
ERRB_PKT_Insert_Mode[1:0]
ERRB_PKT_EDGE_SEL
DESKEW_PER[6]


consider these registers: 0x0: DESKEW may occur before or after
DESKEW_A
ERRB_PKT depending on other registers (see
FTER_ERRB 2
ERRB_PKT_Insert_Mode[1:0] complete table)
_PKT_MODE
ERRB_PKT_EDGE_SEL 0x1: DESKEW occurs after ERRB_PKT
DESKEW_PER[6]

occurs relative to a VS ( frame-start or frame-
end) pkt.

DESKEW_B consider these registers:
0x0: DESKEW occurs after the VS pkt
EFORE_VS_ 1
0x1: DESKEW occurs before the VS pkt
PKT_MODE ERRB_PKT_Insert_Mode[1:0]
ERRB_PKT_EDGE_SEL
DESKEW_PER[6]

GMSL1_4 (0xB04, 0xC04, 0xD04, 0xE04)
BIT 7 6 5 4 3 2 1 0
CC_PORT_
Field – – PRBSEN – – REVCCEN FWDCCEN
SEL
Reset – – 0x0 – 0b0 – 0x1 0x1
Access
– – Write, Read – Write, Read – Write, Read Write, Read
Type

PRBS test enable (in HIBW mode, 0b0: Set device normal operation
PRBSEN 5
PRBS_TYPE—0xB0F must be set to zero) 0b1: Enable PRBS test
CC_PORT_S Selects which I2C port is connected to this 0b00: Port 0 (RX0_SDA0, TX0_SCL0)
3
EL link 0b01: Port 1 (RX1_SDA1, TX1_SCL1)
Enables reverse control channel from 0b0: Disable reverse control channel receiver
REVCCEN 1
deserializer 0b1: Enable reverse control channel receiver
Enables forward control channel to 0b0: Disable forward control channel transmitter
FWDCCEN 0
deserializer 0b1: Enable forward control channel transmitter
GMSL1_5 (0xB05, 0xC05, 0xD05, 0xE05)
BIT 7 6 5 4 3 2 1 0
NO_REM_ HVTR_MO
Field RSVD EN_EQ EQTUNE[3:0]
MST DE
Access
Type

Set to 1 to indicate that there is no I2C master
NO_REM_M on remote side so this (local) chip should 0b0: Master
6
ST ignore any I2C packet initiation (start 0b1: No master
condition) from remote side
HVTR_MOD 0b0: Use partial periodic HV tracking
5 HV tracking allows continuous HSYNC format
E 0b1: Use partial and full periodic HV tracking
Enables equalizer for manual and adaptive 0b0: Disable equalization
EN_EQ 4
modes 0b1: Enable equalization
0b0000: 1.6dB manual EQ setting
Equalizer boost level at 750 MHz 0b0111: 7.3dB manual EQ setting
EQTUNE 3:0
(effective when adaptive EQ is turned off) 0b1000: 8.5dB manual EQ setting
0b1010: 11dB manual EQ setting
0b1100: Reserved
0b1101: Reserved
0b1110: Reserved
0b1111: Reserved

GMSL1_6 (0xB06, 0xC06, 0xD06, 0xE06)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E GPI_COMP GPI_RT_E
Field HIGHIMM I2C_RT_EN HV_SRC[2:0]
N _EN N
Reset 0x0 0x1 0x1 0x0 0x1 0x7
Access
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Type

0b0: Reverse channel high immunity mode
Reverse channel high immunity mode
disabled
HIGHIMM 7 (initial value set by the CFG1/MFP6 pin state
0b1: Reverse channel high immunity mode
at power-up)
enabled
0b0: Disable maximum retransmission limit
MAX_RT_EN 6 Maximum retransmission limit enable
0b1: Enable maximum retransmission limit
0b0: Disable I2C retransmission
I2C_RT_EN 5 I2C retransmission enable
0b1: Enable I2C retransmission enable
Reverse channel high immunity mode
GPI_COMP_ 0b0: Disable GPI skew compensation
4 (initial value set by the CFG1/MFP6 pin state
EN 0b1: Enable GPI skew compensation
at power-up)
0b0: Disable GPI retransmission
GPI_RT_EN 3 GPI retransmission enable
0b1: Enable GPI retransmission
0b000: Use D18/D19 for HS/VS (use this setting
when the serializer is a 3.125Gbps device or if
HIBW mode is used; otherwise, this setting is for
use with the MAX9273 when DBL = 0 or HVEN =
1)
0b001: Use D14/D15 for HS/VS (for use with the
MAX9271/ MAX96705 when DBL = 0 or HVEN =
1)
HV_SRC 2:0 HS_VS bit selection MAX96707 when DBL = 0 or HVEN = 1)
MAX9271/ MAX9273/MAX96705/MAX96707 when
DBL = 1 and HVEN = 0)
0b100: Reserved
0b101: Reserved
0b110: Automatically determine the source of
HSYNC/VSYNC (for use with the MAX96707)
0b111: Automatically determine the source of
HSYNC/VSYNC (for use with the MAX96705)
GMSL1_7 (0xB07, 0xC07, 0xD07, 0xE07)
BIT 7 6 5 4 3 2 1 0
Field DBL DRS BWS – HIBW HVEN – PXL_CRC
Reset 0x0 0x0 0x0 – 0x0 0x1 – 0x0
Access
Write, Read Write, Read Write, Read – Write, Read Write, Read – Write, Read
Type

0b0: Use single-rate output
DBL 7 Double-output mode 0b1: Use double-rate output (2x word rate at 1/2x
width)


0b0: Use normal data rate output
DRS 6 Data rate select 0b1: Use 1/2 rate data output (for use with low data
rates)
0b0: Set bus width for 22-/24-bit bus, 24-/27-bit
BWS 5 Bus width select mode (depending on HIBW setting)
0b1: Set bus width for 30-bit bus (32-bit mode)
0b0: Disable high-bandwidth mode
HIBW 3 High-bandwidth mode 0b1: Enable high-bandwidth mode (when BWS =
0)
0b0: Disable HS/VS encoding
HVEN 2 HS/VS encoding enable
0b1: Enable HS/VS encoding
Pixel error detection type (this is controllable 0b0: Use 1-bit parity (compatible with all devices)
PXL_CRC 0
by pin when LCCEN = 0) 0b1: Use 6-bit CRC
GMSL1_8 (0xB08, 0xC08, 0xD08, 0xE08)
BIT 7 6 5 4 3 2 1 0
EN_FSYNC
Field GPI_SEL[1:0] GPI_EN – PKTCC_EN CC_CRC_LENGTH[1:0]
_TX
Reset 0x0 0x1 0x0 – 0x0 0x1
Access
Write, Read Write, Read Write, Read – Write, Read Write, Read
Type

0b00: GPI_0
0b01: GPI_1
GPI_SEL 7:6 Selects GPI pin to transmit to serializer
0b10: GPI_2
0b11: GPI_3
Enables GPI-to-GPO signal transmission to 0b0: Disable GPI-to-GPO transmission
GPI_EN 5
serializer 0b1: Enable GPI-to-GPO transmission
EN_FSYNC_ 0b0: Disable frame sync signal transmission
4 Enables frame sync signal transmission
TX 0b1: Enable frame sync signal transmission
0b0: Disable packet-based control-channel mode
PKTCC_EN 2 Packet-based control-channel mode enable
0b1: Enable packet-based control-channel mode
0b00: 1-bit CRC
CC_CRC_LE 0b01: 5-bit CRC
1:0 Control channel CRC length
NGTH 0b10: 8-bit CRC
0b11: Reserved
GMSL1_D (0xB0D, 0xC0D, 0xD0D, 0xE0D)
BIT 7 6 5 4 3 2 1 0
I2C_LOC_A HS_TRACK
Field RSVD – – – RSVD RSVD
CK _FSYNC
Reset 0x0 0x0 – – – 0x0 0x0 0x0
Access
Write, Read – – – Write, Read
Type


0b0: Disable local acknowledge when forward
I2C_LOC_A Enables I2C-to-I2C slave local acknowledge channel is not available
7
CK when forward channel is not available 0b1: Enable local acknowledge when forward
channel is not available
HS_TRACK_ 0 = Allow infinite length vertical blanking 0x0: Allow infinite length vertical blanking
2
FSYNC 1 = Lose HLOCKED with VLOCKED 0x1: Lose HLOCKED with VLOCKED
GMSL1_E (0xB0E, 0xC0E, 0xD0E, 0xE0E)
BIT 7 6 5 4 3 2 1 0
Field DET_THR[7:0]
Reset 0x00
Access
Write, Read
Type

0xXX: Number of errors for detected error
DET_THR 7:0 Threshold for detected errors
threshold
GMSL1_F (0xB0F, 0xC0F, 0xD0F, 0xE0F)
BIT 7 6 5 4 3 2 1 0
EN_DE_FIL EN_HS_FIL EN_VS_FIL PRBS_TYP
Field – DE_EN – –
T T T E
Reset – 0x0 0x0 0x0 0x0 – – 0x1
Access
– Write, Read Write, Read Write, Read Write, Read – – Write, Read
Type

0b0: Disable DE glitch filtering
EN_DE_FILT 6 Enables glitch filtering on DE
0b1: Enable DE glitch filtering
0b0: Disable HS glitch filtering
EN_HS_FILT 5 Enables glitch filtering on HS
0b1: Enable HS glitch filtering
0b0: Disable VS glitch filtering
EN_VS_FILT 4 Enables glitch filtering on VS
0b1: Enable VS glitch filtering
Enables processing separate HS and DE 0b0: Disable processing HS and DE signals
DE_EN 3
signals 0b1: Enable processing HS and DE signals
PRBS type select (in HIBW mode, set 0b0: GMSL legacy style PRBS test
PRBS_TYPE 0
PRBS_TYPE = 0) 0b1: MAX9272 style PRBS test
GMSL1_10 (0xB10, 0xC10, 0xD10, 0xE10)
BIT 7 6 5 4 3 2 1 0
RCEG_BO
Field RCEG_TYPE[1:0] RCEG_ERR_NUM[3:0] RCEG_EN
UND
Access
Type


0b00: Random
0b01: Short burst
RCEG_TYPE 7:6 Reverse channel generated error type
0b10: Long burst
0b11: Long burst
RCEG_BOU Reverse channel generated error boundary 0b0: Errors are unbounded to symbols
5
ND (effective when RCEG_TYPE = 0x) 0b1: Errors are bounded to symbols
RCEG_ERR Number of RCEG errors generated with each
4:1 0xX: Number of errors generated per request
_NUM request (effective when RCEG_TYPE = 0x)
0b0: Disable reverse channel error generator
RCEG_EN 0 Enable reverse channel error generator 0b1: Enable reverse channel error generator
enabled
GMSL1_11 (0xB11, 0xC11, 0xD11, 0xE11)
BIT 7 6 5 4 3 2 1 0
Field RCEG_ERR_RATE[3:0] RCEG_LO_BST_PRB[1:0] RCEG_LO_BST_LEN[1:0]
Reset 0xF 0x0 0x0
Access
Type

0x0: Rate is 2-3
0x1: Rate is 2-4
Error generation rate in terms of bit time = 0x2: Rate is 2-5
RCEG_ERR
7:4 2-(RCEG_ERR_RATE + 3). ...
_RATE
Effective when RCEG_TYPE = 0X. ...
...
0xF: Rate is 2-18
0b00: 1/1024
RCEG_LO_B Long burst error probability. 0b01: 1/128
3:2
ST_PRB Effective when RCEG_TYPE = 10. 0b10: 1/32
0b11: 1/8
0b00: Continuous
RCEG_LO_B Long burst error length in terms of bit time. 0b01: 128 (~150μs)
1:0
ST_LEN Effective when RCEG_TYPE = 10. 0b10: 8192 (~9.83ms)
0b11: 1048576 (~1.26s)
GMSL1_12 (0xB12, 0xC12, 0xD12, 0xE12)
BIT 7 6 5 4 3 2 1 0
UNDERBST CC_CRC_E LINE_CRC_ MAX_RT_E RCEG_ER
Field LINE_CRC_LOC[1:0] –
_DET_EN RR_EN EN_GMSL1 RR_EN R_PER_EN
Reset 0x0 0b1 0x1 0x0 – 0b1 0x0
Access
Write, Read Write, Read Write, Read Write, Read – Write, Read Write, Read
Type

UNDERBST_ 0b0: Disable underboost detection
7 Enable underboost detection
DET_EN 0b1: Enable underboost detection


Enables reporting of (CC_CRC_ERR_CNT >
0) on the ERRB pin.
Note: This only applies to the composite

GMSL1 error output to the ERRB pin. See
CC_CRC_E
6 registers G1_A_ERR_OEN,
RR_EN
G1_B_ERR_OEN, G1_C_ERR_OEN, and
G1_D_ERR_OEN
For individual control see register

CC_CRC_ERRB_OEN.
0b00: [1..4]
LINE_CRC_L 0b01: [5..8]
5:4 Video line CRC insertion location
OC 0b10: [9..12]
0b11: [13..16]
LINE_CRC_ 0b0: Disable video line CRC
3 Video line CRC enable
EN_GMSL1 0b1: Enable video line CRC
Enables reflection of maximum
retransmission error on the ERRB pin.
Note: This control only applies to the

composite GMSL1 ERRB output. See
registers G1_A_ERRB_OEN,
G1_B_ERRB_OEN, G1_C_ERRB_OEN, and 0b0: Disable maximum retransmission error on the
MAX_RT_ER G1_D_ERRB_OEN ERROR pin
1
R_EN 0b1: Enable maximum retransmission error on the
This applies to both I2C retransmissions as ERROR pin
well as GPI transmissions.
For individual control see registers

MAX_RT_I2C_ERRB_OEN and
MAX_RT_GPI_ERRB_OEN.
RCEG_ERR Periodic error generation enable. 0b0: Disable periodic error generator
0
_PER_EN Effective when RCEG_TYPE (0xB10) = 0x. 0b1: Enable periodic error generator
GMSL1_13 (0xB13, 0xC13, 0xD13, 0xE13)
BIT 7 6 5 4 3 2 1 0
EOM_MAN
EOM_EN_ EOM_PER_
Field _TRG_REQ EOM_MIN_THR_G1[4:0]
G1 MODE_G1
_G1
Access
Type

EOM_EN_G 0b0: Disable EOM
7 Eye-opening monitor enable
1 0b1: Enable EOM
EOM_PER_ 0b0: Set EOM to use nonperiodic mode
6 Eye-opening monitor periodic mode select
MODE_G1 0b1: Set EOM to use periodic mode
Eye-opening monitor (EOM) manual trigger
EOM_MAN_
request. 0b0: Do not trigger EOM
TRG_REQ_ 5
Valid on the rising edge of this bit when not in 0b1: Manually trigger the EOM
G1
periodic mode.


0b00000: Disabled
0b00001: 3.125%
0b00010: 6.25%
EOM_MIN_T Eye-opening minimum threshold (in terms of
4:0 ...
HR_G1 percent) for flagging ERRB pin
...
...
0b11111: 100%
GMSL1_14 (0xB14, 0xC14, 0xD14, 0xE14)
BIT 7 6 5 4 3 2 1 0
AEQ_PER_ AEQ_MAN_
Field AEQ_EN EOM_PER_THR[4:0]
MODE TRG_REQ
Access
Type

0b0: Disable AEQ
AEQ_EN 7 Adaptive equalization enable
0b1: Enable AEQ
AEQ_PER_ 0b0: Set AEQ to use nonperiodic mode
6 Adaptive equalizer periodic mode select
MODE 0b1: Set AEQ to use periodic mode
Adaptive equalizer manual fine-tune request
AEQ_MAN_T 0b0: Do not trigger AEQ fine tuning
5 enable. Valid on the rising edge of this bit
RG_REQ 0b1: Manually trigger the AEQ fine tuning
when not in periodic mode.
0b00000: Eye-opening threshold is disabled
EOM_PER_T Eye-opening threshold to trigger a fine-tune 0b10000: 50% eye-opening triggers fine-tune
4:0
HR operation operation
All other values: Reserved
GMSL1_15 (0xB15, 0xC15, 0xD15, 0xE15)
BIT 7 6 5 4 3 2 1 0
Field DET_ERR[7:0]
Reset 0x00
Access
Read Only
Type

DET_ERR 7:0 Detected error counter 0xXX: Number of detected errors
GMSL1_16 (0xB16, 0xC16, 0xD16, 0xE16)
BIT 7 6 5 4 3 2 1 0
Field PRBS_ERR[7:0]
Reset 0x00
Access
Read Only
Type

PRBS_ERR 7:0 PRBS error counter 0xXX: Number of detected PRBS errors

GMSL1_17 (0xB17, 0xC17, 0xD17, 0xE17)
BIT 7 6 5 4 3 2 1 0
MAX_RT_E MAX_RT_E
Field RSVD PRBS_OK GPI_IN – – –
RR_I2C RR_GPI
Reset 0x0 0x0 0x0 0x0 0x0 – – –
Access
Read Only Read Only Read Only Read Only – – –
Type

0b0: No control-channel retransmission error
MAX_RT_ER Maximum retransmission error flag. Cleared
6 0b1: Control-channel retransmission maximum
R_I2C when read.
limit reached
MAX9271/73 compatible PRBS test for link is 0b0: No MAX9271/MAX9273 compatible PRBS
completed normally. Check PRBS_ERR test completed
PRBS_OK 5
register for the PRBS success. For other 0b1: MAX9271/MAX9273 compatible PRBS test
SERDES read PRBS_ERR registers. completed normally
0b0: GPI is input low
GPI_IN 4 GPI pin level
0b1: GPI is input high
0b0: No control-channel retransmission error
MAX_RT_ER Maximum retransmission error flag. Cleared
3 0b1: Control-channel retransmission maximum
R_GPI when read.
limit reached
GMSL1_18 (0xB18, 0xC18, 0xD18, 0xE18)
BIT 7 6 5 4 3 2 1 0
Field CC_RETR_CNT[7:0]
Reset 0x00
Access
Read Only
Type

CC_RETR_C
7:0 I2C packet retransmit count 0xXX: Number of I2C packets retransmitted
NT
GMSL1_19 (0xB19, 0xC19, 0xD19, 0xE19)
BIT 7 6 5 4 3 2 1 0
Field CC_CRC_ERRCNT[7:0]
Reset 0x00
Access
Read Only
Type

CC_CRC_E Packet-based control-channel CRC error
7:0 0xXX: Number of control-channel CRC errors
RRCNT counter

GMSL1_1A (0xB1A, 0xC1A, 0xD1A, 0xE1A)
BIT 7 6 5 4 3 2 1 0
Field RCEG_ERR_CNT[7:0]
Reset 0x00
Access
Read Only
Type

RCEG_ERR
7:0 Control-channel number of generated errors 0xXX: Number of control-channel generated errors
_CNT
GMSL1_1B (0xB1B, 0xC1B, 0xD1B, 0xE1B)
BIT 7 6 5 4 3 2 1 0
LINE_CRC_
Field – – – – – – –
ERR
Reset – – – – – 0x0 – –
Access
– – – – – Read Only – –
Type

LINE_CRC_ CRC error bit. Latched on error, cleared to 0 0b0: Video line CRC ok
2
ERR when read. 0b1: Video line CRC mismatch detected
GMSL1_1C (0xB1C, 0xC1C, 0xD1C, 0xE1C)
BIT 7 6 5 4 3 2 1 0
Field – – EOM_EYE_WIDTH[5:0]
Reset – – 0x00
Access
– – Read Only
Type

0b000000: Width is 0%
0b000001: Width is 1/63 x 100%
0b000010: Width is 2/63 x 100%
EOM_EYE_ Measured eye opening. Opening width =
5:0 ...
WIDTH EOM_EYE_WIDTH/63 x 100%
...
...
0b11111: Width is 63/63 x 100%
GMSL1_1D (0xB1D, 0xC1D, 0xD1D, 0xE1D)
BIT 7 6 5 4 3 2 1 0
UNDERBO
Field – – – AEQ_BST[3:0]
OST_DET
Reset – – – 0x0 0x0
Access
– – – Read Only Read Only
Type


UNDERBOO 0b0: Normal operation
4 Underboost detected
ST_DET 0b1: Underboost (at maximum AEQ gain) detected
Adaptive equalizer boost value. Selected
AEQ_BST 3:0 adaptive equalizer value; settings correspond
to gain at 750MHz
0b1010: 11dB manual EQ setting
0b1100: Reserved
0b1101: Reserved
0b1110: Reserved
0b1111: Reserved
GMSL1_20 (0xB20, 0xC20, 0xD20, 0xE20)
BIT 7 6 5 4 3 2 1 0
Field CRC_VALUE_0[7:0]
Reset 0x00
Access
Read Only
Type

CRC_VALUE
7:0 Bits [7:0] of CRC output for the latest line 0xXX: CRC[7:0] of latest line
_0
GMSL1_21 (0xB21, 0xC21, 0xD21, 0xE21)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Read Only
Type

CRC_VALUE
_1
GMSL1_22 (0xB22, 0xC22, 0xD22, 0xE22)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Read Only
Type


CRC_VALUE
_2
GMSL1_23 (0xB23, 0xC23, 0xD23, 0xE23)
BIT 7 6 5 4 3 2 1 0
Reset 0x00
Access
Read Only
Type

CRC_VALUE
_3
GMSL1_96 (0xB96, 0xC96, 0xD96, 0xE96)
BIT 7 6 5 4 3 2 1 0
CONV_GM DBL_ALIGN
Field CONV_GMSL1_DATATYPE[4:0] RSVD
SL1_EN _TO
Access
Type


0x0: RGB888 OLDI
0x1: RGB565
0x2: RGB666
0x3: YUV422 8-bit mux mode (use
yuv_8_10_mux_mode)
0x4: YUV422 10-bit mux mode (use
yuv_8_10_mux_mode)
0x5: RAW8 single
0x6: RAW10 single
0x7: RAW12 single
0x8: RAW14
0x9: User-defined generic 24-bit
0xA: User-defined YUV422 12-bit
0xB: User-defined generic 8-bit
0xC: Reserved
0xD: Reserved
CONV_GMS
Converts from GMSL1 color format mapping 0xE: Reserved
L1_DATATY 7:3
to GMSL2 CSI transmitter color format 0xF: Reserved
PE
0x10: RGB888 VESA
0x11: Reserved
0x12: Reserved
0x13: YUV422 8-bit normal mode
0x14: YUV422 10-bit normal mode
0x15: RAW8 double (use alt_mem_map8)
0x18: Reserved
0x19: Reserved
0x1A: Reserved
0x1B: Reserved
0x1C: Reserved
0x1D: Reserved
0x1E: Reserved
0x1F: Reserved
0x0: GMSL1 color format conversion to GMSL2 not
CONV_GMS Enable conversion from GMSL1 color format Enabled
1
L1_EN mapping to GMSL2 CSI transmitter 0x1: GMSL1 color format conversion to GMSL2
Enabled
HBM DBL mode type
DBL_ALIGN_
0 1 = DBL-DBL mode with no alignment(d)
TO
0 = DBL-Single mode with alignment
GMSL1_CB (0xBCB, 0xCCB, 0xDCB, 0xECB)
BIT 7 6 5 4 3 2 1 0
LOCKED_G
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD
1
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access
Read Only
Type

0b0: Link not locked
LOCKED_G1 0 Link Locked
0b1: Link locked

TX1 (0x1001)
BIT 7 6 5 4 3 2 1 0
Field RSVD – – ERRG_EN – – RSVD RSVD
Reset 0b0 – – 0b0 – – 0b0 0b0
Access
– – Write, Read – –
Type

0b0: Disable error generator for Link A
ERRG_EN 4 Error generator enable
0b1: Enable error generator for Link A
TX2 (0x1002)
BIT 7 6 5 4 3 2 1 0
Field ERRG_CNT[1:0] ERRG_RATE[1:0] ERRG_BURST[2:0] ERRG_PER
Reset 0x0 0x2 0x0 0b0
Access
Type

0b00: Continuous
0b01: 16
ERRG_CNT 7:6 Number of errors to be generated
0b10: 128
0b11: 1024
0b00: 1/5120 bits
ERRG_RAT 0b01: 1/81920 bits
5:4 Error generator average bit error rate
E 0b10: 1/1310720 bits
0b11: 1/20971520 bits
0b000: 1
0b001: 2
0b010: 3
ERRG_BUR 0b011: 4
3:1 Error generator burst error length
ST 0b100: 8
0b101: 12
0b110: 16
0b111: 20
0b0: Pseudorandom
ERRG_PER 0 Error generator error distribution selection
0b1: Periodic
TX3 (0x1003)
BIT 7 6 5 4 3 2 1 0
Field RSVD[1:0] – – – TIMEOUT[2:0]
Reset 0x1 – – – 0x4
Access
Type


0b000: 0.5 x Timeout Base
Link ARQ Timeout Duration Multiplier 0b001: 1.0 x Timeout Base
Multiplies a timeout base constant to set the 0b011: 2.0 x Timeout Base
TIMEOUT 2:0
ARQ timeout. 0b100: 2.5 x Timeout Base
Timeout Base = 8μs 0b110: 3.5 x Timeout Base
RX0 (0x1004)
BIT 7 6 5 4 3 2 1 0
Field PKT_CNT_LBW[1:0] – RSVD PKT_CNT_SEL[3:0]
Reset 0x0 – 0b0 0x0
Access
Type

0b00: Count data packets
PKT_CNT_L Select the sub-type of low-bandwidth packets 0b01: Count acknowledge packets
7:6
BW to count at PKT_CNT register 0b10: Count data and acknowledge packets
0b11: Reserved
0b0000: None
0b0001: Video
0b0010: Reserved
0b0011: INFOFR
0b0100: Reserved
0b0101: I2C
0b0110: Reserved
PKT_CNT_S Select the type of received packets to count 0b0111: GPIO
3:0
EL at PKT_CNT (0x40–0x43) 0b1000: Reserved
0b1001: Reserved
0b1010: Reserved
0b1011: Reserved
0b1100: Reserved
0b1101: Reserved
0b1110: All non-idle packets
0b1111: Unknown/Error
GPIOA (0x1008)
BIT 7 6 5 4 3 2 1 0
GPIO_TX_
Field RSVD GPIO_FWD_CDLY[5:0]
CASC
Reset 0b0 0x1 0x01
Access
Type

GPIO_TX_C Allow multiple pin transitions to be transmitted 0b0: Multiple pin transitions not allowed
6
ASC in the same packet 0b1: Multiple pin transitions allowed


Compensation delay multiplier for the forward
direction. This must be same value as
GPIO_FWD_ GPIO_FWD_CDLY of the chip on the other 0bXXXXXX: Forward compensation delay
5:0
CDLY side of the link. multiplier value
Total delay is the (value + 1) multiplied by
1.7μs. Default delay is 3.4μs.
GPIOB (0x1009)
BIT 7 6 5 4 3 2 1 0
Field GPIO_TX_WNDW[1:0] GPIO_REV_CDLY[5:0]
Reset 0x2 0x08
Access
Type

Wait time after a GPIO transition to create a
0b00: Disabled
packet. This allows grouping transitions of
GPIO_TX_W 0b01: 200ns
7:6 different GPIO inputs in a single packet and
NDW 0b10: 500ns
so increases GPIO bandwdith usage
0b11: 1000ns
efficiency.
Compensation delay multiplier for the reverse
GPIO_REV_ GPIO_REV_CDLY of the chip on the other 0bXXXXXX: Reverse compensation delay
5:0
TX1 (0x1011, 0x1021, 0x1031)
BIT 7 6 5 4 3 2 1 0
Field RSVD – – ERRG_EN – – RSVD RSVD
Reset 0b0 – – 0b0 – – 0b0 0b0
Access
– – Write, Read – –
Type

0b0: Disable error generator
ERRG_EN 4 Error generator enable
0b1: Enable error generator
TX2 (0x1012, 0x1022, 0x1032)
BIT 7 6 5 4 3 2 1 0
Field ERRG_CNT[1:0] ERRG_RATE[1:0] ERRG_BURST[2:0] ERRG_PER
Reset 0x0 0x2 0x0 0b0
Access
Type


0b00: Continuous
0b01: 16 errors
ERRG_CNT 7:6 Number of errors to be generated
0b10: 128 errors
0b11: 1024 errors
0b00: 1/5120 bits
ERRG_RAT 0b01: 1/81920 bits
5:4 Error generator average bit error rate
E 0b10: 1/1310720 bits
0b11: 1/20971520 bits
0b000: 1
0b001: 2
0b010: 3
ERRG_BUR 0b011: 4
3:1 Error generator burst error length
ST 0b100: 8
0b101: 12
0b110: 16
0b111: 20
0b0: Pseudorandom
ERRG_PER 0 Error generator error distribution selection
0b1: Periodic
TX3 (0x1013, 0x1023, 0x1033)
BIT 7 6 5 4 3 2 1 0
Field RSVD[1:0] – – – TIMEOUT[2:0]
Reset 0x1 – – – 0x4
Access
Type

Link ARQ Timeout Duration Multiplier 0b001: 1.0 x Timeout Base
Multiplies a timeout base constant to set the 0b011: 2.0 x Timeout Base
TIMEOUT 2:0
ARQ timeout. 0b100: 2.5 x Timeout Base
Timeout Base = 8μs 0b110: 3.5 x Timeout Base
RX0 (0x1014, 0x1024, 0x1034)
BIT 7 6 5 4 3 2 1 0
Field PKT_CNT_LBW[1:0] – RSVD PKT_CNT_SEL[3:0]
Reset 0x0 – 0b0 0x0
Access
Type

0b00: Count data packets
Selects the sub-type of low-bandwidth
PKT_CNT_L 0b01: Count acknowledge packets
7:6 packets to count at PKT_CNT_x bitfield
BW 0b10: Count data and acknowledge packets
(0x40–0x43).
0b11: Reserved


0x0: None
0x1: Video
0x2: Reserved
0x3: INFOFR
0x4: Reserved
0x5: I2C
0x6: Reserved
PKT_CNT_S Selects the type of received packets to count 0x7: GPIO
3:0
EL at PKT_CNT_x bitfield (0x40–0x43) 0x8: Reserved
0x9: Reserved
0xA: Reserved
0xB: Reserved
0xC: Reserved
0xD: Reserved
0xE: All non-idle packets
0xF: Unknown/Error
GPIOA (0x1018, 0x1028, 0x1038)
BIT 7 6 5 4 3 2 1 0
GPIO_TX_
Field RSVD GPIO_FWD_CDLY[5:0]
CASC
Reset 0b0 0x1 0x01
Access
Type

GPIO_TX_C Allows multiple pin transitions to be 0b0: Multiple pin transitions not allowed
6
ASC transmitted in the same packet 0b1: Multiple pin transitions allowed
Compensation delay multiplier for the forward
GPIO_FWD_ GPIO_FWD_CDLY of the chip on the other 0bXXXXXX: Forward compensation delay
5:0
GPIOB (0x1019, 0x1029, 0x1039)
BIT 7 6 5 4 3 2 1 0
Field GPIO_TX_WNDW[1:0] GPIO_REV_CDLY[5:0]
Reset 0x2 0x08
Access
Type

Wait time after a GPIO transition to create a
0b00: Disabled
packet. This allows grouping transitions of
GPIO_TX_W 0b01: 200 ns
7:6 different GPIO inputs in a single packet and
NDW 0b10: 500 ns
so increases GPIO bandwidth usage
0b11: 1000 ns
efficiency.


Compensation delay multiplier for the reverse
GPIO_REV_ GPIO_REV_CDLY of the chip on the other 0bXXXXXX: Reverse compensation delay
5:0
PATGEN_0 (0x1050)
BIT 7 6 5 4 3 2 1 0
Field GEN_VS GEN_HS GEN_DE VS_INV HS_INV DE_INV VTG_MODE[1:0]
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x3
Access
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Type

Enable to generate VS output according to 0b0: Do not generate VS
GEN_VS 7
the timing definition 0b1: Generate VS
Enable to generate HS output according to
the timing definition 0b0: Do not generate HS
GEN_HS 6
Also, consider setting LS_LE_EN* to 1 as this 0b1: Generate HS
bit defaults to 0 for some parts.
Enable to generate DE output according to 0b0: Do not generate DE
GEN_DE 5
the timing definition 0b1: Generate DE
Inverts VSYNC output of video timing 0b0: Do not invert VS
VS_INV 4
generator 0b1: Invert VS
Inverts HSYNC output of video timing 0b0: Do not invert HS
HS_INV 3
generator 0b1: Invert HS
0b0: Do not invert DE
DE_INV 2 Inverts DE output of video timing generator
0b1: Invert DE


Video interface timing generation mode.
00 or 11 = VS tracking mode. VS input’s

period (VS_HIGH + VS_LOW) is tracked.
After VS tracking is locked, any VS input
edge (glitches) not in the expected PCLK
cycle is ignored. VS tracking is locked with
three consecutive matches and unlocked by
three consecutive mismatches. When
unlocked or power-up, the next VS input edge
is assumed to be the right VS edge.
01 = VS one-trigger mode
One VS input edge will trigger the generation
of one frame of VSO/HSO/DEO. If next VS 0b00: VS tracking mode
input edge comes earlier or later than 0b01: VS on trigger mode
VTG_MODE 1:0
expected by VS period, the newly generated 0b10: Auto-repeat mode
frame will be correct. The current VSO/HSO/ 0b11: Free-running mode
DEO will be cut or extended at the time point
of rising edge of the newly generated VSO/
HSO/DEO.
10 = Auto-repeat mode (default)

VS input edge will trigger the generation of
continuous frames of VSO/HSO/DEO even if
there are no more VS input edges. If next VS
input edge comes earlier or later than
expected by VS period, the newly generated
frame will be correct. The current VSO/HSO/
DEO will be cut or extended at the time point
of rising edge of the newly generated VSO/
HSO/DEO.
PATGEN_1 (0x1051)
BIT 7 6 5 4 3 2 1 0
GRAD_MO
Field – PATGEN_MODE[1:0] – – – VS_TRIG
DE
Reset 0x0 – 0x0 – – – 0x0
Access
Write, Read – Write, Read – – – Write, Read
Type

GRAD_MOD 0b0: Gradient mode disabled
7 Gradient pattern generator mode
E 0b1: Gradient mode enabled
0b00: Reserved
PATGEN_M 0b01: Generate checkerboard pattern
5:4 Pattern generator mode
ODE 0b10: Generate gradient pattern
0b11: Reserved
0b0: Falling edge
VS_TRIG 0 Select VS trigger edge
0b1: Rising edge

VS_DLY_2 (0x1052)
BIT 7 6 5 4 3 2 1 0
Field VS_DLY_2[7:0]
Reset 0x00
Access
Write, Read
Type

VS delay in terms of PCLK cycles. The output
VS_DLY_2 7:0 VS is delayed by VS_DELAY cycles from the 0xXX: Most significant byte of VS delay
input VS. (bits [23:16])
VS_DLY_1 (0x1053)
BIT 7 6 5 4 3 2 1 0
Field VS_DLY_1[7:0]
Reset 0x00
Access
Write, Read
Type

VS_DLY_1 7:0 VS is delayed by VS_DELAY cycles from the 0xXX: Middle significant byte of VS delay
VS_DLY_0 (0x1054)
BIT 7 6 5 4 3 2 1 0
Field VS_DLY_0[7:0]
Reset 0x00
Access
Write, Read
Type

VS_DLY_0 7:0 VS is delayed by VS_DELAY cycles from the 0xXX: Least significant byte of VS delay
VS_HIGH_2 (0x1055)
BIT 7 6 5 4 3 2 1 0
Field VS_HIGH_2[7:0]
Reset 0x00
Access
Write, Read
Type

VS high period in terms of PCLK cycles (bits
VS_HIGH_2 7:0 0xXX: Most significant byte of VS high period
[23:16])

VS_HIGH_1 (0x1056)
BIT 7 6 5 4 3 2 1 0
Reset 0x2A
Access
Write, Read
Type

VS_HIGH_1 7:0 0xXX: Middle significant byte of VS high period
[15:8])
VS_HIGH_0 (0x1057)
BIT 7 6 5 4 3 2 1 0
Reset 0xF8
Access
Write, Read
Type

VS_HIGH_0 7:0 0xXX: Least significant byte of VS high period
[7:0])
VS_LOW_2 (0x1058)
BIT 7 6 5 4 3 2 1 0
Field VS_LOW_2[7:0]
Reset 0x26
Access
Write, Read
Type

VS low period in terms of PCLK cycles (bits
VS_LOW_2 7:0 0xXX: Most significant byte of VS low period
[23:16])
VS_LOW_1 (0x1059)
BIT 7 6 5 4 3 2 1 0
Field VS_LOW_1[7:0]
Reset 0x40
Access
Write, Read
Type

VS_LOW_1 7:0 0xXX: Middle significant byte of VS low period
[15:8])

VS_LOW_0 (0x105A)
BIT 7 6 5 4 3 2 1 0
Field VS_LOW_0[7:0]
Reset 0x00
Access
Write, Read
Type

VS_LOW_0 7:0 0xXX: Least significant byte of VS low period
[7:0])
V2H_2 (0x105B)
BIT 7 6 5 4 3 2 1 0
Field V2H_2[7:0]
Reset 0x00
Access
Write, Read
Type

VS edge to the rising edge of the first HS in 0xXX: Most significant byte of VS edge to first HS
V2H_2 7:0
terms of PCLK cycles (bits [23:16]) rising edge
V2H_1 (0x105C)
BIT 7 6 5 4 3 2 1 0
Field V2H_1[7:0]
Reset 0x00
Access
Write, Read
Type

VS edge to the rising edge of the first HS in 0xXX: Middle significant byte of VS edge to first HS
V2H_1 7:0
V2H_0 (0x105D)
BIT 7 6 5 4 3 2 1 0
Field V2H_0[7:0]
Reset 0x00
Access
Write, Read
Type

VS edge to the rising edge of the first HS in 0xXX: Least significant byte of VS edge to first HS
V2H_0 7:0

HS_HIGH_1 (0x105E)
BIT 7 6 5 4 3 2 1 0
Field HS_HIGH_1[7:0]
Reset 0x00
Access
Write, Read
Type

HS high period in terms of PCLK cycles (bits
HS_HIGH_1 7:0 0xXX: Most significant byte of HS high period
[15:8])
HS_HIGH_0 (0x105F)
BIT 7 6 5 4 3 2 1 0
Field HS_HIGH_0[7:0]
Reset 0xD0
Access
Write, Read
Type

HS high period in terms of PCLK cycles (bits
HS_HIGH_0 7:0 0xXX: Least significant byte of HS high period
[7:0])
HS_LOW_1 (0x1060)
BIT 7 6 5 4 3 2 1 0
Field HS_LOW_1[7:0]
Reset 0x09
Access
Write, Read
Type

HS low period in terms of PCLK cycles (bits
HS_LOW_1 7:0 0xXX: Most significant byte of HS low period
[15:8])
HS_LOW_0 (0x1061)
BIT 7 6 5 4 3 2 1 0
Field HS_LOW_0[7:0]
Reset 0x50
Access
Write, Read
Type

HS low period in terms of PCLK cycles (bits
HS_LOW_0 7:0 0xXX: Least significant byte of HS low period
[7:0])

HS_CNT_1 (0x1062)
BIT 7 6 5 4 3 2 1 0
Field HS_CNT_1[7:0]
Reset 0x04
Access
Write, Read
Type

HS_CNT_1 7:0 HS pulses per frame (bits [15:8]) 0xXX: Most significant byte of HS pulses per frame
HS_CNT_0 (0x1063)
BIT 7 6 5 4 3 2 1 0
Field HS_CNT_0[7:0]
Reset 0xDA
Access
Write, Read
Type

0xXX: Least significant byte of HS pulses per
HS_CNT_0 7:0 HS pulses per frame (bits [7:0])
frame
V2D_2 (0x1064)
BIT 7 6 5 4 3 2 1 0
Field V2D_2[7:0]
Reset 0x00
Access
Write, Read
Type

VS edge to the rising edge of the first DE in
V2D_2 7:0 0xXX: Most significant byte of VS edge to first DE
terms of PCLK cycles (bits [23:16])
V2D_1 (0x1065)
BIT 7 6 5 4 3 2 1 0
Field V2D_1[7:0]
Reset 0x55
Access
Write, Read
Type

V2D_1 7:0 0xXX: Middle significant byte of VS edge to first DE

V2D_0 (0x1066)
BIT 7 6 5 4 3 2 1 0
Field V2D_0[7:0]
Reset 0xF0
Access
Write, Read
Type

V2D_0 7:0 0xXX: Least significant byte of VS edge to first DE
DE_HIGH_1 (0x1067)
BIT 7 6 5 4 3 2 1 0
Field DE_HIGH_1[7:0]
Reset 0x07
Access
Write, Read
Type

DE high period in terms of PCLK cycles (bits
DE_HIGH_1 7:0 0xXX: Most significant byte of DE high period
[15:8])
DE_HIGH_0 (0x1068)
BIT 7 6 5 4 3 2 1 0
Field DE_HIGH_0[7:0]
Reset 0x80
Access
Write, Read
Type

DE high period in terms of PCLK cycles (bits
DE_HIGH_0 7:0 0xXX: Least significant byte of DE high period
[7:0])
DE_LOW_1 (0x1069)
BIT 7 6 5 4 3 2 1 0
Field DE_LOW_1[7:0]
Reset 0x00
Access
Write, Read
Type

DE low period in terms of PCLK cycles (bits
DE_LOW_1 7:0 0xXX: Most significant byte of DE low period
[15:8])

DE_LOW_0 (0x106A)
BIT 7 6 5 4 3 2 1 0
Field DE_LOW_0[7:0]
Reset 0x40
Access
Write, Read
Type

DE low period in terms of PCLK cycles (bits
DE_LOW_0 7:0 0xXX: Least significant byte of DE low period
[7:0])
DE_CNT_1 (0x106B)
BIT 7 6 5 4 3 2 1 0
Field DE_CNT_1[7:0]
Reset 0x04
Access
Write, Read
Type

DE_CNT_1 7:0 Active lines per frame (bits [15:8]) 0xXX: Most significant byte of DE pulses per frame
DE_CNT_0 (0x106C)
BIT 7 6 5 4 3 2 1 0
Field DE_CNT_0[7:0]
Reset 0xB0
Access
Write, Read
Type

0xXX: Least significant byte of DE pulses per
DE_CNT_0 7:0 Active lines per frame (bits [7:0])
frame
GRAD_INCR (0x106D)
BIT 7 6 5 4 3 2 1 0
Field GRAD_INCR[7:0]
Reset 0x06
Access
Write, Read
Type

Gradient mode increment amount
GRAD_INCR 7:0 (increment amount is the register value 0xXX: Gradient increment base
divided by 4)

CHKR_COLOR_A_L (0x106E)
BIT 7 6 5 4 3 2 1 0
Field CHKR_COLOR_A_L[7:0]
Reset 0x80
Access
Write, Read
Type

CHKR_COL 0xXX: Least significant byte of checkerboard mode
7:0 Checkerboard mode color A low byte
OR_A_L color A
CHKR_COLOR_A_M (0x106F)
BIT 7 6 5 4 3 2 1 0
Field CHKR_COLOR_A_M[7:0]
Reset 0x00
Access
Write, Read
Type

CHKR_COL 0xXX: Middle significant byte of checkerboard
7:0 Checkerboard mode color A middle byte
OR_A_M mode color A
CHKR_COLOR_A_H (0x1070)
BIT 7 6 5 4 3 2 1 0
Field CHKR_COLOR_A_H[7:0]
Reset 0x04
Access
Write, Read
Type

CHKR_COL 0xXX: Most significant byte of checkerboard mode
7:0 Checkerboard mode color A high byte
OR_A_H color A
CHKR_COLOR_B_L (0x1071)
BIT 7 6 5 4 3 2 1 0
Field CHKR_COLOR_B_L[7:0]
Reset 0x00
Access
Write, Read
Type

CHKR_COL 0xXX: Least significant byte of checkerboard mode
7:0 Checkerboard mode color B low byte
OR_B_L color B

CHKR_COLOR_B_M (0x1072)
BIT 7 6 5 4 3 2 1 0
Field CHKR_COLOR_B_M[7:0]
Reset 0x08
Access
Write, Read
Type

CHKR_COL 0xXX: Middle significant byte of checkerboard
7:0 Checkerboard mode color B middle byte
OR_B_M mode color B
CHKR_COLOR_B_H (0x1073)
BIT 7 6 5 4 3 2 1 0
Field CHKR_COLOR_B_H[7:0]
Reset 0x80
Access
Write, Read
Type

CHKR_COL 0xXX: Most significant byte of checkerboard mode
7:0 Checkerboard mode color B high byte
OR_B_H color B
CHKR_RPT_A (0x1074)
BIT 7 6 5 4 3 2 1 0
Field CHKR_RPT_A[7:0]
Reset 0x50
Access
Write, Read
Type

CHKR_RPT_
7:0 Checkerboard mode color A repeat count 0xXX: Repeat count of checkerboard mode color A
A
CHKR_RPT_B (0x1075)
BIT 7 6 5 4 3 2 1 0
Field CHKR_RPT_B[7:0]
Reset 0x50
Access
Write, Read
Type

CHKR_RPT_
7:0 Checkerboard mode color B repeat count 0xXX: Repeat count of checkerboard mode color B
B

CHKR_ALT (0x1076)
BIT 7 6 5 4 3 2 1 0
Field CHKR_ALT[7:0]
Reset 0x50
Access
Write, Read
Type

CHKR_ALT 7:0 Checkerboard mode alternate line count 0xXX: Checkerboard mode alternate line count
DP_ORSTB_CTL (0x1191)
BIT 7 6 5 4 3 2 1 0
DPLL_AUT DP_RST_M DP_RST_S DP_RST_M DP_RST_M DP_RST_V DP_RST_F DP_RST_C
Field
O_RST IPI3 TABLE IPI2 IPI P S C
Reset 0x1 0x1 0x1 0b1 0b1 0b1 0b1 0b1
Access
Type

0x0: No auto reset will be generated (If user
changes phy0_csi_tx_dpll_predef_freq, assert
either config_soft_rst_n_CSI1,
config_soft_rst_n_CSI2, or phy_Stdby_n[1:0].
0x1: When changes to
DPLL_AUTO
7 phy#_csi_tx_dpll_predef_freq occur, a reset pulse
_RST
to associated csipll#_rstb is generated.
When changes to phy_4x2, phy_2x4,

force_csi_out_en occur (or any write to 0x08A0), a
reset pulse to all csipll#_rstb is generated.
0b0: Rev B behavior – CMD FIFO read pointer is
not reset automatically when video lock is lost
DP_RST_MI
6 Selects RST mode CMD FIFO read pointer 0b1: (Default) Rev C behavior – CMD FIFO read
PI3
pointer is reset automatically when video lock is
lost
0b0: Do not prevent reset glitches when changing
reset behavior between individualized resets (Rev
C behavior) vs. non-individualized resets (Rev B
DP_RST_ST behavior)
5 Selects RST mode
ABLE 0b1: (Default) Prevent reset glitches when
changing reset behavior between individualized
resets (Rev C behavior) vs. non-individualized
resets (Rev B behavior)
DP_RST_MI 0b1: Rev C behavior – Each MIPI controller can be
4 Selects RST mode to MIPI controllers.
PI2 reset automatically based on the associated GMSL
or link reset


DP_RST_MI
3 Selects RST mode to MIPI controllers. 0b1: Rev C behavior – Each MIPI controller can be
PI
reset individually based on RST_MIPITX_LOC[3:0]
(0x8C9)
0b0: (Default) Rev B behavior – All video pipes will
be reset during any one-shot reset or link reset
DP_RST_VP 2 Selects RST mode to video_rx, vrx blocks. 0b1: Rev C behavior – Each video pipe will be
reset individually based on the associated GMSL
PHY reset during a one-shot reset or link reset
0b0: (Default) Rev B behavior – Frame sync block
DP_RST_FS 1 Selects reset mode to frame sync block 0b1: Rev C behavior – The internal frame sync
block will not be reset during a one-shot reset or
link reset
0b0: (Default) Rev B behavior – All I2C ports will
be reset during any one-shot reset or link reset
DP_RST_CC 0 Selects reset mode for iic_mux_uart blocks 0b1: Rev C behavior – Each I2C port will be reset
individually based on the associated GMSL PHY
reset during a one-shot reset or link reset
CNT_AX (0x11D0)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_AX[7:0]
Reset 0x00
Access
Read Clears All
Type

Total number of video pixel CRC errors
detected at video stream AX. Reset after
reading or with the rising edge of LOCK.
Note: With STREAM_SEL_ALL set to 1 or

VID_PXL_C 0xXX: Total number of video pixel CRC errors
7:0 enabled (default), all Video Pixel CRC Errors
RC_ERR_AX detected at video stream AX
will end up at video stream X only. If desired,
set STREAM_SEL_ALL to 0 or disabled to
allow visibility on specific video pixel stream
CRC errors by matching SER STR_SEL and
DES PIPE_SEL.
CNT_AY (0x11D1)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_AY[7:0]
Reset 0x00
Access
Read Clears All
Type


detected at video stream AY. Reset after

RC_ERR_AY detected at video stream AY
DES PIPE_SEL.
CNT_AZ (0x11D2)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_AZ[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream AZ. Reset after

RC_ERR_AZ detected at video stream AZ
DES PIPE_SEL.
CNT_AU (0x11E0)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_AU[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream AU. Reset after

RC_ERR_AU detected at video stream AU
DES PIPE_SEL.

CNT_BX (0x11E1)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_BX[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream BX. Reset after

RC_ERR_BX detected at video stream BX
DES PIPE_SEL.
CNT_BY (0x11E2)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_BY[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream BY. Reset after

RC_ERR_BY detected at video stream BY
DES PIPE_SEL.
CNT_BZ (0x11E3)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_BZ[7:0]
Reset 0x00
Access
Read Clears All
Type


detected at video stream BZ. Reset after

RC_ERR_BZ detected at video stream BZ
DES PIPE_SEL.
CNT_BU (0x11E4)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_BU[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream BU. Reset after

RC_ERR_BU detected at video stream BU
DES PIPE_SEL.
CNT_CX (0x11E5)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_CX[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream CX. Reset after

RC_ERR_CX detected at video stream CX
DES PIPE_SEL.

CNT_CY (0x11E6)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_CY[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream CY. Reset after

RC_ERR_CY detected at video stream CY
DES PIPE_SEL.
CNT_CZ (0x11E7)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_CZ[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream CZ. Reset after

RC_ERR_CZ detected at video stream CZ
DES PIPE_SEL.
CNT_CU (0x11E8)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_CU[7:0]
Reset 0x00
Access
Read Clears All
Type


detected at video stream CU. Reset after
VID_PXL_C Note: With STREAM_SEL_ALL set to 1 or

0xXX: Total number of video pixel CRC errors
RC_ERR_C 7:0 enabled (default), all Video Pixel CRC Errors
detected at video stream CU
U will end up at video stream X only. If desired,
DES PIPE_SEL.
CNT_DX (0x11E9)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_DX[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream DX. Reset after

RC_ERR_DX detected at video stream DX
DES PIPE_SEL.
CNT_DY (0x11EA)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_DY[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream DY. Reset after

RC_ERR_DY detected at video stream DY
DES PIPE_SEL.

CNT_DZ (0x11EB)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_DZ[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream DZ. Reset after

RC_ERR_DZ detected at video stream DZ
DES PIPE_SEL.
CNT_DU (0x11EC)
BIT 7 6 5 4 3 2 1 0
Field VID_PXL_CRC_ERR_DU[7:0]
Reset 0x00
Access
Read Clears All
Type

detected at video stream DU. Reset after
VID_PXL_C Note: With STREAM_SEL_ALL set to 1 or

0xXX: Total number of video pixel CRC errors
RC_ERR_D 7:0 enabled (default), all Video Pixel CRC Errors
detected at video stream DU
U will end up at video stream X only. If desired,
DES PIPE_SEL.
DE_DET (0x11F0)
BIT 7 6 5 4 3 2 1 0
Field – – – – DE_DET_3 DE_DET_2 DE_DET_1 DE_DET_0
Reset – – – – 0b0 0b0 0b0 0b0
Access
Type

DE activity is detected in Video Pipe 3. Bit 0b0: DE is not detected
DE_DET_3 3
stays high if DE period < ~1ms. 0b1: DE is detected


DE_DET_2 2
DE_DET_1 1
DE_DET_0 0
HS_DET (0x11F1)
BIT 7 6 5 4 3 2 1 0
Field – – – – HS_DET_3 HS_DET_2 HS_DET_1 HS_DET_0
Reset – – – – 0b0 0b0 0b0 0b0
Access
Type

HS activity is detected in Video Pipe 3. Bit 0b0: HS is not detected
HS_DET_3 3
stays high if HS period < ~1ms. 0b1: HS is detected
HS_DET_2 2
HS_DET_1 1
HS_DET_0 0
VS_DET (0x11F2)
BIT 7 6 5 4 3 2 1 0
Field – – – – VS_DET_3 VS_DET_2 VS_DET_1 VS_DET_0
Reset – – – – 0b0 0b0 0b0 0b0
Access
Type

VS activity is detected in Video Pipe 3. Bit 0b0: VS is not detected
VS_DET_3 3
stays high if VS period < ~128ms. 0b1: VS is detected
VS_DET_2 2
VS_DET_1 1
VS_DET_0 0
HS_POL (0x11F3)
BIT 7 6 5 4 3 2 1 0
Field – – – – HS_POL_3 HS_POL_2 HS_POL_1 HS_POL_0
Reset – – – – 0b0 0b0 0b0 0b0
Access
Type


0b0: Active low
HS_POL_3 3 Detected HS polarity in Video Pipe 3
0b1: Active high
0b0: Active low
0b1: Active high
0b0: Active low
0b1: Active high
0b0: Active low
0b1: Active high
VS_POL (0x11F4)
BIT 7 6 5 4 3 2 1 0
Field – – – – VS_POL_3 VS_POL_2 VS_POL_1 VS_POL_0
Reset – – – – 0b0 0b0 0b0 0b0
Access
Type

0b0: Active low
VS_POL_3 3 Detected VS polarity in Video Pipe 3
0b1: Active high
0b0: Active low
0b1: Active high
0b0: Active low
0b1: Active high
0b0: Active low
0b1: Active high
HVD_CNT_CTRL (0x11F9)
BIT 7 6 5 4 3 2 1 0
HVD_CNT_ HVD_CNT_ HVD_CNT_ HVD_CNT_ HVD_CNT_ HVD_CNT_ HVD_CNT_ HVD_CNT_
Field
RST_3 RST_2 RST_1 RST_0 EN_3 EN_2 EN_1 EN_0
Reset 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1
Access
Type

HVD_CNT_R 0x0
7 Reset counter values.
ST_3 0x1: Reset counter values
HVD_CNT_R 0x0
HVD_CNT_R 0x0
HVD_CNT_R 0x0
HVD_CNT_E Enable VS and frames per line counters. 0x0: Disable
3
N_3 0x1: Enable
2
N_2 0x1: Enable


1
N_1 0x1: Enable
0
N_0 0x1: Enable
HVD_CNT_OS (0x11FA)
BIT 7 6 5 4 3 2 1 0
HVD_CNT_ HVD_CNT_ HVD_CNT_ HVD_CNT_
Field – – – –
OS_EN_3 OS_EN_2 OS_EN_1 OS_EN_0
Reset – – – – 0x0 0x0 0x0 0x0
Access
Type

Enable VS and frames per line counters in
HVD_CNT_O one-shot mode. Must be used when 0x0: Disable
3
S_EN_3 HVD_CNT_EN is disabled. 0x1: Enable

HVD_CNT_O 0x0: Disable
2 one-shot mode. Must be used when
S_EN_2 0x1: Enable
HVD_CNT_EN is disabled.
S_EN_1 0x1: Enable
S_EN_0 0x1: Enable
VS_CNT_WNDW_0_MSB (0x1200)
BIT 7 6 5 4 3 2 1 0
VS_CNT_WINDOW_0_M
Field – – – – – –
SB[1:0]
Reset – – – – – – 0x3
Access
– – – – – – Write, Read
Type

VS_CNT_WINDOW_0_ VS counter counts number of frames within window specified in this register in
1:0
MSB milliseconds. Max window at 1.023s. Default set at 1s.
VS_CNT_WNDW_0_LSB (0x1201)
BIT 7 6 5 4 3 2 1 0
Field VS_CNT_WINDOW_0_LSB[7:0]
Reset 0xE8
Access
Write, Read
Type


7:0
LSB milliseconds. Max window at 1.023ms. Default set at 1ms.
VS_CNT_0_CMP (0x1202)
BIT 7 6 5 4 3 2 1 0
Field – – VS_CNT_0_CMP[5:0]
Reset – – 0x0
Access
– – Write, Read
Type

Compare register for VS count value. When this register is non-zero, the
counted value in VS_CNT_x is checked against the value in this register. If
VS_CNT_0_CMP 5:0
the two values are not within +/- 2, the VS_CNT_x_CMP_ERR flag will get
set. When this register is 0, the compare feature is disabled.
HS_CNT_0_CMP_MSB (0x1203)
BIT 7 6 5 4 3 2 1 0
Field – – – – HS_CNT_0_CMP_MSB[3:0]
Reset – – – – 0x0
Access
Type

Upper 4-bits of compare register for HS count value. When this register is
non-zero, the counted value in HS_CNT_x is checked against the value in this
HS_CNT_0_CMP_MSB 3:0
register. If the two values are not within +/- 2, the HS_CNT_x_CMP_ERR flag
will get set. When this register is 0, the compare feature is disabled.
HS_CNT_0_CMP_LSB (0x1204)
BIT 7 6 5 4 3 2 1 0
Field HS_CNT_0_CMP_LSB[7:0]
Reset 0x0
Access
Write, Read
Type

Lower 8-bits of compare register for HS count value. When this register is
HS_CNT_0_CMP_LSB 7:0

DE_CNT_0_CMP_MSB (0x1205)
BIT 7 6 5 4 3 2 1 0
Field – – – – DE_CNT_0_CMP_MSB[3:0]
Reset – – – – 0x0
Access
Type

Upper 4-bits of compare register for DE count value. When this register is
non-zero, the counted value in DE_CNT_x is checked against the value in this
DE_CNT_0_CMP_MSB 3:0
register. If the two values are not within +/- 2, the DE_CNT_x_CMP_ERR flag
DE_CNT_0_CMP_LSB (0x1206)
BIT 7 6 5 4 3 2 1 0
Field DE_CNT_0_CMP_LSB[7:0]
Reset 0x0
Access
Write, Read
Type

Lower 8-bits of compare register for DE count value. When this register is
DE_CNT_0_CMP_LSB 7:0
VS_CNT_0 (0x1207)
BIT 7 6 5 4 3 2 1 0
Field – – VS_CNT_0[5:0]
Reset – –
Access
– – Read Only
Type

VS_CNT_0 5:0 VS counts within window specificed in VS_CNT_WINDOW registers.
HS_CNT_0_MSB (0x1208)
BIT 7 6 5 4 3 2 1 0
Field – – – – HS_CNT_0_MSB[3:0]
Reset – – – –
Access
Type

HS_CNT_0_MSB 3:0 Lines per frame HS counter.

HS_CNT_0_LSB (0x1209)
BIT 7 6 5 4 3 2 1 0
Field HS_CNT_0_LSB[7:0]
Reset
Access
Read Only
Type

HS_CNT_0_LSB 7:0 Lines per frame HS counter.
DE_CNT_0_MSB (0x120A)
BIT 7 6 5 4 3 2 1 0
Field – – – – DE_CNT_0_MSB[3:0]
Reset – – – –
Access
Type

DE_CNT_0_MSB 3:0 Lines per frame DE counter.
DE_CNT_0_LSB (0x120B)
BIT 7 6 5 4 3 2 1 0
Field DE_CNT_0_LSB[7:0]
Reset
Access
Read Only
Type

DE_CNT_0_LSB 7:0 Lines per frame DE counter.
VRX_0_CMP_ERR_OEN (0x120C)
BIT 7 6 5 4 3 2 1 0
VS_CNT_0 HS_CNT_0 DE_CNT_0
Field _CMP_ERR _CMP_ERR _CMP_ERR – – – – –
_OEN _OEN _OEN
Reset 0x1 0x1 0x1 – – – – –
Access
Write, Read Write, Read Write, Read – – – – –
Type

VS_CNT_0_
VS count comparison error flag output 0x0: Disable reporting of error to ERRB pin
CMP_ERR_ 7
enable. Refer to VS_CNT_x_CMP register. 0x1: Enable reporting of error to ERRB pin
OEN
HS_CNT_0_
HS count comparison error flag output 0x0: Disable reporting of error to ERRB pin
CMP_ERR_ 6
enable. Refer to HS_CNT_x_CMP register. 0x1: Enable reporting of error to ERRB pin
OEN


DE_CNT_0_
DE count comparison error flag output 0x0: Disable reporting of error to ERRB pin
CMP_ERR_ 5
enable. Refer to DE_CNT_x_CMP register. 0x1: Enable reporting of error to ERRB pin
OEN
VRX_0_CMP_ERR_FLAG (0x120D)
BIT 7 6 5 4 3 2 1 0
_FLAG _FLAG _FLAG
Reset 0x0 0x0 0x0 – – – – –
Access
Read Only Read Only Read Only – – – – –
Type

VS_CNT_0_
VS count comparison error flag. Refer to 0x0: No VS count error detected
CMP_ERR_F 7
VS_CNT_x_CMP register. 0x1: VS count error detected
LAG
HS_CNT_0_
HS count comparison error flag. Refer to 0x0: No HS count error detected
CMP_ERR_F 6
HS_CNT_x_CMP register. 0x1: HS count error detected
LAG
DE_CNT_0_
DE count comparison error flag. Refer to 0x0: No DE count error detected
CMP_ERR_F 5
DE_CNT_x_CMP register. 0x1: DE count error detected
LAG
BIT 7 6 5 4 3 2 1 0
VS_CNT_WINDOW_1_M
Field – – – – – –
SB[1:0]
Reset – – – – – – 0x3
Access
– – – – – – Write, Read
Type

VS_CNT_WINDOW_1_ VS counter counts number of frames within window specificed in this register
1:0
MSB in milliseconds. Max window at 1.023s. Default set at 1s.
BIT 7 6 5 4 3 2 1 0
Reset 0xE8
Access
Write, Read
Type

7:0
LSB in milliseconds. Max window at 1.023ms. Default set at 1ms.

BIT 7 6 5 4 3 2 1 0
Reset – – 0x0
Access
– – Write, Read
Type

VS_CNT_1_CMP 5:0
BIT 7 6 5 4 3 2 1 0
Reset – – – – 0x0
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BIT 7 6 5 4 3 2 1 0
Reset – – – – 0x0
Access
Type


BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

VS_CNT_1 (0x1217)
BIT 7 6 5 4 3 2 1 0
Reset – –
Access
– – Read Only
Type

VS_CNT_1 5:0 VS counts within window specified in VS_CNT_WINDOW registers.
BIT 7 6 5 4 3 2 1 0
Reset – – – –
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type


BIT 7 6 5 4 3 2 1 0
Reset – – – –
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type

BIT 7 6 5 4 3 2 1 0
_OEN _OEN _OEN
Reset 0x1 0x1 0x1 – – – – –
Access
Type

VS_CNT_1_
CMP_ERR_ 7
OEN
HS_CNT_1_
CMP_ERR_ 6
OEN
DE_CNT_1_
CMP_ERR_ 5
OEN

BIT 7 6 5 4 3 2 1 0
_FLAG _FLAG _FLAG
Reset 0x0 0x0 0x0 – – – – –
Access
Type

VS_CNT_1_
CMP_ERR_F 7
LAG
HS_CNT_1_
CMP_ERR_F 6
LAG
DE_CNT_1_
CMP_ERR_F 5
LAG
BIT 7 6 5 4 3 2 1 0
VS_CNT_WINDOW_2_M
Field – – – – – –
SB[1:0]
Reset – – – – – – 0x3
Access
– – – – – – Write, Read
Type

1:0
MSB in milliseconds. Max window at 1.023s. Default set at 1s.
BIT 7 6 5 4 3 2 1 0
Reset 0xE8
Access
Write, Read
Type

7:0
LSB milliseconds. Max window at 1.023ms. Default set at 1ms.

BIT 7 6 5 4 3 2 1 0
Reset – – 0x0
Access
– – Write, Read
Type

VS_CNT_2_CMP 5:0
BIT 7 6 5 4 3 2 1 0
Reset – – – – 0x0
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BIT 7 6 5 4 3 2 1 0
Reset – – – – 0x0
Access
Type


BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

VS_CNT_2 (0x1227)
BIT 7 6 5 4 3 2 1 0
Reset – –
Access
– – Read Only
Type

BIT 7 6 5 4 3 2 1 0
Reset – – – –
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type


BIT 7 6 5 4 3 2 1 0
Reset – – – –
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type

BIT 7 6 5 4 3 2 1 0
_OEN _OEN _OEN
Reset 0x1 0x1 0x1 – – – – –
Access
Type

VS_CNT_2_
CMP_ERR_ 7
OEN
HS_CNT_2_
CMP_ERR_ 6
OEN
DE_CNT_2_
CMP_ERR_ 5
OEN

BIT 7 6 5 4 3 2 1 0
_FLAG _FLAG _FLAG
Reset 0x0 0x0 0x0 – – – – –
Access
Type

VS_CNT_2_
CMP_ERR_F 7
LAG
HS_CNT_2_
CMP_ERR_F 6
LAG
DE_CNT_2_
CMP_ERR_F 5
LAG
BIT 7 6 5 4 3 2 1 0
VS_CNT_WINDOW_3_M
Field – – – – – –
SB[1:0]
Reset – – – – – – 0x3
Access
– – – – – – Write, Read
Type

1:0
MSB milliseconds. Max window at 1.023s. Default set at 1ms.
BIT 7 6 5 4 3 2 1 0
Reset 0xE8
Access
Write, Read
Type

7:0
LSB milliseconds. Max window at 1.023ms. Default set at 1s.

BIT 7 6 5 4 3 2 1 0
Reset – – 0x0
Access
– – Write, Read
Type

VS_CNT_3_CMP 5:0
BIT 7 6 5 4 3 2 1 0
Reset – – – – 0x0
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

BIT 7 6 5 4 3 2 1 0
Reset – – – – 0x0
Access
Type


BIT 7 6 5 4 3 2 1 0
Reset 0x0
Access
Write, Read
Type

VS_CNT_3 (0x1237)
BIT 7 6 5 4 3 2 1 0
Reset – –
Access
– – Read Only
Type

BIT 7 6 5 4 3 2 1 0
Reset – – – –
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type


BIT 7 6 5 4 3 2 1 0
Reset – – – –
Access
Type

BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type

BIT 7 6 5 4 3 2 1 0
_OEN _OEN _OEN
Reset 0x1 0x1 0x1 – – – – –
Access
Type

VS_CNT_3_
CMP_ERR_ 7
OEN
HS_CNT_3_
CMP_ERR_ 6
OEN
DE_CNT_3_
CMP_ERR_ 5
OEN

BIT 7 6 5 4 3 2 1 0
_FLAG _FLAG _FLAG
Reset 0x0 0x0 0x0 – – – – –
Access
Type

VS_CNT_3_
CMP_ERR_F 7
LAG
HS_CNT_3_
CMP_ERR_F 6
LAG
DE_CNT_3_
CMP_ERR_F 5
LAG
TUN_MODE_DET (0x1260)
BIT 7 6 5 4 3 2 1 0
CPHY_MO
BACKTOP4 BACKTOP3 BACKTOP2 BACKTOP1
Field DE_OVRD_ – – –
_TUN_DET _TUN_DET _TUN_DET _TUN_DET
EN
Reset 0x0 – – –
Access
Write, Read – – – Read Only Read Only Read Only Read Only
Type

Each backtop use values set in
BACKTOPx_CPHY_MODE_OVRD register
CPHY_MOD instead of detected 0x0: Controller 0
7
E_OVRD_EN (BACKTOPx_CPHY_MODE_DET). 0x1: Controller 1
Used only in Wx4H aggregation in tunneling
mode.
BACKTOP4_ 0x0: Tunnel Mode not detected
3 Detected tunneling mode flag
TUN_DET 0x1: Tunnel Mode detected

TUN_CPHY_DET (0x1261)
BIT 7 6 5 4 3 2 1 0
BACKTOP4 BACKTOP3 BACKTOP2 BACKTOP1 BACKTOP4 BACKTOP3 BACKTOP2 BACKTOP1
Field _CPHY_MO _CPHY_MO _CPHY_MO _CPHY_MO _CPHY_MO _CPHY_MO _CPHY_MO _CPHY_MO
DE_OVRD DE_OVRD DE_OVRD DE_OVRD DE_DET DE_DET DE_DET DE_DET
Access
Write, Read Write, Read Write, Read Write, Read Read Only Read Only Read Only Read Only
Type

Must also set CPHY_MODE_OVRD register
BACKTOP4_ to 1.
0x0: Controller 0
CPHY_MOD 7 BACKTOP4 cphy_mode override value (used
0x1: Controller 1
E_OVRD only in Wx4H aggregation and DPHY-to-
CPHY conversion in tunneling mode).
BACKTOP3_ to 1.
0x0: Controller 0
0x1: Controller 1
BACKTOP2_ to 1.
0x0: Controller 0
0x1: Controller 1
BACKTOP1_ to 1.
0x0: Controller 0
0x1: Controller 1
Detected CPHY mode header/packets from
BACKTOP4_
SER in tunneling mode (used for Wx4H 0x0: CPHY Tunnel Mode not Detected
CPHY_MOD 3
aggregation and setting DPHY-to-CPHY 0x1: CPHY Tunnel Mode Detected
E_DET
conversion mode in tunneling mode)
BACKTOP3_
CPHY_MOD 2
E_DET
BACKTOP2_
CPHY_MOD 1
E_DET
BACKTOP1_
CPHY_MOD 0
E_DET

TUN_CPHY_LANE_DET (0x1262)
BIT 7 6 5 4 3 2 1 0
BACKTOP4_TUN_CPHY_ BACKTOP3_TUN_CPHY_ BACKTOP2_TUN_CPHY_ BACKTOP1_TUN_CPHY_
Field
SER_LANE_DET[1:0] SER_LANE_DET[1:0] SER_LANE_DET[1:0] SER_LANE_DET[1:0]
Reset
Access
Type

BACKTOP4_
TUN_CPHY_ 0x0: 1-lane
7:6 Detected number of CPHY lanes in SER
SER_LANE_ 0x1: 2-lanes
DET
BACKTOP3_
DET
BACKTOP2_
DET
BACKTOP1_
DET
TMD_HEADER_ERR_FLAGS_1 (0x1264)
BIT 7 6 5 4 3 2 1 0
BACKTOP1 BACKTOP1 BACKTOP1
BACKTOP1 BACKTOP1
_TMD_CRC _TMD_CRC _TMD_ECC
Field _TMD_SP_ – – – _TMD_ECC
_2L_ERR_F _1L_ERR_F _ERR_FLA
DET_ERR _FLAG
LAG LAG G
Reset – – –
Access
Read Only – Read Only Read Only – – Read Only Read Only
Type

Detected header error in short-packet detect
state. Short packet header after detected
BACKTOP1_
three consecutive matching headers did not 0x0: No error detected
TMD_SP_DE 7
match in mode (DPHY/CPHY 1-lane/CPHY 0x1: Detected Header Error
T_ERR
2-lane). This error will also reset the
tmd_pkt_cnt in the same backtop.
BACKTOP1_ 2-lane CPHY mode CRC error detected. This
TMD_CRC_2 flag is sticky and will update when header is 0x0: No error detected
5
L_ERR_FLA enabled (i.e. during tunnel mode detection 0x1: Detected Error
G OR Wx4H aggregation)
4


DPHY mode uncorrectable ECC error
BACKTOP1_
detected. This flag is sticky and will update 0x0: No error detected
TMD_ECC_E 1
when header is enabled (i.e. during tunnel 0x1: Detected Error
RR_FLAG
mode detection OR Wx4H aggregation)
DPHY mode ECC error (1-bit correctable)
BACKTOP1_
TMD_ECC_F 0
LAG
BIT 7 6 5 4 3 2 1 0
BACKTOP2 BACKTOP2
DET_ERR _FLAG
LAG LAG G
Reset – – –
Access
Type

BACKTOP2_
3-consecutive matching headers did not 0x0: No error detected
TMD_SP_DE 7
T_ERR
5
4
BACKTOP2_
TMD_ECC_E 1
RR_FLAG
BACKTOP2_
TMD_ECC_F 0
LAG

BIT 7 6 5 4 3 2 1 0
BACKTOP3 BACKTOP3
DET_ERR _FLAG
LAG LAG G
Reset – – –
Access
Type

BACKTOP3_
TMD_SP_DE 7
T_ERR
5
4
BACKTOP3_
TMD_ECC_E 1
RR_FLAG
BACKTOP3_
TMD_ECC_F 0
LAG
BIT 7 6 5 4 3 2 1 0
BACKTOP4 BACKTOP4
DET_ERR _FLAG
LAG LAG G
Reset – – –
Access
Type

BACKTOP4_
TMD_SP_DE 7
T_ERR


5
4
BACKTOP4_
TMD_ECC_E 1
RR_FLAG
BACKTOP4_
TMD_ECC_F 0
LAG
TMD_PKT_CNT_1 (0x126A)
BIT 7 6 5 4 3 2 1 0
Field TMD_PKT_CNT_1[7:0]
Reset
Access
Read Only
Type

TMD_PKT_CNT_1 7:0 Number of packets used to determine tunnel/pixel mode in BACKTOP1
TMD_PKT_CNT_2 (0x126B)
BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type

TMD_PKT_CNT_3 (0x126C)
BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type


TMD_PKT_CNT_4 (0x126D)
BIT 7 6 5 4 3 2 1 0
Reset
Access
Read Only
Type

TMD_PKT_CNT_1_H (0x126E)
BIT 7 6 5 4 3 2 1 0
Field – – – TMD_PKT_CNT_1_H[4:0]
Reset – – –
Access
Type

TMD_PKT_CNT_1_H 4:0 Number of packets used to determine tunnel/pixel mode in BACKTOP1
TMD_PKT_CNT_2_H (0x126F)
BIT 7 6 5 4 3 2 1 0
Reset – – –
Access
Type

TMD_PKT_CNT_3_H (0x1270)
BIT 7 6 5 4 3 2 1 0
Reset – – –
Access
Type


TMD_PKT_CNT_4_H (0x1271)
BIT 7 6 5 4 3 2 1 0
Reset – – –
Access
Type


Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 7/22 Initial Release —
1 7/22 Corrected typos in Table 9. MFP Pin Function Map 41
2 9/22 General description and Simplified Block Diagram updated. 1-2
3 10/22 Removed asterisks from future products in the Ordering Information table. 46
Changed the verbiage in the tunneling and pixel mode sections and
4 1/23 34
adjusted the pictures.
GMSL is a trademark of Maxim Integrated Products, Inc.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of
their respective owners.
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MAX96724/F/R Quad Tunneling GMSL2/1 to CSI-2 Deserializer

General Description Benefits and Features

Ordering Information appears at end of datasheet. 19-101575; Rev 4; 1/23

Simplified Block Diagram

GMSL2 – TUNNEL MODE MIPI CSI-2 v1.3

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TABLE OF CONTENTS (CONTINUED)

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Absolute Maximum Ratings

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Differential Output RL = 100Ω ±1% VDD18 - VDD18 - VDD18 -

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Electrical Characteristics (continued)

VOD Mismatch when

HS Output High Voltage VOHHS 360 mV

Six Possible High-

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

TCLK-PREPARE + Time TCLK-

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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X1/OSC X2 XRES PWDNB CFG[0:1] MFP[0:8]

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Control Channel Programming

Host-to-Peripheral Main I2C and Pass-Through I2C Communication

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I2C Write Packet Format

Figure 1. I2C Write Packet Format

I2C Read Packet Format

Figure 2. I2C Read Packet Format

Advanced GMSL User Documentation

Recommended Operating Conditions

External Component Requirements

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Table 3. External Component Requirements

www.analog.com Analog Devices | 26

GMSL2 Reverse Channel Serial Outputs

VODT = VOD(+) + VOD(-) VOD(+)