PRELIMINARY Specification

Alliance Semiconductor P1708C

Low Power Notebook LCD Panel EMI Reduction IC

FEATURES

• FCC approved method of EMI attenuation • CMOS/TTL compatible inputs and outputs

• Generates a low EMI spread spectrum of the • Ultra low power CMOS design
input clock frequency 8.46 mA @3.3V, 54 MHz
9.79 mA @3.3V, 65 MHz
• Optimized for frequency range from 50MHz 12.06 mA @3.3V, 81MHz
16.51 mA @303V, 108 MHz
to 110MHz operation

• Internal loop filter minimizes external • Supports notebook VGA and other LCD timing
components and board space controller applications

• 4 selectable spread ranges • Pinout compatible to ICS MK1708 and

Cypress CY25560
• Low inherent cycle-to-cycle jitter
• SSON/SBM pin for Spread Spectrum On/Off
and Standby Mode controls
• 3.3V operating voltage
• Available in 8 pin SOIC and TSSOP

PRODUCT DESCRIPTION
The P1708C uses the most efficient and
The P1708C is a versatile spread spectrum optimized modulation profile approved by the FCC
frequency modulator designed specifically for a and is implemented by using a proprietary all-
wide range of clock frequencies. The P1708C digital method.
reduces electromagnetic interference (EMI) at the
clock source, allowing system wide reduction of APPLICATIONS
EMI of down stream (clock and data dependent
signals). The P1708C allows significant system The P1708C is targeted towards notebook LCD
cost savings by reducing the number of circuit displays, other displays using an LVDS interface,
board layers and shielding that are traditionally PC peripheral devices, and embedded systems.
required to pass EMI regulations.

The P1708C modulates the output of a single PLL Figure 1 - P1708C Pin Diagram
in order to “spread” the bandwidth of a
synthesized clock, thereby decreasing the peak
amplitudes of its harmonics. This results in CLKIN 1 8 NC
significantly lower system EMI compared to the
typical narrow band signal produced by oscillators VDD 2 7 SR0
and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called “spread VSS 3 6 SR1
spectrum clock generation”.
ModOUT 4 5 SSON/SBM

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This datasheet has been downloaded from http://www.digchip.com at this page

 PRELIMINARY Specification
Alliance Semiconductor P1708C
Figure 2 - P1708C Block Diagram
VDD
SR0 SR1 SSON

PLL
Modulation

CLKIN Frequency
D ivider
Phase Loop Output
VCO
Detector Filter Divider
Feedback
D ivider

ModOUT

P1708C Block Diagram

VSS

Table 1 - Standby Mode Selection

CLKIN SSON/SBM Spread Spectrum ModOut PLL Mode
Disabled 0 N/A Disabled Disabled Standby
Disabled 1 N/A Disabled Free Running Free Running
Enabled 0 OFF Reference Disabled Buffer Out
Enabled 1 ON Normal Normal Normal

Table 2 - Spread Range Selection

SR1 SR0 Spreading Range Modulation rate
0 0 +/- 1.00% (Fin/40)*62.49 KHz
0 1 +/- 2.00% (Fin/40)*62.49 KHz
1 0 +/- 0.25% (Fin/40)*62.49 KHz
1 1 +/- 0.75% (Fin/40)*62.49 KHz

PIN DESCRIPTION

PIN # Name Type Description

1 CLKIN I Connect to externally generated clock signal. To put the part into
standby mode, disable the input clock signal to this pin and pull
SSON/SBM (Pin 5) low (see
Table 1).
2 VDD P Connect to +3.3V
3 VSS P Ground Connection. Connect to system ground.
4 ModOUT O Spread Spectrum Clock Output.
5 SSON/SB I Spread Spectrum On / Off and Standby Mode control (see
M Table 1). This pin has an internal pull-up resistor.
6 SR1 I Digital logic input used to select Spreading Range (see Table 2). This pin
has an internal pull-up resistor.
7 SR0 I Digital logic input used to select Spreading Range (see Table 2). This pin
has an internal pull-up resistor.
8 NC NC No Connect
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 PRELIMINARY Specification
Alliance Semiconductor P1708C
Figure 3 - P1708C Schematic for Notebook VGA Application

50MHz-110MHz Pixel Clock

Input from VGA Chip Pin 8 can be tied either
high or low. Or it may be
1 CLKIN NC 8 left unconnected.
0.1uF
Tie SR0 and SR1 High/Low
FB 2 VDD SR0 7 according to spread range
VDD desired. See Table 2. External
3 VSS SR1 6 resistors are not needed to pull
these pins high.
4 ModOUT SSON 5 Pin 5 SSON should be be left
P1708C
P2040B unconnected to turn on Spread
Spectrum. Pull this pin low to
turn Spread Spectrum OFF and
50MHz-110MHz EMI
enable Standby Mode (see note).
Reduced Pixel Clock Output

Note: To set the P1708C into Standby Mode, disable the input clock (CLKIN, Pin1) and also pull
SSON/SBM (Pin 5) low (see Table 1).

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 PRELIMINARY Specification
Alliance Semiconductor P1708C
ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Unit

VDD, VIN Voltage on any pin with respect to GND -0.5 to +7.0 V
TSTG Storage Temperature -65 to +125 ºC
TA Operating Temperature 0 to +70 ºC

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit

VIL Input Low Voltage GND – 0.3 - 0.8 V

VIH Input High Voltage 2.0 - VDD + 0.3 V
IIL Input Low Current (100 KΩ input pull-up - - -35 µA
resistor on inputs SR0, 1)
IIH Input High Current (100 KΩ input pull- - - 35 µA
down resistor on input SSON)
IXOL XOUT Output Low Current - 3 - mA
(@ 0.4V, VDD = 3.3V)
IXOH XOUT Output High Current - 3 - mA
(@ 2.5V, VDD = 3.3V)
VOL Output Low Voltage - - 0.4 V
(VDD=3.3V, IOL = 20 mA)
VOH Output High Voltage 2.5 - - V
(VDD=3.3V, IOH = 20 mA)
IDD Static Supply Current - 0.6 - mA
Standby Mode
ICC Dynamic Supply Current 7.90 9.79 17.53 mA
Normal Mode (3.3V and 10 pF loading) f IN-min f IN-typ f IN-max
VDD Operating Voltage 2.7 3.3 3.7 V
tON Power Up Time - 0.18 - mS
(First locked clock cycle after power up)
ZOUT Clock Output Impedance - 50 - Ω

AC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit

f IN Input Frequency 50 65 110 MHz

tLH Output Rise Time 0.7 0.9 1.1 ns
Note 1 (measured at 0.8V to 2.0V)
tHL Output Fall Time 0.6 0.8 1.0 ns
Note 1 (measured at 2.0V to 0.8V)
tJC Jitter (cycle to cycle) - - 360 ps
tD Output Duty Cycle 45 50 55 %
Note1: tLH and tHL are measured into a capacitive load of 15pF

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 PRELIMINARY Specification
Alliance Semiconductor P1708C
Figure 4 - Mechanical Package Outline (8 Pin SOIC)

L
INCHES MILLIMETERS
SYMBOL MIN NOR MAX MIN NOR MAX
P1708C A 0.057 0.064 0.071 1.45 1.63 1.80
LOT NUMBER H E
YYWW
A1 0.004 0.007 0.010 0.10 0.18 0.25
A2 0.053 0.061 0.069 1.35 1.55 1.75
B 0.012 0.016 0.020 0.31 0.41 0.51
C 0.004 0.006 0.001 0.10 0.15 0.25
a
D 0.186 0.194 0.202 4.72 4.92 5.12
D
E 0.148 0.156 0.164 3.75 3.95 4.15
e 0.050 BSC 1.27 BSC
H 0.224 0.236 0.248 5.70 6.00 6.30
A2 A L 0.012 0.020 0.028 0.30 0.50 0.70
a 0° 5° 8° 0° 5° 8°
B e A1
Note: Controlling dimensions are millimeters.

Figure 5 - Mechanical Package Outline (8 Pin TSSOP)

C
INCHES MILLIMETERS
SYMBOL MIN NOR MAX MIN NOR MAX
L
A - - 0.047 - - 1.10
A1 0.002 - 0.006 0.05 - 0.15
YYWW
1708C

Lot #

A2 0.031 0.039 0.041 0.80 1.00 1.05

P

H
E
B 0.007 - 0.012 0.19 - 0.30
C 0.004 - 0.008 0.09 - 0.20
D 0.114 0.118 0.122 2.90 3.00 3.10
E 0.169 0.173 0.177 4.30 4.40 4.50
a
e 0.026 BSC 0.65 BSC
D
H 0.244 0.252 0.260 6.20 6.40 6.60
L 0.018 0.024 0.030 0.45 0.60 0.75
A2 A a 0° - 8° 0° - 8°
Note: Controlling dimensions are millimeters.
B e A1

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Revision C 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
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 PRELIMINARY Specification
Alliance Semiconductor P1708C
ORDERING INFORMATION

Ordering Number Marking Package Type Qty. / Reel Temperature

P1708C-08ST P1708C 8 PIN SOIC, TUBE 0°C TO 70°C
P1708C-08SR P1708C 8 PIN SOIC, TAPE & REEL 2,500 0°C TO 70°C
P1708C-08TT P1708C 8 PIN TSSOP, TUBE 0°C TO 70°C
P1708C-08TR P1708C 8 PIN TSSOP, TAPE & REEL 2,500 0°C TO 70°C

"Licensed under U.S. Patent Nos. 5,488,627 and 5,631,920"

May, 2002 PulseCore, a Division of Alliance Semiconductor

Revision C 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
6 of 6 http://www.pulsecore.com; http://www.alsc.com