PCIe Equalization

PCIE EQUALIZATION
At the time of its introduction in 2003, the PCIe serial bus standard was meant to replace
these older parallel buses to enable a higher data rate and to simplify system design. In 2003, the
PCIe standard was defined by the PCI-SIG organization. Since then, the PCIe standard has
iteratively improved over time to accommodate the latest bandwidth needs of modern computers.
In 2021, the PCIe 6.0 specification was introduced, enabling 64 GT/s, or 64 Gbps per link. One
unique feature of the PCIe standard is the ability to increase the number of lanes from 1 to 32
lanes to increase its throughput, a feature inspired by its parallel bus predecessor. A PCIe 6.0 link
that is 16 lanes wide would have a data rate of 128 GB/s, which is extremely fast by today's
standards.
Figure: Timeline of PCIe Interface
But with increased signal transmission rates comes an increased risk for signal loss
during transmission. Factors such as channel quality and transmission rate can contribute to
interference that distort the receiver's ability to capture signals accurately. Beyond a certain
threshold, signal distortion can result in high error rates that ultimately impact communication
performance. To make up for this inevitable distortion, signal compensation is applied at both the
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transmitter and receiver ends. This compensation process is known as PCIe link equalization and
aims to strengthen incoming PCIe signals that will in turn build clear signal eye diagrams.
As the data rates get higher, the Unit Interval time becomes smaller, with the result that
it’s increasingly difficult to avoid having the value in one bit time affect the value in another bit
time. The channel always resists to the changes in voltage level. In PCIe Gen1 and Gen2
adopting 8b/10b encoding and fixed de-emphasis equalization at the transmitter was enough to
ensure the quality of low signal throughput, eliminating the need for PCIe equalization parameter
negotiation. As a result, PCIe equalization processes were more straightforward and standardized
in the early days.
De-Emphasis -
De-emphasis is technique where it reduces the voltage for the repeated bits in a bit
stream. Below diagram shows the De-emphasis for the bit stream “100001000” transmitted.
• PCIe 1.0: De-emphasis value fixed at -3.5dB.
• PCIe 2.0: De-emphasis value fixed at -3.5dB and -6dB, without dynamic adjustment.
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Pre-emphasis -
In high-speed PCIe serial communication signals, signal distortion occurs due to greater
attenuation of high-frequency components compared to low-frequency components, especially at
the signal's rise and fall edges. Pre-emphasis compensates for the attenuation of high-frequency
components by increasing the signal amplitude at the transition edges, effectively boosting the
high-frequency components.
From PCIe Gen 3.0 onwards PCIe uses the handshake mechanism to do the Equalization.
PCIe spec defines the LTSSM state Recovery Equalization state during which the Receiver
instructs the Link partner’s transmitter to adjust the voltage levels by updating its co-efficient
values.
Figure: Recovery Substate (LTSSM) Machine

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For Gen 3 and Gen 4, there are 11 presets numbered from 0 to 10 that may be used, each with
its own unique signal characteristics. The preset values for each port are negotiated through link
equalization until the ideal preset is chosen via phases 0, 1, 2, and 3 for all link equalization
processes.
Phase 0: This is the first stage of link equalization. The Down Stream Port (Root port) sends
the required transmission endpoint preset values to the Up Stream Port (Endpoint) for each lane,
which are conveyed through Training Sequence 2 (TS2). Upon receiving the request from the
DSP, the USP increases the data transmission rate of the link to Gen3 (8 GT/s) and sends back a
Training Sequence 1 (TS1) containing the received preset values. Once the Gen3 connection is
established, the link equalization enters Phase 1.
Phase 1: The same TS1 is repeated regardless of link quality to ensure that DSP receives the
correct preset values. This is done to prime the link for the exchange of TS1 and the subsequent
stages of link fine-tuning. Once the link achieves a Bit Error Rate (BER) of ≤10e-4, the link
equalization enters Phase 2.
Phase 2: The DSP adjusts the USP's preset values by sending equalization requests through
TS1 until the optimal settings are obtained, with the link's BER meeting the requirement of ≤1E-
12.
Phase 3: The USP adjusts the DSP's preset values by sending equalization requests through
TS1 until the optimal setting link's BER ≤1E-12 is met. The conclusion of Phase 3 also
concludes the link equalization process.
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Figure: Link Equalization preset values and Signals
Conclusion:
PCIe devices go through the link training process to establish connection among the root
complex and the PCIe endpoints. This allows PCIe devices to send and receive data at PCIe Gen
1 data rate. If all connected PCIe devices are higher than Gen 3, PCIe devices will conduct link
equalization processes to establish PCIe link at faster rates. Link equalization goes through initial
tuning and fine tuning to allow bit error rate of less than 10-12 and send or receive data at the
fastest rate it can stably support.
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PCIe Equalization

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PCIE EQUALIZATION

Figure: Timeline of PCIe Interface

• PCIe 1.0: De-emphasis value fixed at -3.5dB.

Figure: Recovery Substate (LTSSM) Machine

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