REVIEW ON LOW POWER VLSI DESIGN

Mr. Hitesh V. Chopade Ms. Anshu N. Adwani Prof. Swapnil S. Jain

M. Tech (ECE), DMIETR M. Tech (ECE), DMIETR Asst. Prof. Dept. of E & TC,
Wardha, Maharashtra, India Wardha, Maharashtra, India DMIETR, Wardha, Maharashtra,
Email:hiteshchopade@outlook.com Email: anshuadwani@gmail.com India
Email: swapniljain73@rediffmail.com

ABSTRACT device must be addressed. Lowering the total power

consumption in these systems is important since it is desirable
Low power requirement has become a principal motto in
to maximize the run time with minimum requirements on size,
today’s world of electronics industries. Power dissipation has
battery support and required weight of batteries. So the most
becoming an important consideration as performance and area
useful factor to consider while designing SOC for portable
for VLSI Chip design. With reducing the chip size, reduced
devices is 'low power design'.[1]
power consumption and power management on chip are the
key challenges due to increased complexity. Low power chip
requirement in the VLSI industry is main considerable field Problem associated with power dissipation
due to the reduction of chip dimension day by day and Scaling of technology node increases power-density more
environmental factors. For many designs, optimization of than expected. CMOS technology beyond 65nm node arises a
power is important as timing due to the need to reduce real challenge for any sort of voltage and frequency scaling
package cost and extended battery life. This paper present Starting from 120nm node, each new process has obvious
various techniques to reduce the power requirement in various higher dynamic and leakage current density with minimum
stages of CMOS designing i.e. Dynamic Power Suppression, increase in speed. Between 90nm to 65nm the dynamic power
Adiabatic Circuits, Logic Design for Low Power, Reducing dissipation is almost same whereas there is ~5% higher
Glitches, Logic Level Power Optimization, Standby Mode leakage/mm2 [3].Low cost always require higher levels of
Leakage Suppression, Variable Body Biasing, Sleep integration, whereas less costly technological breakthroughs to
Transistors, Dynamic Threshold MOS, Short Circuit Power keep power under control are getting very scarce.
Suppression.
Keywords-Low power, VLSI, CMOS, package cost, battery Do we need to bother with power?
life, power dissipation. Power dissipation is the main look up when it comes
to Portability. The mobile device consumer keeps demanding
1) INTRODUCTION
more features and extended battery life at a lower cost. About
In modern era VLSI design efforts have focused primarily 70% of users require longer talk-time and maximum stand-by
on increasing the speed to realize computationally intensive time as primary mobile phone feature. For 3G technology we
functions such as video compression, gaming &graphics etc. require more power efficiency, consumer also needs smaller
So, we have semiconductor ICs that successfully integrated size gadgets. It requires high levels of Silicon integration in
various complex signal processing modules & graphical advanced processes, where as advanced processes have
processing units to meet our requirement. While these inherently higher leakage current. So we must need to
solutions have addressed the real-time problem, they haven’t consider leakage current while designing low power gadgets.
addressed the demand for portable high speed operation,
where mobile phone needs to design with all this without [4]
consuming much power. The strict limitation on total power Why power matters in soc?
dissipation in portable electronics applications like smart Power Management useful in System on Chip because of
phones and tablet computers must be met by the VLSI chip following concerns:
designer while still meeting the computational requirements. 1. Packaging & Cooling costs.
But wireless devices are rapidly making their importance to 2. Digital noise immunity,
the consumer electronics market; a key design component for 3. Battery life of portable systems
portable operation namely the total power consumption of the 4. Environmental issues.

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 dissipation. However the static power or leakage power is
2) SOURCES OF POWER DISSIPATION same as or exceeds the dynamic power below 65nanometer
The power dissipation in circuit is classified into three technology node.
classes as described below. So themethods to reduce power dissipation is not
1. Dynamic power consumption: Because of logic limited to dynamic power. In this paper we approaches to
transitions causing logic gates to charge/discharge load minimize Dynamic, Leakage power dissipation and Short
capacitance. Circuit power dissipation. Power minimization in a processor
2. Short-circuit current: In a CMOS logic P-branch and N- can be achieved at various levels of designing. So we need to
branch are momentarily shorted as logic gate changes optimize or reduce the power requirement of desired
state for short circuit power dissipation. circuitry[3].
3. Leakage current: It occurs when the system is in standby Total Power dissipated in a CMOS circuit is equal to
mode or not powered. There are various sources of total of dynamic power, short circuit power and static power
leakage current in MOSFET[7]. Diode leakages around or leakage power. Designed structure for low-power
transistors &n-wells, Sub-threshold Leakage, Gate requirement implies the ability to reduce all three parameters
Leakage, Tunnel Currents etc. Increasing 20 times for of power consumption in CMOS circuits during the designing
each new fabrication technology. of a low power electronic product.

3) LOW-POWER DESIGN TECHNIQUES

An integrated low power methods requires optimization at all
design abstraction layers as below:
1. System: Partitioning, Power lowering.
2. Algorithm: Complexity in design, Concurrency of
operation, Regularity in working.
3. Architecture: Parallelism of operations, Pipelining of
processes, Redundancy of data, Data Encoding &
decoding.
4. Circuit Logic: Logic design Styles, Energy Recovery Figure 1.Components of Power in CMOS circuit P total =
methods, component sizing. CLVDD2 + tscVDDIpeak + VDDIleakage
5. Technology: Threshold Reduction capability, Multi
Threshold Devices. 5.1. Dynamic power suppression
Dynamic power varies as VDD2. So lowering the Dynamic/Switching power is due to charging and
supply voltage reduces power dissipation. The selective discharging of load capacitors driven by the circuit. Supply
frequency reduction technique used to lower the dynamic voltage variation has been the most preferred approach to
power requirement[4]. At system level, multi threshold voltage power optimization, since it normally result in considerable
can be used to reduce leakage power. For speed-up circuit and power savings due to the quadratic dependence of
reduce power transistor resizing can be used. Sleep transistors switching/dynamic power PSwitching on supply voltage VDD.
can be used efficiently to reduce standby power. Parallel However limiting the supply voltage affects circuit speed
processing and pipelining can reduce power requirement. which is the major short-coming of this method. So design and
Clock disabling, power-down of selected logic blocks, technological solutions must be applied to compensate the
adiabatic computing, software redesign to lower power decrease in circuit performance introduced by reduced
dissipation are the other techniques commonly used for low voltage. Some of the methodology often used to reduce
power design. dynamic power are described below.

5.2. Adiabatic circuits

4) VLSI CIRCUIT DESIGN FOR LOW POWER In adiabatic circuits instead of dissipating the power
The growing market of portable gadgets (cellular is reused. By externally limiting the length and shape of signal
phones, gaming remotes) battery-powered electronic systems transitions energy spent to flip a bit can be reduced to very
require microelectronic circuits design havingultra-low power small values. As the diodes have thermodynamic irreversible
dissipation. As the integration, size, and complexity of the nature they are not used in the design of Adiabatic Logic.
chips continue to increase, the difficulty in providing MOSFETs should not be switched ON when there is
sufficient cooling might either add significant cost or limit the significant potential difference between source and drain. And
functionality of the computing systems which make use of shouldn’t be TURNOFF when there is a significant current
those integrated circuits. The technology node scales down to flowing through gadget.
65nm there is not much increase in dynamic power

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 and hence Z switches towards 1 for small time before
switching back to 0 resulting in unnecessary power
dissipation.

Figure.5. Glitch Free AND Gate

Figure 2.Charge Recovery Logic
5.5. Logic level power optimization
5.3. Logic design for low power During logical design implementation for low power,
Selection between static & dynamic topologies, technology parameters like supply voltage are of fixed value,
conventional CMOS &pass-transistor logic styles and and availability for selecting the functionality and sizing the
synchronous & asynchronous timing styles has to be made gates. Equalizing the path & insertion of buffer is one of the
while designing a circuit. In static CMOS circuits, about 10% techniques which make sure that signal propagation from
of total power consumption is due to short circuit current. inputs to outputs of a logic network follows paths of similar
However, in dynamic circuits there is small amount of power length to overcome glitches. When paths are equalized, there
dissipation to reduce the sharing, as there is no direct dc path is equal delay for each branch which result in less delay while
between GND & power supply.[6] feeding signal to next node.

Figure 6. Logic Remapping of design for Low Power [4]

5.6. Standby mode leakage suppression

Figure 3 (a) Static NOR circuit Figure 3(b) Dynamic NOR
Static power & Leakage powergenerated from
circuits
substrate currents and sub-threshold leakages. For
technologies 1 µm and above, PSwitching was more dominant.
We also use pass transistor logic to exploit reduced But for deep-submicron processes below 180nm, P Leakage
swing to lower power. becomes dominant parameter. Leakage power is a major issue
in recent technologies, as it impacts battery lifecycle & battery
life. CMOS technology has been most power-efficient when
transistors are not switching or in stand-by mode, and system
manufacturer expect low leakage from CMOS IC chips. To
meet leakage power parameters, multiple-threshold and
variable threshold circuit techniques are frequently used. In
multiple-threshold CMOS, the process provides two different
threshold transistors. Low-threshold is employed on speed-
critical sub-circuits and there are fast and leaky. High-
Figure 4. Pass Transistor Logic, P = CL* Vdd* (Vdd-Vt) threshold transistors are of low speed but exhibit low sub-
threshold leakage, and they are results in noncritical or slow
5.4. Reducing glitches paths of the chip.
Glitches generates in a logic chain when two parallel
driving common gate approaches at different times. The 5.7. Variable body biasing
output instantly switches to incorrect value before settling to Threshold voltage of transistors can be dynamically
correct value. Consider circuit shown below. consider that in control by variable-threshold through substrate biasing and
the absence of buffer path A is high speed and Path B is slow. hence overcome shortcoming associated with multi-threshold
At beginning if A=0 and B=1 then Z=0.Next if B switched to design. When a variable-threshold circuit is on standby mode,
0 and A to 1 as B is slow the data 0 arriving at B will be slow the substrate of NMOS transistors is negatively biased, and

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their threshold increases due to effect of body-biasingt. Also only preferred for ultralow voltage (0.6V and below) circuits
the substrate of PMOS transistors is biased by positive body in bulk CMOS.
bias to increase their Vt in stand-by mode.[5] Variable-
threshold require control circuits that modulate substrate
voltage in stand-by mode. When the circuit is in standby mode
the bulk/body of both PMOS and NMOS are biased by third
supply voltage to increase the Vt of the MOSFET as shown in
the Figure. But in normal operation they are switched back to
reduce the Vt.

Figure 9 DTMOS Circuit

5.10. Short circuit power suppression

Short circuit currents that comes into consideration
when pairs of PMOS/NMOS transistors are conducting
simultaneously resulting in Short circuit power.

Figure 7. Variable Body Biasing

5.8. Sleep transistors

When High Vt transistors connected in series with low Vtlogic
as shown below are termed as Sleep Transistor.When Low Vt Figure 10 Short Circuit Power in CMOS Circuits
devices are ON the sleep transistors are also ON resulting in
One way to reduce short circuit power is to keep the
normal operation of the circuit. When the circuit is in Standby
input and output rise/fall times the same. If the load
mode, HighVttransistors are OFF. As High Vt devices are in
capacitance is greater, so the output fall time is larger than the
series with Low Vt circuit the leakage current is calculated by
input rise time. The drain-source voltage of the PMOS
High Vt devices and is less, thus reduced the power
transistor is 0. So the short-circuit power is 0. If the load
dissipation.
capacitance is of less capacitance, the output fall time is less
than the input rise time. For PMOS transistor the drain-source
voltage is nearer to VDD during most of the transition period.
Therefore we obtain large short circuit current.

CONCLUSION
The need for lower power systems is being driven by
many market segments. Unfortunately designing for low
power adds another dimension to the already complex design
problem and the design has to be optimized for power as well
Figure 8. Sleep Transistors Circuit Design as Performance and Area.

REFERENCES
5.9. Dynamic threshold MOS
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