AD

S78 ADS7822
22
      AD
S7822

SBAS062C – JANUARY 1996 – REVISED AUGUST 2007

12-Bit, 200kHz, microPower Sampling

ANALOG-TO-DIGITAL CONVERTER

1FEATURES
• 200kHz Sampling Rate
2
DESCRIPTION
• microPower: The ADS7822 is a 12-bit sampling analog-to-digital
1.6mW at 200kHz (A/D) converter with ensured specifications over a
0.54mW at 75kHz 2.7V to 5.25V supply range. It requires very little
0.06mW at 7.5kHz power even when operating at the full 200kHz rate. At
lower conversion rates, the high speed of the device
• Power Down: 3μA max enables it to spend most of its time in the
• Mini-DIP-8, SO-8, and MSOP-8 Packages power-down mode—the power dissipation is less
• Pseudo-Differential Input than 60μW at 7.5kHz.
• Serial Interface The ADS7822 also features operation from 2.0V to
5V, a synchronous serial interface, and a
APPLICATIONS pseudo-differential input. The reference voltage can
• Battery-Operated Systems be set to any level within the range of 50mV to VCC.
• Remote Data Acquisition Ultra low power and small size make the ADS7822
• Isolated Data Acquisition ideal for battery-operated systems. It is also a perfect
fit for remote data-acquisition modules, simultaneous
• Simultaneous Sampling, Multichannel Systems
multichannel systems, and isolated data acquisition.
The ADS7822 is available in a plastic mini-DIP-8, an
SO-8, or an MSOP-8 package.

SAR Control

VREF

DOUT
+In
CDAC Serial
-In Interface DCLOCK
CS/SHDN
S/H Amp Comparator

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas Copyright © 1996–2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

MAXIMUM MAXIMUM
INTEGRAL DIFFERENTIAL SPECIFIED TRANSPORT
PACKAGE- PACKAGE PACKAGE ORDERING
PRODUCT LINEARITY LINEARITY TEMPERATURE MEDIA,
LEAD DESIGNATOR MARKING (2) NUMBER
ERROR ERROR RANGE QUANTITY
(LSB) (LSB)
Tape and Reel,
ADS7822E/250
250
ADS7822E ±2 ±2 MSOP-8 DGK –40°C to +85°C A22
Tape and Reel,
ADS7822E/2K5
2500
Tape and Reel,
ADS7822EB/250
250
ADS7822EB ±1 ±1 MSOP-8 DGK –40°C to +85°C A22
Tape and Reel,
ADS7822EB/2K5
2500
Tape and Reel,
ADS7822EC/250
250
ADS7822EC ±0.75 ±0.75 MSOP-8 DGK –40°C to +85°C A22
Tape and Reel,
ADS7822EC/2K5
2500
Plastic
ADS7822P ±2 ±2 P –40°C to +85°C ADS7822P ADS7822P Rails, 50
DIP-8
Plastic
ADS7822PB ±1 ±1 P –40°C to +85°C ADS7822PB ADS7822PB Rails, 50
DIP-8
Plastic
ADS7822PC ±0.75 ±0.75 P –40°C to +85°C ADS7822PC ADS7822PC Rails, 50
DIP-8
ADS7822U Rails, 100
ADS7822U ±2 ±2 SO-8 D –40°C to +85°C ADS7822U Tape and Reel,
ADS7822U/2K5
2500
ADS7822UB Rails, 100
ADS7822UB ±1 ±1 SO-8 D –40°C to +85°C ADS7822UB Tape and Reel,
ADS7822UB/2K5
2500
ADS7822UC Rails, 100
ADS7822UC ±0.75 ±0.75 SO-8 D –40°C to +85°C ADS7822UC Tape and Reel,
ADS7822UC/2K5
2500

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI website at www.ti.com.
(2) Performance grade information is marked on the reel.

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
ADS7822 UNIT
VCC +6 V
Analog input –0.3 to VCC + 0.3 V
Logic input –0.3 to 6 V
Case temperature +100 °C
Junction temperature +150 °C
Storage temperature +125 °C
External reference voltage +5.5 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

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ELECTRICAL CHARACTERISTICS: +VCC = +2.7V

At –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, and fCLK = 16 × fSAMPLE, unless otherwise noted.
ADS7822 ADS7822B ADS7822C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
ANALOG INPUT
Full-scale input span +In – (–In) 0 VREF 0 VREF 0 VREF V
+In – GND –0.2 VCC + 0.2 –0.2 VCC + 0.2 –0.2 VCC + 0.2 V
Absolute input range
–In – GND –0.2 +1.0 –0.2 +1.0 –0.2 +1.0 V
Capacitance 25 25 25 pF
Leakage current ±1 ±1 ±1 μA
SYSTEM PERFORMANCE
Resolution 12 12 12 Bits
No missing codes 11 12 11 Bits
Integral linearity error –2 ±0.5 +2 –1 ±0.5 +1 –0.75 ±0.25 +0.75 LSB (1)
Differential linearity error –2 ±0.5 +2 –1 ±0.5 +1 –0.75 ±0.25 +0.75 LSB
Offset error –3 +3 –3 +3 –1 +1 LSB
Gain error –3 +3 –3 +3 –1 +1 LSB
Noise 33 33 33 μVrms
Power-supply rejection 82 82 82 dB
SAMPLING DYNAMICS
Conversion time 12 12 12 Clk Cycles
Acquisition time 1.5 1.5 1.5 Clk Cycles
Throughput rate 75 75 75 kHz
DYNAMIC CHARACTERISTICS
Total harmonic distortion VIN = 2.5VPP at 1kHz –82 –82 –82 dB
SINAD VIN = 2.5VPP at 1kHz 71 71 71 dB
Spurious-free dynamic range VIN = 2.5VPP at 1kHz 86 86 86 dB
REFERENCE OUTPUT
Voltage range 0.05 VCC 0.05 VCC 0.05 VCC V
CS = GND, fSAMPLE = 0Hz 5 5 5 GΩ
Resistance
CS = VCC 5 5 5 GΩ
At code 710h 8 40 8 40 8 40 μA
Current drain fSAMPLE = 7.5kHz 0.8 0.8 0.8 μA
CS = VCC 0.001 3 0.001 3 0.001 3 μA
DIGITAL INPUT/OUTPUT
Logic family CMOS CMOS CMOS
VIH IIH = +5μA 2.0 5.5 2.0 5.5 2.0 5.5 V
VIL IIL = +5μA –0.3 0.8 –0.3 0.8 –0.3 0.8 V
Logic levels
VOH IOH = –250μA 2.1 2.1 2.1 V
VOL IOL = 250μA 0.4 0.4 0.4 V
Data format Straight Binary Straight Binary Straight Binary
POWER-SUPPLY REQUIREMENTS
Specified performance 2.7 3.6 2.7 3.6 2.7 3.6 V
(2) (3)
VCC See Notes and 2.0 2.7 2.0 2.7 2.0 2.7 V
(3)
See Note 2.7 3.6 2.7 3.6 2.7 3.6 V
fSAMPLE = 7.5kHz (4) (5) 20 20 20 μA
Quienscent current
fSAMPLE = 75kHz (5) 200 325 200 325 200 325 μA
Power down CS = VCC 3 3 3 μA
TEMPERATURE RANGE
Specified performance –40 +85 –40 +85 –40 +85 °C

(1) LSB means least significant bit. With VREF equal to +2.5V, one LSB is 0.61mV.
(2) The maximum clock rate of the ADS7822 is less than 1.2MHz in this power-supply range.
(3) See the Typical Characteristics for more information.
(4) fCLK = 1.2MHz, CS = VCC for 145 clock cycles out of every 160.
(5) See the Power Dissipation section for more information regarding lower sample rates.

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ELECTRICAL CHARACTERISTICS: +VCC = +5V

At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 × fSAMPLE, unless otherwise noted.
ADS7822 ADS7822B
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
ANALOG INPUT
Full-scale input span +In – (–In) 0 VREF 0 VREF V
+In – GND –0.2 VCC + 0.2 –0.2 VCC + 0.2 V
Absolute input range
–In – GND –0.2 +1.0 –0.2 +1.0 V
Capacitance 25 25 pF
Leakage current ±1 ±1 μA
SYSTEM PERFORMANCE
Resolution 12 12 Bits
No missing codes 11 12 Bits
Integral linearity error –2 +2 –1 +1 LSB (1)
Differential linearity error ±0.8 –1 ±0.5 +1 LSB
Offset error –3 +3 –3 +3 LSB
Gain error –4 +4 –3 +3 LSB
Noise 33 33 μVrms
Power-supply rejection 70 70 dB
SAMPLING DYNAMICS
Conversion time 12 12 Clk Cycles
Acquisition time 1.5 1.5 Clk Cycles
Throughput rate 200 200 kHz
DYNAMIC CHARACTERISTICS
Total harmonic distortion VIN = 5VPP at 10kHz –78 –78 dB
SINAD VIN = 5VPP at 10kHz 71 71 dB
Spurious-free dynamic range VIN = 5VPP at 10kHz 79 79 dB
REFERENCE OUTPUT
Voltage range 0.05 VCC 0.05 VCC V
CS = GND, fSAMPLE = 0Hz 5 5 GΩ
Resistance
CS = VCC 5 5 GΩ
At code 710h 40 100 40 100 μA
Current drain fSAMPLE = 12.5kHz 2.5 2.5 μA
CS = VCC 0.001 3 0.001 3 μA
DIGITAL INPUT/OUTPUT
Logic family CMOS CMOS
VIH IIH = +5μA 3.0 5.5 3.0 5.5 V
VIL IIL = +5μA –0.3 0.8 –0.3 0.8 V
Logic levels
VOH IOH = –250μA 3.5 3.5 V
VOL IOL = 250μA 0.4 0.4 V
Data format Straight Binary Straight Binary
POWER-SUPPLY REQUIREMENTS
VCC Specified performance 4.75 5.25 4.75 5.25 V
Quienscent current fSAMPLE = 200kHz 320 550 320 550 μA
Power down CS = VCC 3 3 μA
TEMPERATURE RANGE
Specified performance –40 +85 –40 +85 °C

(1) LSB means least significant bit. With VREF equal to +5V, one LSB is 1.22mV.

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PIN CONFIGURATION
D, DGK, OR P PACKAGE
SO, MSOP, or DIP
(TOP VIEW)

VREF 1 8 +VCC

+In 2 7 DCLOCK
ADS7822
-In 3 6 DOUT

GND 4 5 CS/SHDN

PIN ASSIGNMENTS
PIN
DESCRIPTION
NAME NO.
VREF 1 Reference input
+In 2 Noninverting input
–In 3 Inverting input. Connect to ground or to remote ground sense point.
GND 4 Ground
CS/SHDN 5 Chip select when low; Shutdown mode when high.
The serial output data word is comprised of 12 bits of data. In operation, the data are valid on the falling edge of DCLOCK. The
DOUT 6
second clock pulse after the falling edge of CS enables the serial output. After one null bit, the data are valid for the next edges.
DCLOCK 7 Data clock synchronizes the serial data transfer and determines conversion speed.
+VCC 8 Power supply

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TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 × fSAMPLE, unless otherwise specified.

INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs CODE vs CODE
1.00 1.00

0.75 0.75

Differential Linearity Error (LSB)

Integral Linearity Error (LSB)

0.50 0.50

0.25 0.25

0.00 0.00

-0.25 -0.25

-0.50 -0.50

-0.75 -0.75

-1.00 -1.00
0 2048 4095 0 2048 4095
Code Code
Figure 1. Figure 2.

SUPPLY CURRENT POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE vs TEMPERATURE
350 120

300 100
Supply Current (nA)
Supply Current (mA)

250 80

200 60

150 40

100 20

50 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
Figure 3. Figure 4.

QUIESCENT CURRENT MAXIMUM SAMPLE RATE

vs VCC vs VCC
400 1000

350
Quiescent Current (mA)

Sample Rate (kHz)

300 100

250

200 10

150

100 1
1 2 3 4 5 1 2 3 4 5
VCC (V) VCC (V)
Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 × fSAMPLE, unless otherwise specified.

CHANGE IN OFFSET CHANGE IN OFFSET

vs REFERENCE VOLTAGE vs TEMPERATURE
1.2 0.6
1.0 VCC = 5V
0.4
0.8
Change in Offset (LSB)

Delta from 25°C (LSB)

0.6
0.2
0.4
0.2 0
0.0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.8 -0.6
1 2 3 4 5 -50 -25 0 25 50 75 100
Reference Voltage (V) Temperature (°C)
Figure 7. Figure 8.

CHANGE IN GAIN CHANGE IN GAIN

vs REFERENCE VOLTAGE vs TEMPERATURE
2.5 0.15

2.0 V
VCC = 5V
CC = 5V
0.10
1.5
Delta from 25°C (LSB)
Change in Gain (LSB)

0.05
1.0

0.5 0

0.0
-0.05
-0.5
-0.10
-1.0

-1.5 -0.15
1 2 3 4 5 -50 -25 0 25 50 75 100
Reference Voltage (V) Temperature (°C)
Figure 9. Figure 10.

EFFECTIVE NUMBER OF BITS PEAK-TO-PEAK NOISE

vs REFERENCE VOLTAGE vs REFERENCE VOLTAGE
12.00 10
VCC = 5V VCC = 5V
11.75 9
Effective Number of Bits (rms)

8
Peak-to-Peak Noise (LSB)

11.50
7
11.25 6
11.00 5

10.75 4
3
10.50
2
10.25
1
10.00 0
0.1 1 10 0.1 1 10
Reference Voltage (V) Reference Voltage (V)
Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 × fSAMPLE, unless otherwise specified.

SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION

SIGNAL-TO-NOISE RATIO vs FREQUENCY vs FREQUENCY
100 0
90 Spurious Free Dynamic Range -10

Total Harmonic Distortion (dB)

80 -20
SFDR and SNR (dB)

70 -30
60 -40
Signal-to-Noise Ratio
50 -50
40 -60
30 -70
20 -80
10 -90
0 -100
1 10 100 1 10 100
Frequency (kHz) Frequency (kHz)
Figure 13. Figure 14.

SIGNAL-TO-(NOISE+DISTORTION) SIGNAL-TO-(NOISE+DISTORTION)
vs FREQUENCY vs INPUT LEVEL
100 80
Signal-to-(Noise Ratio + Distortion) (dB)

90
Signal-to-(Noise + Distortion) (dB)

70
80
60
70
60 50

50 40
40 30
30
20
20
10 10

0 0
1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0
Frequency (kHz) Input Level (dB)
Figure 15. Figure 16.

REFERENCE CURRENT REFERENCE CURRENT vs TEMPERATURE

vs SAMPLE RATE (Code = 710h)
14 14

12 12
Reference Current (mA)

Reference Current (A)

10
10
8
8
6
6
4

2 4

0 2
0 15 30 45 60 75 -50 -25 0 25 50 75 100
Sample Rate (kHz) Temperature (°C)
Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 × fSAMPLE, unless otherwise specified.

POWER-SUPPLY REJECTION POWER-SUPPLY REJECTION

vs RIPPLE FREQUENCY vs RIPPLE FREQUENCY
0 0
VCC = 2.7V VCC = 5V
-10 Ripple = 500mVPP -10 Ripple = 500mVPP
VIN = 1.25VDC VIN = 2.5VDC
-20 -20
VREF = 2.5V VREF = 5V
-30 -30

PSR (dB)
PSR (dB)

-40 -40

-50 -50

-60 -60

-70 -70

-80 PSR (dB) = 20log(500mV/DVO) -80 PSR (dB) = 20log(500mV/DVO)

where DVO = change in digital result where DVO = change in digital result
-90 -90
1k 10k 100k 1M 10M 10 1 1k 10k 100k 1M 10M
Ripple Frequency (Hz) Ripple Frequency (Hz)
Figure 19. Figure 20.

CHANGE IN INTEGRAL LINEARITY

AND DIFFERENTIAL LINEARITY
vs REFERENCE VOLTAGE
0.20
VCC = 5V
Delta from +2.5V Reference (LSB)

0.15

0.10 Change in Integral

Linearity (LSB)
0.05

0.00

-0.05 Change in Differential

Linearity (LSB)
-0.10
1 2 3 4 5
Reference Voltage (V)
Figure 21.

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THEORY OF OPERATION

The ADS7822 is a classic successive approximation The range of the –In input is limited to –0.2V to +1V.
register (SAR) A/D converter. The architecture is Because of this, the differential input can be used to
based on capacitive redistribution that inherently reject only small signals that are common to both
includes a sample/hold function. The converter is inputs. Thus, the –In input is best used to sense a
fabricated on a 0.6μ CMOS process. The architecture remote signal ground that may move slightly with
and process allow the ADS7822 to acquire and respect to the local ground potential.
convert an analog signal at up to 200,000
The input current on the analog inputs depends on a
conversions per second while consuming very little
number of factors: sample rate, input voltage, source
power.
impedance, and power-down mode. Essentially, the
The ADS7822 requires an external reference, an current into the ADS7822 charges the internal
external clock, and a single power source (VCC). The capacitor array during the sample period. After this
external reference can be any voltage between 50mV capacitance has been fully charged, there is no
and VCC. The value of the reference voltage directly further input current. The source of the analog input
sets the range of the analog input. The reference voltage must be able to charge the input capacitance
input current depends on the conversion rate of the (25pF) to a 12-bit settling level within 1.5 clock
ADS7822. cycles. When the converter goes into the hold mode
or while it is in the power-down mode, the input
The external clock can vary between 10kHz (625Hz impedance is greater than 1GΩ.
throughput) and 3.2MHz (200kHz throughput). The
duty cycle of the clock is essentially unimportant as Care must be taken regarding the absolute analog
long as the minimum high and low times are at least input voltage. To maintain the linearity of the
400ns for a supply range between 2.7V to 3.6V, or converter, the –In input should not drop below GND –
125ns for a supply range between 4.75V to 5.25V. 200mV or exceed GND + 1V. The +In input should
The minimum clock frequency is set by the leakage always remain within the range of GND – 200mV to
on the capacitors internal to the ADS7822. VCC + 200mV. Outside of these ranges, the converter
linearity may not meet specifications.
The analog input is provided to two input pins: +In
and –In. When a conversion is initiated, the
differential input on these pins is sampled on the REFERENCE INPUT
internal capacitor array. While a conversion is in The external reference sets the analog input range.
progress, both inputs are disconnected from any The ADS7822 operates with a reference in the range
internal function. of 50mV to VCC. There are several important
implications of this.
The digital result of the conversion is clocked out by
the DCLOCK input and is provided serially, most As the reference voltage is reduced, the analog
significant bit first, on the DOUT pin. The digital data voltage weight of each digital output code is reduced.
that is provided on the DOUT pin is for the conversion This is often referred to as the LSB (least significant
currently in progress—there is no pipeline delay. It is bit) size and is equal to the reference voltage divided
possible to continue to clock the ADS7822 after the by 4096. This means that any offset or gain error
conversion is complete and to obtain the serial data inherent in the A/D converter will appear to increase,
least significant bit first. See the Digital Interface in terms of LSB size, as the reference voltage is
section for more information. reduced.

ANALOG INPUT
The +In and –In input pins allow for a
pseudo-differential input signal. Unlike some
converters of this type, the –In input is not resampled
later in the conversion cycle. When the converter
goes into the hold mode, the voltage difference
between +In and –In is captured on the internal
capacitor array.

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The noise inherent in the converter will also appear to DIGITAL INTERFACE
increase with lower LSB size. With a 2.5V reference,
the internal noise of the converter typically contributes Signal Levels
only 0.32 LSB peak-to-peak of potential error to the
output code. When the external reference is 50mV, The digital inputs of the ADS7822 can accommodate
logic levels up to 6V regardless of the value of VCC.
the potential error contribution from the internal noise
Thus, the ADS7822 can be powered at 3V and still
will be 50 times larger—16 LSBs. The errors due to
accept inputs from logic powered at 5V.
the internal noise are gaussian in nature and can be
reduced by averaging consecutive conversion results. The CMOS digital output (DOUT) will swing 0V to VCC.
If VCC is 3V and this output is connected to a 5V
For more information regarding noise, consult the
CMOS logic input, then that IC may require more
typical characteristic curves Effective Number of Bits
supply current than normal and may have a slightly
vs Reference Voltage and Peak-to-Peak Noise vs
longer propagation delay.
Reference Voltage. Note that the effective number of
bits (ENOB) figure is calculated based on the
Serial Interface
converter signal-to-(noise + distortion) ratio with a
1kHz, 0dB input signal. SINAD is related to ENOB as The ADS7822 communicates with microprocessors
follows: and other digital systems via a synchronous 3-wire
serial interface, as shown in Figure 22 and Table 1.
SINAD = 6.02 • ENOB + 1.76
The DCLOCK signal synchronizes the data transfer
With lower reference voltages, extra care should be with each bit being transmitted on the falling edge of
taken to provide a clean layout including adequate DCLOCK. Most receiving systems will capture the
bypassing, a clean power supply, a low-noise bitstream on the rising edge of DCLOCK. However, if
reference, and a low-noise input signal. Because the the minimum hold time for DOUT is acceptable, the
LSB size is lower, the converter will also be more system can use the falling edge of DCLOCK to
sensitive to external sources of error such as nearby capture each bit.
digital signals and electromagnetic interference.

tCYC
CS/SHDN

tSUCS Power
Down
DCLOCK
tCSD
Null Null
Hi-Z Bit (1) Hi-Z Bit
DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
tSMPL (MSB)
tCONV tDATA

Note: (1) After completing the data transfer, if further clocks are applied with CS LOW,
the A/D will output LSB-First data then followed with zeroes indefinitely.

tCYC
CS/SHDN

tSUCS Power Down

DCLOCK
tCSD
Null
Hi-Z Bit Hi-Z
DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(1)
tSMPL (MSB)
tCONV tDATA

Note: (1) After completing the data transfer, if further clocks are applied with CS LOW,
the A/D will output zeroes indefinitely.

tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-first data or zeroes.

Figure 22. Basic Timing Diagrams

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Table 1. Timing Specifications (–40°C to +85°C)

VCC = 2.7V VCC = 5V
SYMBOL DESCRIPTION UNITS
MIN TYP MAX MIN TYP MAX
tSMPL Analog input sample time 1.5 2.0 1.5 2.0 Clk Cycles
tCONV Conversion time 12 12 Clk Cycles
tCYC Cycle time 16 16 Clk Cycles
tCSD CS falling to DCLOCK low 0 0 ns
tSUCS CS falling to DCLOCK rising 0.03 1000 0.03 1000 μs
thDO DCLOCK falling to current DOUT not valid 15 15 ns
tdDO DCLOCK falling to next DOUT valid 130 200 85 150 ns
tdis CS rising to DOUT tri-state 40 80 25 50 ns
ten DCLOCK falling to DOUT enabled 75 175 50 100 ns
tf DOUT fall time 90 200 70 100 ns
tr DOUT rise time 110 200 60 100 ns

1.4V

3kW VOH
DOUT
DOUT VOL
Test Point
tr tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf

Load Circuit for tdDO, tr, and tf

Test Point

DCLOCK VIL VCC

3kW tdis Waveform 2, ten
tdDO DOUT

VOH 100pF tdis Waveform 1

DOUT
CLOAD
VOL
thDO
Load Circuit for tdis and ten
Voltage Waveforms for DOUT Delay Times, tdDO

CS/SHDN VIH CS/SHDN

DOUT DCLOCK 1 2
90%
Waveform 1(1)
tdis
DOUT VOL
DOUT B11
10%
Waveform 2(2)
ten
Voltage Waveforms for tdis
Voltage Waveforms for ten

NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control.
(2) Waveform 2 is for an output with internal conditions such that the output
is LOW unless disabled by the output control.

Figure 23. Timing Diagrams and Test Circuits for the Parameters in Table 1

12 Submit Documentation Feedback Copyright © 1996–2007, Texas Instruments Incorporated

Product Folder Link(s): ADS7822

 ADS7822

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SBAS062C – JANUARY 1996 – REVISED AUGUST 2007

A falling CS signal initiates the conversion and data transition (as is typical for digital CMOS components),
transfer. The first 1.5 to 2.0 clock periods of the but also uses some current for the analog circuitry,
conversion cycle are used to sample the input signal. such as the comparator. The analog section
After the second falling DCLOCK edge, DOUT is dissipates power continuously, until the power-down
enabled and outputs a low value for one clock period. mode is entered.
For the next 12 DCLOCK periods, DOUT outputs the
Figure 24 shows the current consumption of the
conversion result, most significant bit first.
ADS7822 versus sample rate. For this graph, the
After the least significant bit (B0) has been output, converter is clocked at 1.2MHz regardless of the
subsequent clocks repeat the output data, but in a sample rate—CS is high for the remaining sample
least significant bit first format. After the most period. Figure 25 also shows current consumption
significant bit (B11) has been repeated, DOUT will versus sample rate. However, in this case, the
tri-state. Subsequent clocks have no effect on the DCLOCK period is 1/16th of the sample period—CS
converter. A new conversion is initiated only when CS is high for one DCLOCK cycle out of every 16.
is taken high and returned low.
1000
Data Format TA = 25°C
fCLK = 1.2MHz
The output data from the ADS7822 is in straight

Supply Current (mA)

binary format, as shown in Table 2. This table 100
represents the ideal output code for the given input
voltage and does not include the effects of offset, VCC = 5.0V VCC = 2.7V
gain error, or noise. VREF = 5.0V VREF = 2.5V
10
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT
DESCRIPTION ANALOG VALUE
STRAIGHT BINARY
Full-Scale range VREF 1
0.1 1 10 100
Least significant
VREF/4096 Sample Rate (kHz)
bit (LSB) BINARY CODE HEX CODE
Full-Scale VREF – 1 LSB 1111 1111 1111 FFF
Midscale VREF/2 1000 0000 0000 800 Figure 24. Maintaining fCLK at the Highest
Midscale – 1 LSB VREF/2 – 1 LSB 0111 1111 1111 7FF Possible Rate Allows the Supply Current to Drop
Zero 0V 0000 0000 0000 000
Linearly with the Sample Rate

POWER DISSIPATION 1000

The architecture of the converter, the semiconductor

fabrication process, and a careful design allow the
Supply Current (mA)

ADS7822 to convert at up to a 75kHz rate while 100

requiring very little power. Still, for the absolute
lowest power dissipation, there are several things to
keep in mind.
10
The power dissipation of the ADS7822 scales directly TA = 25°C
with conversion rate. So, the first step to achieving VCC = 2.7V
the lowest power dissipation is to find the lowest VREF = 2.5V
fCLK = 16 · fSAMPLE
conversion rate that will satisfy the requirements of 1
the system. 0.1 1 10 100
In addition, the ADS7822 goes into power-down Sample Rate (kHz)
mode under two conditions: when the conversion is
complete and whenever CS is high (see Figure 22). Figure 25. Scaling fCLK Reduces the Supply
Ideally, each conversion should occur as quickly as Current Only Slightly with the Sample Rate
possible; preferably, at a 1.2MHz clock rate. This
way, the converter spends the longest possible time
in the power-down mode. This is very important since
the converter not only uses power on each DCLOCK

Copyright © 1996–2007, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): ADS7822
ADS7822

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SBAS062C – JANUARY 1996 – REVISED AUGUST 2007

There is an important distinction between the

power-down mode that is entered after a conversion
Power dissipation can also be reduced by lowering
is complete and the full power-down mode that is
the power-supply voltage and the reference voltage.
enabled when CS is high. While both shutdown the
analog section, the digital section is completely The ADS7822 operates over a VCC range of 2.0V to
5.25V. It will run up to a 200kHz throughput rate over
shutdown only when CS is high. Thus, if CS is left
a supply range of 4.75V to 5.25V; therefore, it can be
low at the end of a conversion and the converter is
clocked at up to 3.2MHz. However, at voltages below
continually clocked, the power consumption will not
2.7V, the converter does not run at a 75kHz sample
be as low as when CS is high; see Figure 26 for more
rate. See the Typical Characteristic curves for more
information.
information regarding power-supply voltage and
maximum sample rate.
10.0
TA = 25°C
VCC = 2.7V Short Cycling
8.0 VREF = 2.5V
fCLK = 16 · fSAMPLE Another way of saving power is to use the CS signal
Supply Current (mA)

6.0 to short-cycle the conversion. Because the ADS7822

places the latest data bit on the DOUT line as it is
4.0 CS LOW (GND)
generated, the converter can easily be short-cycled.
This term means that the conversion can be
2.0 terminated at any time. For example, if only eight bits
of the conversion result are needed, then the
0.0
CS HIGH (VCC) conversion can be terminated (by pulling CS high)
0.050 after the eighth bit has been clocked out.
0.00
0.1 1 10 100 This technique can be used to lower the power
Sample Rate (kHz) dissipation (or to increase the conversion rate) in
those applications where an analog signal is being
Figure 26. Shutdown Current with CS High is monitored until some condition becomes true. For
Typically 50nA, Regardless of the Clock. example, if the signal is outside a predetermined
Shutdown Current with CS Low varies with range, the full 12-bit conversion result may not be
Sample Rate. needed. If so, the conversion can be terminated after
the first n-bits, where n might be as low as 3 or 4.
This results in lower power dissipation in both the
converter and the rest of the system, because they
spend more time in the power-down mode.

14 Submit Documentation Feedback Copyright © 1996–2007, Texas Instruments Incorporated

Product Folder Link(s): ADS7822

 ADS7822

www.ti.com
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007

LAYOUT Also, keep in mind that the ADS7822 offers no

inherent rejection of noise or voltage variation in
For optimum performance, care should be taken with regards to the reference input. This is of particular
the physical layout of the ADS7822 circuitry. This is concern when the reference input is tied to the power
particularly true if the reference voltage is low and/or supply. Any noise and ripple from the supply will
the conversion rate is high. At a 75kHz conversion appear directly in the digital results. While
rate, the ADS7822 makes a bit decision every 830ns. high-frequency noise can be filtered out as described
If the supply range is limited to 4.75V to 5.25V, then in the previous paragraph, voltage variation due to
up to a 200kHz conversion rate can be used, which the line frequency (50Hz or 60Hz), can be difficult to
reduces the bit decision time to 312ns. That is, for remove.
each subsequent bit decision, the digital output must
be updated with the results of the last bit decision, The GND pin on the ADS7822 should be placed on a
the capacitor array appropriately switched and clean ground point. In many cases, this will be the
charged, and the input to the comparator settled to a analog ground. Avoid connecting the GND pin too
12-bit level all within one clock cycle. close to the grounding point for a microprocessor,
microcontroller, or digital signal processor. If needed,
The basic SAR architecture is sensitive to spikes on run a ground trace directly from the converter to the
the power supply, reference, and ground connections power-supply connection point. The ideal layout will
that occur just prior to latching the comparator output. include an analog ground plane for the converter and
Thus, during any single conversion for an n-bit SAR associated analog circuitry.
converter, there are n windows in which large
external transient voltages can easily affect the
conversion result. Such spikes might originate from APPLICATION CIRCUITS
switching power supplies, digital logic, and Figure 27 and Figure 28 show some typical
high-power devices, to name a few. This particular application circuits for the ADS7822. Figure 27 uses
source of error can be very difficult to track down if an ADS7822 and a multiplexer to provide for a
the glitch is almost synchronous to the converter flexible data acquisition circuit. A resistor string
DCLOCK signal because the phase difference provides for various voltages at the multiplexer input.
between the two changes with time and temperature, The selected voltage is buffered and driven into VREF.
causing sporadic misoperation. As shown in Figure 27, the input range of the
ADS7822 is programmable to 100mV, 200mV,
With this in mind, power to the ADS7822 should be
300mV, or 400mV. The 100mV range would be
clean and well-bypassed. A 0.1μF ceramic bypass
useful for sensors such as the thermocouple shown.
capacitor should be placed as close to the ADS7822
package as possible. In addition, a 1μF to 10μF Figure 28 shows a basic data acquisition system. The
capacitor and a 5Ω or 10Ω series resistor can be ADS7822 input range is 0V to VCC, as the reference
used to lowpass filter a noisy supply. input is connected directly to the power supply. The
5Ω resistor and 1μF to 10μF capacitor filter the
The reference should be similarly bypassed with a
microcontroller noise on the supply, as well as any
0.1μF capacitor. Again, a series resistor and large
high-frequency noise from the supply itself. The exact
capacitor can be used to lowpass filter the reference
values should be picked such that the filter provides
voltage. If the reference voltage originates from an op
adequate rejection of the noise.
amp, be careful that the op amp can drive the bypass
capacitor without oscillation (the series resistor can
help in this case). Keep in mind that while the
ADS7822 draws very little current from the reference
on average, there are still instantaneous current
demands placed on the external reference circuitry.

Copyright © 1996–2007, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): ADS7822
ADS7822

www.ti.com
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007

+3V

+3V +3V
R8
26kW
0.4V
R7
R9
5W
R1 1kW
OPA237
D1 150kW C2 0.3V
R3 U2
0.1mF R10
500kW C1
Mux 1kW
R2 R6 VREF 10mF
59kW 1MW DCLOCK 0.2V
R11
C3 DOUT 1kW
TC1 ADS7822 A0
TC2 0.1mF
CS/SHDN 0.1V
Thermocouple A1
R12
TC3 C4 U1 1kW
R4 U3
10mF R5 C5
1kW
500W 0.1mF P
ISO Thermal Block

3-Wire
Interface
U4

Figure 27. Thermocouple Application Using a Mux to Scale the Input Range of the ADS7822

+2.7V to +3.6V

5W

+ 1mF to
10mF
ADS7822

VREF VCC
+ 1mF to
0.1mF 10mF

+In CS Microcontroller

-In DOUT

GND DCLOCK

Figure 28. Basic Data Acquisition System

16 Submit Documentation Feedback Copyright © 1996–2007, Texas Instruments Incorporated

Product Folder Link(s): ADS7822

 ADS7822

www.ti.com
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007

Revision History

Changes from Revision B (May 2006) to Revision C ...................................................................................................... Page

• Added – GND to absolute input range test conditions .......................................................................................................... 3

• Added – GND to absolute input range test conditions .......................................................................................................... 3
• Changed VCC min from 3.6 V to 2.7 V ................................................................................................................................... 3
• Changed VCC max from 5.25 V to 3.6 V ................................................................................................................................ 3
• Changed VCC min from 3.6 V to 2.7 V ................................................................................................................................... 3
• Changed VCC max from 5.25 V to 3.6 V ................................................................................................................................ 3
• Changed VCC min from 3.6 V to 2.7 V ................................................................................................................................... 3
• Changed VCC max from 5.25 V to 3.6 V ................................................................................................................................ 3
• Added – GND to absolute input range test conditions .......................................................................................................... 4
• Added – GND to absolute input range test conditions .......................................................................................................... 4

Copyright © 1996–2007, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Link(s): ADS7822
 PACKAGE OPTION ADDENDUM

www.ti.com 1-Aug-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS7822E/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822E/250G4 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822E/2K5 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822E/2K5G4 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822EB/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822EB/2K5 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822EB/2K5G4 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822EC/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822EC/2K5 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822EC/2K5G4 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A22 Samples

ADS7822U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U
ADS7822U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U
ADS7822UB ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U
ADS7822UB/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U
ADS7822UBG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U
ADS7822UC ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U
ADS7822UC/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7822U

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 1-Aug-2024

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS7822 :

• Automotive : ADS7822-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7822U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS7822UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS7822UC/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7822U/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS7822UB/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS7822UC/2K5 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ADS7822U D SOIC 8 75 506.6 8 3940 4.32
ADS7822UB D SOIC 8 75 506.6 8 3940 4.32
ADS7822UBG4 D SOIC 8 75 506.6 8 3940 4.32
ADS7822UC D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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