12/10/24, 4:39 PM Power Analysis | VLSI Back-End Adventure

a VLSI BACK-END ADVENTURE (INDEX.HTML) Search Feroz Ahmed ()

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h Physical Design 5 Content on this page Power Analysis

h PD Verification Power Analysis

(pd_verification.html) -Leakeage Power
-Switching Power Physical Design Analysis (pd_qa.html)

h PD Analysis 5
-Short Circuit
Digital Electronics Q&A
Leakage/static Power
-Static power Dissipation
Power Analysis (digital_electronics.html)

h PD Essentials 5 -Types of Static Leakage

-Static Power Reduction
Power Density of the Integrated Circuit increase exponentially with every Technology generation
PTOTAL = PDYNAMIC + PLEAKAGE
Physical Design MCQs
(pd_mcqs.html)
Techniques PDYNAMIC = PSWITCHING + PSHORT_CIRCUIT
h Discontinuity 5 Dynamic/Switching Power
-Dynamic Power calculation Leakage Power (Static Power): Leakage at almost all junctions due to various effects
STA Numericals
(sta_numericals.html)

 Videos depends on
-Types of Dynamic Power
Reverse Biased Diode Leakage
Gate Induced Drain Leakage
PD Verification
(videos.html) -Dynamic Power Reduction Gate Oxide Tunnelling (pd_verification.html)
Techniques Sub-threshold Leakage

 STA Numericals Switching Power: When signal change their state, energy is drawn from the power supply to charge up the loadcapacitance from
(sta_numericals.html)
0 to VDD 
Logic Synthesis

 Q&A 5 Short Circuit Power (Crowbar Power/ EM Rush Through Power): Finite non-zero rise and fall times of transistors which causes
a direct current path between the Power and Ground` PD Inputs 

h Extras (Extras.html) Static/ Leakage Power Analysis

Dynamic Power Analysis
FloorPlan 

PowerPlan 

Placement 

CTS 

Routing 

STA 

Congestion Analysis 

Power Analysis 

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a VLSI BACK-END ADVENTURE (INDEX.HTML) IR Analysis Feroz Ahmed 

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 Home (index.html) Issues in PD 

h Physical Design 5 With Shrinking technology Static leakage increases which results in more focus in Reducing leakage power for advanced
technologies
Cells in PD 

h PD Verification IO Design 
Static Power/ Leakage Power
(pd_verification.html) 
It is the power consumed when the device is powered up but no signals are changing value (when the transistors are not Delay Models
switching)
h PD Analysis 5 In CMOS devices, static power consumption is due to leakage
Sub-threshold leakage occurs when a CMOS gate is not turned completely OFF
ECO


h PD Essentials 5 Types of Std cells



h Discontinuity 5 where
DFM/DFY 

 Videos
μ - Carrier mobility 
COX - Gate capacitance MC/MM/OCV
(videos.html) VT - Threshold voltage
VGS - Gate-Source voltage

 STA Numericals W and L - Dimensions of the transistor

VTH - Thermal voltage, kT/q = 25.9mV at room temperature
(sta_numericals.html) n - function of device fabrication process (ranges 1.0 -2.5)

 Q&A 5
Static Power Dissipation — Leakage Power, is consumed when the transistors are not switching
Dependent on the voltage, temperature and state of the transistors
Leakage Power = V * Ileak

h Extras (Extras.html) Types of Static Leakages

Reverse biased diode leakage from the diffusion layers and the substrate
Gate Induced Drain Leakage
Gate Oxide Tunnelling
Sub-threshold Leakage caused by reduced threshold voltages which prevents the Gate from completely turning OFF

Static Power Reduction Techniques

Using Multi VT cell in the design and optimizing for leakage by replacing high VT cell for non timing critical paths
Power Gating
Power Shut-off groups of logic which are not used
Voltage Scaling
Multi VDD and Voltage Island
Multi-threshold CMOS (Back Biasing)

Dynamic/ Switching Power

Dynamic power is the power consumed when the device is active, when signals are changing values (by switching logic states)
Primary source of dynamic power consumption is switching power
PDYN= A C V2 F
h

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12/10/24, 4:39 PM Power Analysis | VLSI Back-End Adventure

where,

a VLSI BACK-END ADVENTURE A is activity factor, i.e., the fraction of the circuit that is switching
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C is Load capacitance
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V is supply voltage
 Home (index.html) F is clock frequency

h Physical Design 5 Dynamic Power Calculation depends on

h PD Verification Switching frequency
Transition
(pd_verification.html) Output load
Cell internal power Dynamic Power Dissipation
h PD Analysis 5 Dynamic power is dissipated any time the voltage on a net changesdue to some stimulus

Types of Dynamic Power

h PD Essentials 5 Net Switching Power = (Cint * V*V *f)

Internal Power = (Cint * V*V *f) + (V * Isc)

h Discontinuity 5 Short Circuit : = (V*ISC) During switching both PMOS and NMOS becomes on which results in a short circuit current
Internal Capacitance Loading Power = (Cint * V*V *f) is the power consumed while charging/discharging internal nets

 Videos Dynamic Power Reduction Techniques

(videos.html)

 STA Numericals
(sta_numericals.html)

 Q&A 5
h Extras (Extras.html)

Dynamic Power Reduction Techniques

Clock Gating
Architectural Technique to reduce Dynamic Power along the Clock Path
Clock gates should be placed at the Root of the Clock
Results in small delay, more area and makes the design complex
Clock Gating logic is generally in the form of "Integrated clock gating" (ICG)
Sequential clock gating is the process of extracting/propagating the enable conditions to the upstream/downstream sequential
elements, so that additional registers can be clock gated

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12/10/24, 4:39 PM Power Analysis | VLSI Back-End Adventure

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As the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit
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approaches that of an asynchronous circuit: the circuit only generates logic transitions when it is actively computing Feroz Ahmed ()

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