Int. J. Electron. Commun.

(AEÜ) 108 (2019) 251–261

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

Regular paper

Impact of different localized trap charge profiles on the short

channel double gate junctionless nanowire transistor based inverter
and Ring Oscillator circuit
Neha Garg a, Yogesh Pratap a, Mridula Gupta b, Sneha Kabra a,⇑
a
Department of Instrumentation, Shaheed Rajguru College of Applied Sciences for Women, University of Delhi, Delhi 110096, India
b
Semiconductor Device Research Laboratory, Department of Electronics, University of Delhi South Campus, New Delhi 110021, India

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, the reliability issues due to localized charges on Double Gate Junctionless Nanowire
Received 12 March 2019 Transistor (DG-JNT) based circuits are investigated. The localized/fixed charges come into existence at
Accepted 17 June 2019 the interface of substrate and oxide in the device during the manufacturing due to radiation, stress, pro-
cess and hot carriers damage which significantly alters various characteristics of the device. The damage
due to different profiles of localized charges on several parameters of DG-JNT based P-MOSFET is ana-
Keywords: lyzed. Also, for analog circuit application, this work explicitly reports the comprehensive analysis of local-
Double Gate Junctionless Nanowire
ized charge profiles on DG- JNT based CMOS inverter and three Stage Ring Oscillator circuit at 20 nm Gate
Transistor (DG-JNT)
Hot-carrier effects
length. The simulated results are obtained using Silvaco Atlas, TCAD device simulator.
Localized charges Ó 2019 Elsevier GmbH. All rights reserved.
Interface trap charges
Short Channel Effects (SCE’s)

1. Introduction It’s a challenge for manufacturers to make a steep source and

drain channel junctions in short channel length devices. The P-N
Over the past years, the fast-paced development in semicon- junction at source and drain not only enhance the fabrication com-
ductor technology has seen a tremendous increase in attention in plication but also impacts the device electrical characteristics. To
device modeling and simulation. Scaling in the semiconductor overcome these challenges, Jean-Pierre Colinge’s at Tyndall
devices, which leads to various short channel effects in the MOS National Institute designed and fabricated first junction less tran-
devices augmented the minds of manufacturers to find novel tech- sistor (JNT), which is a novel structure that revolutionized micro-
nologies for extremely smaller dimensions [1]. Many novel struc- chip manufacturing in the semiconductor industry [9]. Doping is
tures have been proposed for the nanoscale regime. One solution uniform throughout (source, channel and drain region) in JNT,
is Multi- gate MOSFET. Other possible structures to extend Moore’s which eliminates the crisis related with the diffusion of impurities
law include tunnel FET, nanowire FET, FinFET, SOI technology and and also simplifies the process of fabrication. JNT also shows high
Carbon nanotube FETs, etc. [2–7]. Multi-gate structures are the current driving capability, offers good Ion/Ioff ratio and is more
promising architectures for Nano-dimension devices. They have resistive to various SCE’s. Due to all these advantages, JNT has
the ability to deplete the channel completely and also have more gained a lot of scope in the microelectronic industry.
controlling power over the channel region. Double gate MOSFET Apart from SCE’s immunity, reliability is also one of the major
(DG-MOSFET) has proven to be a good structure to overcome var- concerns for the devices having small dimensions. During the man-
ious short channel effect’s (SCE’s) [8]. It reduces sub threshold cur- ufacturing of device, various types of charges are induced into the
rent as both the gates, upper and lower control the channel more oxide and traps at Si-SiO2 interface which degrade the performance
effectively than the conventional structure. The presence of con- of device. Basic classification of these traps and charges are: (a)
ducting channel on both sides also increases ON current (Ion) of interface-trapped charge, (b) fixed-oxide charge, (c) oxide-
the device. trapped charge and (d) mobile ionic charge [10]. It’s very important
to study the impact of interface trapped charge on device perfor-
mance. Trap charges at the Si-SiO2 interface appear because of
⇑ Corresponding author. interrupted periodic lattice structure at interface. These trap
E-mail addresses: mridula@south.du.ac.in (M. Gupta), snehakabra1@gmail.com charges at the interface are induced due to various type of damages
(S. Kabra).

https://doi.org/10.1016/j.aeue.2019.06.014
1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.
252 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261

Fig. 1. (a) 2-D view of DG-JNT P-MOSFET, (b) 2-D view of DG-JNT N-MOSFET and (c) Different Interface charge density profiles.

like radiation induced damage, stress induced damage, process based P-MOSFET for the device having the gate length of 20 nm has
induced damage and hot carrier induced damage during the pro- been studied. The main objective of this work is to investigate the
cess of manufacturing [11–13]. These trap charges have a serious impact of different profiles of localized charges present at Si-SiO2
impact on the performance of MOSFET based devices. Previously, interface on different characteristics of DGJNT based CMOS
a lot of research works related to the effect of localized charge inverter. In this paper we have also evaluated the performance
on Double Gate (DG) MOSFET [14], Tunnel FET [15], GAA MOSFET
[16–18] have been carried out. Double gate transistor structures
based on the junctionless concept for the gate length of 32 nm
Table 1
was investigated previously for the impact of interface/localized Localized charge density profile and their cause of damage.
charges [19]. But the effect of different charge density profiles
Type of profile Cause of damage QF (cm
2)
due to different defects added during the manufacturing process
are still not addressed for double gate junctionless MOSFET. Perfor- Step (Maximum at Hot Electron stress [25] 1012
drain)
mance of CMOS inverter which is the basic building block of digital
Uniform Process Damage [26] 1011 –1012
circuits depends majorly on P-MOSFET which acts as the load in Uniform Radiation Induced Damage [27] 4.0  1010–8.0  1011
CMOS Inverter [20]. In the present work, the performance of DGJNT
 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261 253

degradation due to different profiles of localized charges on three three stage Ring Oscillator circuit have been discussed in detail
stage DGJNT based Ring oscillator. Designing of CMOS inverter is in Section 3. Finally, the conclusion is drawn in Section 4.
done by customizing the PMOS and NMOS devices for same thresh-
old voltage. Designed CMOS inverter shows near ideal transfer
characteristics and a high value of noise margin as it is designed 2. Device structure and simulation
using Double gate, which controls channel from both sides and
junctionless concept which involves bulk conduction rather than Fig. 1(a) and (b) represents a two-Dimensional structure of a
surface conduction. Hence it offers high on current (Ion) and DG-JNT P- MOSFET and DG-JNT N- MOSFET respectively. In this
improves overall performance [21]. With continuous scaling, the device, gates present on both sides (upper and lower) control the
reliability concern of the device becomes more severe. In order to channel region and hence provide better performance by reducing
enhance the design efficiency, it becomes important to study the various SCE’s. No junctions are present in the device and uniform
impact of localized trap charges not only at transistor level but at doping of 1018 cm-3 is considered throughout the device from the
circuit level as well. The impact of these trap charges on DG-JNT source region to drain region. The trap charges are considered on
based CMOS inverter and DG-JNT based Ring Oscillator circuit both sides of the device at Si-SiO2 interface, since the damage
has also been studied. Substrate/Oxide interface acts as a negative caused due to fabrication will have an impact on both sides.
interface trap charge, if it accepts the electron and as a positive Fig. 1(c) shows different profiles of localized charge density which
interface trap charge, if it donates the electron. Therefore, in this are considered, keeping in view that trap charges created due to
analysis, both positive as well as negative charges have been taken the different type of damages during the manufacturing process
into consideration. of the device are different. The step profile of trap charges is caused
The paper is organized as follows. The device structure and sim- due to Hot Electron stress and Uniform profile of trap charges is
ulation set-up are discussed in Section 2. Various methods and caused due to Process/Radiation induced damage, as mentioned
models used to evaluate surface potential, drain current and in Table 1 [22].For the validation of the simulated structure, mod-
threshold voltage have been discussed in this section. It is followed els used for DG-JNT transistor in previously published work have
by results and discussion in Section 3. Performance of DG-JNT been taken into consideration [23]. Simulated results are obtained
based PMOSFET, DG-JNT based CMOS inverter and DG-JNT based using Silvaco ATLAS, TCAD device simulator [24].

Fig. 2. Effect of localized charges on the surface potential of DGJNT for different interface charge density profiles.
254 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261

3. Results and discussion for two different types of trap charges (positive and negative). The
surface potential is found to be higher for the Positive charges as
3.1. DG-JNT based PMOSFET performance compared to negative charges.
In case of step profile of the charge, the effect of trap charges is
3.1.1. Surface potential more at drain side as can be seen from Fig. 2(a). For Gaussian
Fig. 2 shows the variation in the surface potential of DG-JNT charge profile, the impact is maximum at center as depicted
MOSFET as a function of channel length for different density pro- Fig. 2(c). Fig. 2(b) shows that, for Uniform charge profile, effect of
files of interface charges. Variation in surface potential is analyzed charges is even throughout the device. In case of linearly graded

Fig. 3. (a), (b), (c) &(d) Effect of localized charges on drain current of DGJNT for different interface charge density profile & (e) Change in ratio of Ioff of DGJNT due to different
interface charge density profile.
 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261 255

profile, the impact of trap charges increases towards the drain as where
shown in Fig. 2(d). The variation in surface potential is mainly
caused by flat band voltage. Due to the interface (Si-SiO2) trap Q F is the density of interface trap charge
charge, the amount of change in flat band voltage is given by [28]: C ox is the capacitance of gate-oxide
qQ F
DV fb ¼ ð1Þ
C ox

Fig. 4. Variation in threshold voltage of DGJNT for different interface charge density
profile. Fig. 6. DGJNT based CMOS Inverter.

Fig. 5. Variation in Transconductance of DGJNT for different interface charge density profile.
256 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261

3.1.2. Drain current

Fig. 3 shows the change in drain current because of the change
of gate to source voltage (transfer characteristics) for different
interface charge density profiles of DG-JNT MOSFET. Drain current
is analyzed for both positive and negative charges. Since, the vari-
ation in flatband voltage is more in subthreshold region, therefore
the interface trap charges cause more degradation in subthreshold
current in all cases. The drain current degradation is found to be
maximum for uniform charge density profile and minimum for
step function profile. This is because in step charge density profile
the trap charges exist at only half region of Silicon-Silicon dioxide
Fig. 7. Drain Current versus Gate Voltage graphs of N-channel and P -channel interface. Fig. 3(e) shows the comparison of ratio of change in off
DGJNT. current due to different profiles of trap charges under study. For

Fig. 8. (a), (b), (c) &(d) Voltage Transfer Characteristics of DG-JNT based CMOS Inverter for different interface charge density profile & (e) Change in switching voltage of DG-
JNT based CMOS Inverter for different interface charge density profile.
 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261 257

uniform profile there is maximum change in ratio of Ioff, 11.2 for step profile, change in threshold voltage due to trap charges are
positive charges and 12.13 for negative charges whereas for step minimum (44% for positive and 52% for negative trap charge) as
profile minimum change in ratio of Ioff, 3.97 for positive charges charges cover only the half part of the interface. The percentage
and 3.67 for negative charges is observed. However, for Gaussian change in threshold voltage of the device in case of linearly graded
profile change in ratio of Ioff is approximately equal for positive profile (60% for positive and 59% for negative trap charge) is almost
and negative charges, 8.48 for positive charges and 9.02 for nega- the same for positive and negative trap charge and in case of gaus-
tive charges and for Linearly Graded profile change in ratio of Ioff sian profile also, the change in threshold voltage for positive and
is also observed to be almost same for positive and negative negative trap charges is same (64% for positive and 66% for nega-
charges, 5.8 for positive charges and 6.08 for negative charges. tive trap charge)
For positive charges the ratio Ioff(undamaged)/Ioff(damaged) and for neg-
ative charges the ratio Ioff(damaged)/Ioff(undamaged) is calculated for
comparison. 3.1.4. Transconductance
Transconductance is a very important parameter for a device as
3.1.3. Threshold voltage it decides the gain, efficiency, cut-off frequency and bias point of
In MOSFET, threshold voltage plays an important role in various the device. Deviation in transconductance directly impacts RF per-
digital circuit applications and is severely affected by SCEs. Thus, formance of the device [30]. Fig. 5 shows the change in transcon-
various parameters causing variation in threshold voltage need to ductance for different interface charge density profiles of DG-JNT
be studied and addressed [29]. Fig. 4 shows the change in the value MOSFET. Due to the presence of trap charges, a shift in bias point
of threshold voltage for different profiles of trap charge density at of about 16.6% for positive charges and 33.33% for negative charges
the interface. Maximum change in threshold voltage (80% for pos- is observed corresponding to transconductance peak value for uni-
itive and 70% for negative trap charge) is observed for uniform pro- form profile. However, shift in bias point corresponding to
file of charges at the interface. This is because the change in transconductance peak value for all other profiles for both the
minimum surface potential is maximum for this profile. For the types of charge carriers positive and negative is observed to be

Fig. 9. Butterfly Plot of DG-JNT based CMOS Inverter for different interface charge density profile.
258 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261

same i.e. 16.6%. This shift of bias point is a big threat to circuit margin (NMH-Noise margin high and NML-Noise margin low) of
reliability. DG-JNT based CMOS inverter through butterfly graphs. In case of
step profile, since the change in minimum surface potential and
3.2. DG-JNT based CMOS Inverter performance drain current is least among all four profiles of trap charges, there-
fore, change in noise margin is also minimum as compared to the
In this section CMOS Inverter circuit shown in Fig. 6, has been non-degraded device
designed and degradation in device performance due to presence
of localized charges at substrate and oxide interface is presented. 3.3. DG-JNT based ring oscillator performance
Fig. 7 shows variation of drain current with gate voltage. It can
be clearly seen from the figure that both DG JNT based PMOS In this section, three stage CMOS Ring Oscillator circuit shown
and NMOS exhibit threshold voltage of approximately 0.5 V. The in Fig. 10, has been designed and degradation in it due to presence
similar threshold voltage is obtained by optimizing the work func- of localized charges at substrate and oxide interface is discussed.
tion of gate metal. This Oscillator is formed using an odd number of inverters and out-
put of each stage is given as input to the next stage. The first stage
3.2.1. Transfer characteristics is fed back by the output of the last stage and thus form a ring. Each
Fig. 8 shows the effect of localized trap charges on the transfer inverter stage provides some delay time, due to which the com-
characteristics of CMOS Inverter. It can be observed that there is a plete circuit starts oscillating at a particular frequency [31]. This
shift in the Voltage transfer curve of Inverter from the non- frequency of oscillation is the function of the number of stages
damaged device. This is due to the degradation of the threshold used and delay time due to each stage and is given as [32]:
voltage and drain current. The threshold voltage is decreased by 1
the inclusion of Positive trap charges and is increased by the inclu- f ¼ ð2Þ
2nT
sion of negative trap charges. Four different profiles of trap charges
have been considered. Maximum shift is observed in the case of where
Uniform profile of trap charges and a minimum shift in case of step
function profile. This shifting in Voltage transfer curve alters the n = No. of stages used
inverter’s switching voltage. Fig. 8(e) compares the change in T = Delay time due to one stage
switching voltage for four different profiles of charge carriers
under study. For uniform profile there is maximum change in
switching voltage, 0.08 V for both positive and negative charges
whereas for step profile minimum change in switching voltage,
0.06 V for positive charges and 0.04 V for negative charges is
observed. However, for Gaussian profile change in switching volt-
age is approximately 0.05 V for both positive and negative charges
and for Linearly Graded profile change in switching voltage, 0.06 V
for both positive and negative charges. As shown in Fig. 8(b), it has
been observed that device having positive trap charges switches off
at lower gate voltage as compared to the device having negative
trap charges or no trap charges. whereas device having negative
trap charges switches off at higher gate voltage in comparison to
trap free device.

3.2.2. Noise margin

Noise margin in CMOS inverter is the amount of noise it can
withstand without deteriorating the output of the circuit. Fig. 9
Fig. 11. Transient Oscillation of 3-StageRing Oscillator.
shows the impact of localized trap charges at the interface on noise

Fig. 10. DGJNT based 3-StageRing Oscillator.

 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261 259

Fig. 12. Transient Oscillation of 3-Stage Ring Oscillator for different interface charge density profile.

Fig. 11 shows the transient Oscillations of non damaged Ring Fig. 12 shows the change in frequency of Ring Oscillator by con-
Oscillator at different nodes. The same amount of delay can be sidering the positive localized trap charges at the interface. Four
observed at each node in the figure as all three inverters are iden- different profiles of trap charges have been considered. Table 2
tical. The oscillating frequency of 2.72 GHz has been obtained shows the change in the value of frequency due to different profiles
using 3 stage Ring Oscillator. of trap charges. Maximum change in frequency is observed in the
260 N. Garg et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 251–261

Fig. 12 (continued)

Table 2 Acknowledgement
Change in frequency of Ring oscillator due to different Localized charge density
profile. Authors are thankful to Science and Engineering Research
Different profile of trap Frequency of non Frequency of Change in Board, Department of Science and Technology (SERB-DST project
charges at interface degraded circuit degraded frequency ‘‘ECR/2017/000576”), Govt. of India and Shaheed Rajguru College
circuit of Applied Sciences for Women, University of Delhi for providing
Step function Profile 2.72 GHz 4.17 GHz 1.45 GHz the infrastructural support and opportunity for carrying out this
Uniform Profile 2.72 GHz 3.85 GHz 1.13 GHz work.
Linearly Graded Profile 2.72 GHz 4.10 GHz 1.38 GHz
Approximated 2.72 GHz 4 GHz 1.28 Hz
Gaussian profile
Appendix A. Supplementary material

Supplementary data to this article can be found online at

case of step function profile of trap charges. Change in frequency
https://doi.org/10.1016/j.aeue.2019.06.014.
will also have an impact on delay time due to each stage.

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