AT24C04C-1 MHZ

Atmel AT24C04C and Atmel AT24C08C
I2C-Compatible, (2-wire) Serial EEPROM

4-Kbit (512 x 8), 8-Kbit (1024 x 8)
DATASHEET
Standard Features
 Low-voltage and standard-voltage operation

 VCC = 1.7V to 5.5V
 Internally organized as 512 x 8 (4K), or 1024 x 8 (8K)
 I2C-compatible (2-wire) serial interface
 Schmitt Trigger, filtered inputs for noise suppression
 Bidirectional data transfer protocol
 1MHz (2.5V, 2.7V, 5V), 400kHz (1.7V) compatibility
 Write Protect pin for hardware data protection
 16-byte Page Write mode
 Partial Page Writes allowed
 Self-timed write cycle (5ms max)
 High-reliability
 Endurance: 1,000,000 write cycles
 Data retention: 100 years
 Green package options (Pb/Halide-free/RoHS compliant)
 8-lead PDIP, 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 5-lead SOT23,
and 8-ball VFBGA
 Die options: wafer form and tape and reel
Description
The Atmel® AT24C04C and AT24C08C provides 4096/8192 bits of Serial Electrically
Erasable and Programmable Read-Only Memory (EEPROM) organized as
512/1024 words of eight bits each. The device is optimized for use in many industrial
and commercial applications where low-power and low-voltage operation are essential.
AT24C04C/08C is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC,
8-lead TSSOP, 8-pad UDFN, 5-lead SOT23, and 8-ball VFBGA packages and is
accessed via a 2-wire serial interface.
Atmel-8787D-SEEPROM-AT24C04C,08C-Datasheet_042013
Table 1. Pin Configuration
Pin Name Function 8-lead PDIP 8-lead SOIC

NC 1 8 VCC NC 1 8 VCC
NC No Connect A1/NC 2 7 WP A1/NC 2 7 WP
A1 Address Input (4K only) A2 3 6 SCL A2 3 6 SCL
GND 4 5 SDA GND 4 5 SDA
A2 Address Input
SDA Serial Data 8-lead TSSOP 8-lead UDFN

SCL Serial Clock Input NC 1 8 VCC VCC 8 1 NC
A1/NC 2 7 WP WP 7 2 A1/NC
WP Write Protect A2 3 6 SCL SCL 6 3 A2
GND Ground GND 4 5 SDA SDA 5 4 GND
Bottom View
VCC Power Supply
5-lead SOT23 8-ball VFBGA
Note: 1. For use of 5-lead SOT23, the software
A2 and A1 bits in the device address SCL 1 5 WP VCC 8 1 NC
word must be set to zero to properly WP 7 2 A1/NC
GND 2
communicate. SCL 6 3 A2
SDA 3 4 VCC SDA 5 4 GND
Bottom View
Atmel AT24C04C/08C [DATASHEET] 2

1. Absolute Maximum Ratings
Operating Temperature ........................–55C to +125C *Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
Storage Temperature ...........................–65C to +150C damage to the device. This is a stress rating only
and functional operation of the device at these or
Voltage on any pin
any other conditions beyond those indicated in
with respect to ground .............................–1.0V to +7.0V
the operational sections of this specification is
Maximum Operating Voltage ................................. 6.25V not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
DC Output Current................................................ 5.0mA device reliability.
2. Block Diagram
VCC
GND
WP
SCL Start
Stop
SDA Logic
Serial High Voltage
Enable
Control Pump & Timing
Logic
Data Latches
Device Load
Address COMP
INC
Comparator
Row Decoder
Data Word
Read/Write ADDR/Counter
A2 EEPROM
Array
A1
Column Serial MUX

Decoder
DOUT / ACK
Logic
DIN
DOUT

3. Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device/Page Addresses (A2 and A1): The AT24C04C uses the A2 and A1 inputs for hard wire addressing allowing a
total of four 4K devices to be addressed on a single bus system. Pin 1 is a no connect and can be connected to ground
(see Section 6. “Device Addressing” on page 10). The AT24C08C only uses the A2 input for hardware addressing and a
total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be
connected to ground (see Section 6. “Device Addressing” on page 10).
Write Protect (WP): AT24C04C/08C has a Write Protect pin that provides hardware data protection. The Write Protect
pin allows normal read/write operations when connected to Ground (GND). When the Write Protect pin is connected to
VCC, the write protection feature is enabled and operates as shown in Table 3-1.
Table 3-1. Write Protect
Part of the Array Protected

WP Pin
Status Atmel AT24C04C/08C
At VCC Full array
At GND Normal read/write operations

4. Memory Organization
Atmel AT24C04C, 4K Serial EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data
word address for random word addressing.
Atmel AT24C08C, 8K Serial EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit
data word address for random word addressing.
Table 4-1. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0MHz, VCC = +1.7V to +5.5V
Symbol Test Condition Max Units Conditions
CI/O Input/Output capacitance (SDA) 8 pF VI/O = 0V
CIN Input capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 4-2. DC Characteristics

Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.7V to +5.5V
(unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.7 5.5 V
VCC2 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V Read at 100kHz 0.4 1.0 mA
ICC Supply Current VCC = 5.0V Write at 100kHz 2.0 3.0 mA
ISB1 Standby Current VCC = 1.7V VIN = VCC or VSS 1.0 μA
ISB2 Standby Current VCC = 5.5V VIN = VCC or VSS 6.0 μA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 μA
ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 μA
VIL Input Low Level(1) –0.6 VCC x 0.3 V
VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V
VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V
Note: 1. VIL min and VIH max are reference only and are not tested.

Table 4-3. AC Characteristics
Applicable over recommended operating range from TAI = –40C to +85C, VCC = +1.7V to +5.5V,
CL = 1TTL Gate and 100pF (unless otherwise noted)
1.7V 2.5V, 2.7V, 5.0V
Symbol Parameter Min Max Min Max Units
fSCL Clock Frequency, SCL 400 1000 kHz
tLOW Clock Pulse Width Low 1.2 0.4 μs
tHIGH Clock Pulse Width High 0.6 0.4 μs
tI Noise Suppression Time 100 50 ns
tAA Clock Low to Data Out Valid 0.1 0.9 0.05 0.55 μs
Time the bus must be free before a new

tBUF 1.2 0.5 μs
transmission can start.
tHD.STA Start Hold Time 0.6 0.25 μs
tSU.STA Start Setup Time 0.6 0.25 μs
tHD.DAT Data In Hold Time 0 0 μs
tSU.DAT Data In Setup Time 100 100 ns

(1)
tR Inputs Rise Time 0.3 0.3 μs
tF Inputs Fall Time(1) 300 100 ns
tSU.STO Stop Setup Time 0.6 .25 μs
tDH Data Out Hold Time 50 50 ns
tWR Write Cycle Time 5 5 ms
Endurance(1) 3.3V, +25C, Page Mode 1 Million Write Cycles
Note: 1. This parameter is ensured by characterization only.

5. Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see Figure 5-4 on page 9). Data changes during SCL high periods will indicate
a Start or Stop condition as defined below.
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede any other
command (see Figure 5-5 on page 9).
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the Stop
command will place the EEPROM in a standby power mode (see Figure 5-5 on page 9).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in eight bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Standby Mode: The Atmel AT24C04/08C features a low-power standby mode which is enabled:
 Upon power-up
 After the receipt of the Stop bit and the completion of any internal operations
2-wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1. Create a start bit condition
2. Clock nine cycles
3. Create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps have been completed.
Figure 5-1. Software Reset
Dummy Clock Cycles
SCL 1 2 3 8 9
Start Start Stop

Bit Bit Bit
SDA

Figure 5-2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O

tHIGH
tF tR
tLOW tLOW
SCL
tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO
SDA IN
tAA tDH tBUF
SDA OUT
Figure 5-3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA 8th bit ACK
WORDn
(1)
tWR
Stop Start
Condition Condition
Notes: 1. The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal
clear/write cycle.

Figure 5-4. Data Validity
SDA
SCL
Data Stable Data Stable
Data
Change
Figure 5-5. Start and Stop Definition
SDA
SCL
Start Stop
Figure 5-6. Output Acknowledge
SCL 1 8 9
DATA IN
DATA OUT
Start Acknowledge

6. Device Addressing
Standard EEPROM Access: The 4K and 8K EEPROM device requires an 8-bit device address word following a start
condition to enable the chip for a read or write operation. The device address word consists of a mandatory “1010” (0xA)
sequence for the first four Most Significant Bits (MSB) as shown in Figure 8-1 on page 11. This is common to all the
EEPROM devices.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The
two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2
address bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to
a standby state.
For the SOT23 package offering, the 4K EEPROM software A2 and A1 bits in the device address word must be set to
zero to properly communicate. The 8K EEPROM software A2 bit in the device address word must be set to zero to
properly communicate.
7. Write Operations
Byte Write: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such
as a microcontroller, must terminate the write sequence with a Stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see Figure 8-2 on page 11).
Page Write: The 4K and 8K EEPROM devices are capable of a 16-byte Page Write.
A Page Write is initiated in the same way as a Byte Write, but the microcontroller does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the Page Write sequence with a Stop condition (see Figure 8-3 on page 12).
The data word address lower four bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than
16 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled,
Acknowledge Polling can be initiated. This involves sending a Start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.

8. Read Operations
Read operations are initiated in the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three read operations: Current Address Read, Random Address Read, and
Sequential Read.
Current Address Read: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first
page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input zero but does
generate a following stop condition (see Figure 8-4 on page 12).
Random Read: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a Current Address Read by sending a device address
with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word.
The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-5 on page
12).
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After
the microcontroller receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an
Acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the Sequential Read will continue. The
Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a
following Stop condition (see Figure 8-6 on page 12).
Figure 8-1. Device Address
Density Access Area Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
4K EEPROM 1 0 1 0 A2 A1 P0 R/W
8K EEPROM 1 0 1 0 A2 P1 P0 R/W
MSB LSB
Figure 8-2. Byte Write
S W
T R S
A I T
R Device T O
T Address E Word Address Data P
SDA LINE
M R A A A
S / C C C
B W K K K

Figure 8-3. Page Write
S W
T R S
A I T
R Device T Word O
T Address E Address (n) Data (n) Data (n + 1) Data (n + x) P
SDA LINE
M R A A A A A
S / C C C C C
B W K K K K K
Figure 8-4. Current Address Read
S
T R S
A E T
R Device A O
T Address D Data P
SDA LINE
M R A N
S / C O
B W K
A
C
K
Figure 8-5. Random Read
S W S
T R T R S
A I A E T
R Device T Word R Device A O
T Address E Address (n) T Address D Data (n) P
SDA LINE
M R A A A N
S / C C C O
B W K K K
A
C
Dummy Write K
Figure 8-6. Sequential Read
R S
E T
Device A O
Address D Data (n) Data (n + 1) Data (n + 2) Data (n + x) P
SDA LINE
R A A A A N
/ C C C C O
WK K K K
A
C
K

9. Ordering Code Detail
AT 2 4 C 0 4 C - S S H M - B
Atmel Designator Shipping Carrier Option

B or blank = Bulk (tubes)
T = Tape and reel
Product Family Operating Voltage
24C = Standard Serial EEPROM M = 1.7V to 5.5V
Package Device Grade or

Wafer/Die Thickness
Device Density H = Green, NiPdAu lead finish,
04 = 4K Industrial temperature range
08 = 8K (-40˚C to +85˚C)
U = Green, matte Sn lead finish,
Industrial temperature range
Device Revision (-40˚C to +85˚C)
11 = 11mil wafer thickness
Package Option
P = PDIP
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
ST = SOT23
C = VFBGA
WWU = Wafer unsawn

10. Product Markings
AT24C04C and AT24C08C: Package Marking Information

8-lead PDIP 8-lead SOIC 8-lead TSSOP
ATMLUYWW ATHYWW
###M @ ATMLHYWW ###M @
###M @
AAAAAAAA AAAAAAAA AAAAAAA
8-lead UDFN 5-lead SOT-23 8-ball VFBGA

2.0 x 3.0 mm Body 1.5 x 2.0 mm Body
###MU
### Top Mark
HM@ ###U
YMXX
YXX
YMXX Bottom Mark PIN 1
Note 1: designates pin 1

Note 2: Package drawings are not to scale
Catalog Number Truncation

AT24C04C Truncation Code ###: 04C
AT24C08C Truncation Code ###: 08C
Date Codes Voltages
Y = Year M = Month WW = Work Week of Assembly M: 1.7V min
2: 2012 6: 2016 A: January 02: Week 2
3: 2013 7: 2017 B: February 04: Week 4
4: 2014 8: 2018 ... ...
5: 2015 9: 2019 L: December 52: Week 52
Country of Assembly Lot Number Grade/Lead Finish Material
@ = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/Matte Tin
H: Industrial/NiPdAu
Trace Code Atmel Truncation

XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel
Example: AA, AB.... YZ, ZZ ATM: Atmel
ATML: Atmel
5/01/12
TITLE DRAWING NO. REV.
24C04-08CSM, AT24C04C and AT24C08C Package

Package Mark Contact: 24C04-08CSM B
Marking Information
DL-CSO-Assy_eng@atmel.com

11. Ordering Codes
11.1 Atmel AT24C04C Ordering Information
Ordering Code Lead Finish Package Voltage Operation Range
Bulk Form Only

AT24C04C-PUM 8P3
(Lead-free/Halogen-free)
AT24C04C-SSHM-B(1)
8S1
(2)
AT24C04C-SSHM-T
NiPdAu
AT24C04C-XHM-B(1)
8X
Industrial Temperature
AT24C04C-XHM-T(2) 1.7V to 5.5V
(–40C to 85C)
AT24C04C-MAHM-T(2) 8MA2
AT24C04C-STUM-T(2) (Lead-free/Halogen-free) 5TS1
AT24C04C-CUM-T(2) (Lead-free/Halogen-free) 8U3-1
AT24C04C-WWU11M(3) — Wafer Sale
Notes: 1. B = Bulk
2. T = Tape and reel
 SOIC = 4K per reel
 TSSOP, UDFN, SOT23, and VFBGA = 5K per reel
3. For Wafer sales, please contact Atmel Sales.
Package Type
8P3 8-lead, 0.300" wide, Plastic Dual Inline (PDIP)
8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN)
5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23)
8U3-1 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Die Ball Grid Array (VFBGA)

11.2 Atmel AT24C08C Ordering Information
Ordering Code Lead Finish Package Voltage Operation Range
Bulk Form Only

AT24C08C-PUM 8P3
AT24C08C-SSHM-B(1)
8S1
(2)
AT24C08C-SSHM-T
NiPdAu
AT24C08C-XHM-B(1)
8X
Industrial Temperature
AT24C08C-XHM-T(2) 1.7V to 5.5V
(–40C to 85C)
AT24C08C-MAHM-T(2) 8MA2
AT24C08C-STUM-T(2) (Lead-free/Halogen-free) 5TS1
AT24C08C-CUM-T(2) (Lead-free/Halogen-free) 8U3-1
AT24C08C-WWU11M(3) — Wafer Sale
Notes: 1. B = Bulk
2. T = Tape and reel
 SOIC = 4K per reel
 TSSOP, UDFN, SOT23, and VFBGA = 5K per reel
3. For Wafer sales, please contact Atmel Sales.
Package Type
8P3 8-lead, 0.300" wide, Plastic Dual Inline (PDIP)
8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN)
5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23)
8U3-1 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Die Ball Grid Array (VFBGA)

12. Packaging Information
8P3 — 8-lead PDIP
1
E
E1
Top View c
eA
End View
COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
06/21/11
TITLE GPC DRAWING NO. REV.
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
Package Drawing Contact: PTC 8P3 D
In-line Package (PDIP)
packagedrawings@atmel.com

12.1 8S1 — 8-lead JEDEC SOIC
E E1
N L
Ø
TOP VIEW
END VIEW
e b
A COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE

A1
A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
D
E1 3.81 – 3.99
E 5.79 – 6.20
SIDE VIEW e 1.27 BSC
Notes: This drawing is for general information only. L 0.40 – 1.27
Refer to JEDEC Drawing MS-012, Variation AA Ø 0° – 8°
for proper dimensions, tolerances, datums, etc.
6/22/11
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Package Drawing Contact: SWB 8S1 G
Small Outline (JEDEC SOIC)

12.2 8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1 E
L1
N
L
Top View End View
A
b
A1
COMMON DIMENSIONS
e A2
D
A - - 1.20
Side View A1 0.05 - 0.15
Notes: 1. This drawing is for general information only. A2 0.80 1.00 1.05
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc. D 2.90 3.00 3.10 2, 5
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
E 6.40 BSC
0.15mm (0.006in) per side. E1 4.30 4.40 4.50 3, 5
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm b 0.19 – 0.30 4
(0.010in) per side. e 0.65 BSC
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess L 0.45 0.60 0.75
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
L1 1.00 REF
space between protrusion and adjacent lead is 0.07mm. C 0.09 - 0.20
5. Dimension D and E1 to be determined at Datum Plane H.
6/22/11
8X, 8-lead 4.4mm Body, Plastic Thin
Package Drawing Contact: TNR 8X D
Shrink Small Outline Package (TSSOP)

12.3 8MA2 — 8-pad UDFN
1 8
Pin 1 ID
2 7
D
3 6
4 5
C
A2 A
A1
E2
COMMON DIMENSIONS
b (8x) (Unit of Measure = mm)

8 1 D 2.00 BSC
E 3.00 BSC
7 2
D2 1.40 1.50 1.60
Pin#1 ID D2
E2 1.20 1.30 1.40
6 3
A 0.50 0.55 0.60
5 4 A1 0.0 0.02 0.05
e (6x) A2 – – 0.55
C 0.152 REF
L (8x) K
L 0.30 0.35 0.40
e 0.50 BSC
b 0.18 0.25 0.30 3
K 0.20 – –
7/15/11
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Package Drawing Contact: Enhanced Plastic Ultra Thin Dual Flat No YNZ 8MA2 B
packagedrawings@atmel.com Lead Package (UDFN)

12.4 5TS1 — 5-lead SOT23
e1
5 4 C
E1 E C
L
L1
1 2 3
TOP VIEW END VIEW
A2 A
SEATING
PLANE e A1
D
SIDE VIEW
COMMON DIMENSIONS
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,
protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does SYMBOL MIN NOM MAX NOTE
not include interlead flash or protrusion. Interlead flash or protrusion shall not
exceed 0.15 mm per side. A - - 1.00
2. The package top may be smaller than the package bottom. Dimensions D and E1 A1 0.00 - 0.10
are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch A2 0.70 0.90 1.00
between the top and bottom of the plastic body. c 0.08 - 0.20 3
3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15
mm from the lead tip. D 2.90 BSC 1,2
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion E 2.80 BSC 1,2
shall be 0.08 mm total in excess of the "b" dimension at maximum material
condition. The dambar cannot be located on the lower radius of the foot. Minimum E1 1.60 BSC 1,2
space between protrusion and an adjacent lead shall not be less than 0.07 mm.
L1 0.60 REF
e 0.95 BSC
e1 1.90 BSC
This drawing is for general information only. Refer to JEDEC
Drawing MO-193, Variation AB for additional information. b 0.30 - 0.50 3,4
5/31/12
5TS1, 5-lead 1.60mm Body, Plastic Thin
Package Drawing Contact: Shrink Small Outline Package (Shrink SOT) TSZ 5TS1 D

12.5 8U3-1 — 8-ball VFBGA
D
2. b
PIN 1 BALL PAD CORNER A1

A2
TOP VIEW A
SIDE VIEW
PIN 1 BALL PAD CORNER
1 2 3 4
(d1)
8 7 6 5
e COMMON DIMENSIONS
(Unit of Measure - mm)
(e1)
BOTTOM VIEW A 0.73 0.79 0.85

8 SOLDER BALLS A1 0.09 0.14 0.19
A2 0.40 0.45 0.50
Notes: b 0.20 0.25 0.30 2
1. This drawing is for general information only. D 1.50 BSC
E 2.0 BSC
2. Dimension ‘b’ is measured at maximum solder ball diameter. e 0.50 BSC
e1 0.25 REF
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
d 1.00 BSC
d1 0.25 REF
3/27/12
8U3-1, 8-ball, 1.50mm x 2.00mm body,
Package Drawing Contact: GXU 8U3-1 E
0.50mm pitch, VFBGA Package

13. Revision History
Doc. Rev. Date Comments
In the Page Write description, correct from eight to 16 data words.

8787D 04/2013
Update ordering code table, footers, and disclaimer page.
Correct ordering codes:

- AT24C04C-WWU11, Die Sale to AT24C04C-WWU11M, Wafer Sale.
8787C 07/2012 - AT24C08C-WWU11, Die Sale to AT24C08C-WWU11M, Wafer Sale.
Remove WDT from ordering code detail.
Update Atmel logos and disclaimer page.
Remove preliminary status.

Remove A0 signal from the block diagram.
ISB2 parameter measured at 5.5V.
In AC Characteristics table, changed 1.7V, 2.5V, 2.7V to 1.7 and 5.0V to 2.5V, 2.7V, 5.0V.
Increase tI maximum value from 50ns to 100ns.
8787B 05/2012
Endurance parameter is studied at 3.3V, to +25C, Page mode.
Remove Serial Number Read from read operations.
Update product markings.
Update 8X and 8U3-1 package drawings.
Update template.
8787A 10/2011 Initial document release.

X X X X
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-8787D-SEEPROM-AT24C04C,08C-Datasheet_042013
Atmel®, Atmel logo and combinations thereof, RapidS™, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel
Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES
FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information
contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,
authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.
Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are
not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

AT24C04C-1 MHZ

Uploaded by

Copyright:

Available Formats

AT24C04C-1 MHZ

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

AT24C04C-1 MHZ

Uploaded by

Copyright:

Available Formats

Atmel AT24C04C and Atmel AT24C08C

I2C-Compatible, (2-wire) Serial EEPROM

 Low-voltage and standard-voltage operation

Pin Name Function 8-lead PDIP 8-lead SOIC

SDA Serial Data 8-lead TSSOP 8-lead UDFN

Atmel AT24C04C/08C [DATASHEET] 2

Column Serial MUX

Atmel AT24C04C/08C [DATASHEET] 3

Table 3-1. Write Protect

Part of the Array Protected

At VCC Full array

At GND Normal read/write operations

Atmel AT24C04C/08C [DATASHEET] 4

Table 4-1. Pin Capacitance(1)

Symbol Test Condition Max Units Conditions

CI/O Input/Output capacitance (SDA) 8 pF VI/O = 0V

CIN Input capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 4-2. DC Characteristics

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.7 5.5 V

VCC2 Supply Voltage 4.5 5.5 V

ICC Supply Current VCC = 5.0V Read at 100kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V Write at 100kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 1.7V VIN = VCC or VSS 1.0 μA

ISB2 Standby Current VCC = 5.5V VIN = VCC or VSS 6.0 μA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 μA

ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 μA

VIL Input Low Level(1) –0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V

VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V

Atmel AT24C04C/08C [DATASHEET] 5

1.7V 2.5V, 2.7V, 5.0V

Symbol Parameter Min Max Min Max Units

fSCL Clock Frequency, SCL 400 1000 kHz

tLOW Clock Pulse Width Low 1.2 0.4 μs

tHIGH Clock Pulse Width High 0.6 0.4 μs

tI Noise Suppression Time 100 50 ns

Time the bus must be free before a new

tHD.STA Start Hold Time 0.6 0.25 μs

tSU.STA Start Setup Time 0.6 0.25 μs

tHD.DAT Data In Hold Time 0 0 μs

tSU.DAT Data In Setup Time 100 100 ns

tF Inputs Fall Time(1) 300 100 ns

tSU.STO Stop Setup Time 0.6 .25 μs

tDH Data Out Hold Time 50 50 ns

tWR Write Cycle Time 5 5 ms

Endurance(1) 3.3V, +25C, Page Mode 1 Million Write Cycles

Note: 1. This parameter is ensured by characterization only.

Atmel AT24C04C/08C [DATASHEET] 6

Figure 5-1. Software Reset

Dummy Clock Cycles

Start Start Stop

Atmel AT24C04C/08C [DATASHEET] 7

SCL: Serial Clock, SDA: Serial Data I/O

tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO

tAA tDH tBUF

Figure 5-3. Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O