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29 views2 pages

Dsd pyq

Uploaded by

sauravrajsingh02
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Seat No.: ________ Enrolment No.

___________

GUJARAT TECHNOLOGICAL UNIVERSITY


BE - SEMESTER– III (NEW) EXAMINATION – SUMMER 2022
Subject Code:3131102 Date:15-07-2022
Subject Name:Digital System Design
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks
Q.1 (a) Why Nand gate is called universal gate? Implement of AND and OR 03
logic using NAND gate.
(b) Convert the following numbers to decimal and to binary. 04
a. 44335
b. 56547
(c) Distinguish between combinational and sequential logic circuit? 07

Q.2 (a) Write a short note on full adder. 03


(b) Obtain the minimal expression for 04
f= m (1,2,4,6,7) and implement using universal gate.
(c) Write a short note on JK flip flop. 07
OR
(c) Draw and explain 4-bit Magnitude comparator. 07

Q.3 (a) What is master Slave flip flop? Explain with the help of diagram. 03
(b) Draw and explain the excitation table and state diagram of D Flip 04
flop.
(c) Write a short note on ripple counter. 07
OR
Q.3 (a) What is race around condition in flip flop? 03
(b) Give comparison between Moore and Mealy state machine. 04
(c) Obtain the reduced state table and reduced state diagram for the 07
sequential machine whose state diagram is given below.

1
Q.4 (a) Define Finite State machine. 03
(b) Differentiate between asynchronous and synchronous sequential 04
circuit
(c) With the help of neat diagram explain the working of two input TTL 07
NAND gate.
OR
Q.4 (a) Draw neat diagram of universal shift register. 03
(b) Write a short note on bidirectional shift register. 04
(c) Define Following terms with respect to logic families. 07
Propagation Delay, Fan in, Fan out, Power dissipation

Q.5 (a) What are various modeling styles supported in Verilog? Explain 03
behavioral style of modelling.
(b) Determine the resolution of 6-bit DAC and 12-bit DAC. 04
(c) Write a short note on Programmable array logic. 07
OR
Q.5 (a) Explain Structural Modelling Style in Verilog with suitable example. 03
(b) Explain D to A conversion using R2R ladder 04
(c) Explain PLD. What are the advantages of PLD over fixed function 07
ICs?

********

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