UNIT-2 Instruction Set

Architecture
Basic Computer Introduction :
• Every different processor type has its own design (different registers, buses,
microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• However, to understand how processors work, we will start with a simplified processor
model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic Computer
• We will use this to introduce processor organization and the relationship of the RTL
model to the higher level computer processor
THE BASIC COMPUTER

• The Basic Computer has two components, a processor and

memory
• The memory has 4096 words in it
• 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
CPU RAM
• 4096 X 16 Bits 0

15 0

4095

16 bit data
 INSTRUCTIONS :
• Program
• A sequence of (machine) instructions
• (Machine) Instruction
• A group of bits that tell the computer to perform a specific operation (a sequence
of micro-operation)
• The instructions of a program, along with any needed data are
stored in memory.
• The CPU reads the next instruction from memory.
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into
the sequence of microoperations necessary to implement it.
 Instruction Code :
An instruction code is a group of bits that instruct the computer to perform a specific
operation.

Opcode Operands
Operation Code :

The operation code of an instruction is a group of bits that define such operations as add, subtract,
multiply, shift, and complement.

The number of bits required for the operation code of an instruction depends on the total number of
operations available in the computer. The operation code must consist of at least n bits for a given 2n (or
less) distinct operations.

Accumulator (AC)
Computers that have a single-processor register usually assign to it the name accumulator (AC) accumulator
and label it AC.

The operation is performed with the memory operand and the content of AC.
Stored Program Organization :
 INSTRUCTION FORMAT
• A computer instruction is often divided into two parts

1. An opcode (Operation Code) that specifies the operation for that instruction
2. An address that specifies the registers and/or locations in memory to use for that operation

• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12
bit to specify which memory address this instruction will use.
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3
bits for the instruction’s opcode
Instruction Format

15 14 12 11 0

I Opcode Address

Addressing
mode
 ADDRESSING MODES :
• The address field of an instruction can represent either
• Direct address (0): the address in memory of the data to use (the address of the operand), or
• Indirect address (1): the address in memory of the address in memory of the data to use
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

• Effective Address (EA)

• The address, that can be directly used without modification to access an operand for a computation-
type instruction, or as the target address for a branch-type instruction
Micro-operations:
• The operations executed on values stored in registers.
• CPU can not perform one operation in single steps.

• Transfer the contents from one register R2 to another register R1.

• Symbolic notation to describe the micro-operations is called Register

Transfer Language (RTL).
R1  R2
 Register Transfer Language (RTL) :
• Definition: The symbolic notation used to describe the microoperation transfers among
registers is called a register transfer language.

• The term "register transfer" implies the availability of hardware logic circuits that can
perform a stated microoperation and transfer the result of the operation to the same or
another register.
• The word "language" is borrowed from programmers, who apply this term to
programming languages.
• A register transfer language is a system for expressing in symbolic form the
microoperation sequences among the registers of a digital module.

• It is a convenient tool for describing the internal organization of digital computers in

concise and precise manner.
• It can also be used to facilitate the design process of digital systems.
• Information transfer from one register to another is designated in symbolic form by means
of a replacement operator.

• The statement below denotes a transfer of the content of register R1 into register R2.
R2 ← R1

Eg. Copy content of program counter into memory address register.

MAR  PC

• A statement that specifies a register transfer implies that circuits are available from the
outputs of the destination register has a parallel load capability.

• Every statement written in a register transfer notation implies a hardware construction for
implementing the transfer.
Register Transfer in detail with block diagram and timing diagram :
• Definition: Information transfer from one register to another is designated in symbolic form by
means of a replacement operator is known as Register Transfer.
R2 ← R1
• Denotes a transfer of the content of register R1 into register R2.
• Computer registers are designated by capital letters (sometimes followed by numerals) to denote
the function of the register.
For example:
• The most common way to represent a register is by a rectangular box with the name of the register inside,
as shown in figure.
• Bits 0 through 7 are assigned the symbol L (for low byte) and bits 8 through 15 are assigned the symbol H
(for high byte). The name of the 16-bit register is PC. The symbol PC(0-7) or PC(L) refers to the low-order
byte and PC(8-15) or PC(H) to the high-order byte.
• The statement that specifies a register transfer implies that circuits are available from the outputs of the
source register to the inputs of the destination register and that the destination register has a parallel load
capability.

Register Transfer with control function:

• If we want the transfer to occur only under a predetermined control condition. This can be
shown by means of an if-then statement.
If (P = 1) then (R2 R1)
where P is a control signal.
• It is sometimes convenient to separate the control variables from the register transfer operation
control function by specifying a control function.
• A control function is a Boolean variable that is equal to 1 or 0. The control function is included in
the statement as follows:
P: R2 R1
• The n outputs of register R1 are connected to the n inputs of register R2. The letter n will be used to
indicate any number of bits for the register.
• In the timing diagram, P is activated in the control section by the rising edge of a clock pulse at time t.
• The next positive transition of the clock at time t + 1 finds the load input active and the data inputs of
R2 are then loaded into the register in parallel.
• P may go back to 0 at time t + 1; otherwise, the transfer will occur with every clock pulse transition
while P remains active.
• A comma is used to separate two or more operations that are executed at the
same time.
• The statement below, denotes an operation that exchanges the contents of two
registers during one common clock pulse provided that T = 1.
T: R2 R1, PC  PC+1
• This simultaneous operation is possible with registers that have edge-triggered
flipflops.
Ans : 26

Ans : 24
Ans : 17
Common Bus System :
• A typical digital computer has many registers, and paths must be provided to
transfer information from one register to another.
• The number of wires will be excessive if separate lines are used between each
register and all other registers in the system.
• A more efficient scheme for transferring information between registers in a
multiple register configuration is a common bus system.
• A bus structure consists of a set of common lines, one for each bit of a register,
through which binary information is transferred one at a time.

• Control signals determine which register is selected by the bus during each
particular register transfer.
• One way of constructing a common bus system is with multiplexers.
• The multiplexers select the source register whose binary information is then placed on
the bus.
• The construction of a bus system for four registers is shown in figure below.
• Each register has four bits, numbered 0 through 3.
• The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and
two selection inputs, S1 and S0.
• The diagram shows that the bits in the same significant position in each register are
connected to the data inputs of one multiplexer to form one line of the bus.
• The two selection lines S1 and S0 are connected to the selection inputs of all four
multiplexers.
• The selection lines choose the four bits of one register and transfer them into the four line
common bus.
• When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the
outputs that form the bus.
• This causes the bus lines to receive the content of register A since the outputs of this
register are connected to the 0 data inputs of the multiplexers.

• Similarly, register B is selected if S1S0 = 01, and so on.

• Table shows the register that is selected by the bus for each of the four possible binary
values of the selection lines.

• In general, a bus system will multiplex k registers of n bits each to produce an n-line
common bus.
• The number of multiplexers needed to construct the bus is equal to n, the number of
bits in each register.
• The size of each multiplexer must be K x 1 since it multiplexes K data lines.

For example, a common bus for eight registers of 16 bits each requires 16 multiplexers, one
for each line in the bus. Each multiplexer must have eight data input lines and three
selection lines to multiplex one significant bit in the eight registers.
A digital computer has a common bus system for 16 registers of 32 bits each.
(i) How many selection input are there in each multiplexer?
(ii) What size of multiplexers is needed?
(iii) How many multiplexers are there in a bus?

(i) How many selection input are there in each multiplexer?

2n=No. of Registers; n=selection input of multiplexer
2n=16; here n=4
Therefore 4 selection input lines should be there in each multiplexer.
(ii) What size of multiplexers is needed?
size of multiplexers= Total number of register X 1
= 16 X 1
Multiplexer of 16 x 1 size is needed to design the above defined common bus.
(iii) How many multiplexers are there in a bus?
No. of multiplexers = bits of register
= 32
32 multiplexers are needed in a bus.
 Registers of basic computer :
• It is necessary to provide a register in the control unit for storing the instruction code after it is read from
memory.
• The computer needs processor registers for manipulating data and a register for holding a memory address.
• These requirements dictate the register configuration shown in Figure

Figure : Basic Computer Register and Memory

• The data register (DR) holds the operand read from memory.
• The accumulator (AC) register is a general purpose processing register.
• The instruction read from memory is placed in the instruction register (IR).

• The temporary register (TR) is used for holding temporary data during the processing.
• The memory address register (AR) has 12 bits.
• The program counter (PC) also has 12 bits and it holds the address of the next
instruction to be read from memory after the current instruction is executed.

• Instruction words are read and executed in sequence unless a branch instruction is
encountered. A branch instruction calls for a transfer to a nonconsecutive instruction
in the program.

• Two registers are used for input and output. The input register (INPR) receives an 8-bit
character from an input device. The output register (OUTR) holds an 8-bit character for an
output device.
Common Bus System for basic computer register :
• The basic computer has eight registers, a memory unit and a control unit.
• Paths must be provided to transfer information from one register to another and
between memory and register.

• The number of wires will be excessive if connections are between the outputs of
each register and the inputs of the other registers. An efficient scheme for
transferring information in a system with many register is to use a common bus.

• The connection of the registers and memory of the basic computer to a common
bus system is shown in figure.
• The outputs of seven registers and memory are connected to the common bus. The
specific output that is selected for the bus lines at any given time is determined from the
binary value of the selection variables S2, S1, and S0.
• The number along each output shows the decimal equivalent of the required binary
selection.

• The particular register whose LD (load) input is enabled receives the data from the bus
during the next clock pulse transition. The memory receives the contents of the bus when
its write input is activated. The memory places its 16-bit output onto the bus when the read
input is activated and S2 S1 S0 = 1 1 1.
• Four registers, DR, AC, IR, and TR have 16 bits each.
• Two registers, AR and PC, have 12 bits each since they hold a memory address.

• When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to 0’s. When AR and PC receive information from the bus, only
the 12 least significant bits are transferred into the register.
• The input register INPR and the output register OUTR have 8 bits each and communicate
with the eight least significant bits in the bus.
• INPR is connected to provide information to the bus but OUTR can only receive
information from the bus.
• Five registers have three control inputs: LD (load), INR (increment), and CLR (clear). Two
registers have only a LD input.
• AR must always be used to specify a memory address; therefore memory address is
connected to AR.

• The 16 inputs of AC come from an adder and logic circuit. This circuit has three sets of
inputs.
1. Set of 16-bit inputs come from the outputs of AC.
2. Set of 16-bits come from the data register DR.
3. Set of 8-bit inputs come from the input register INPR.

• The result of an addition is transferred to AC and the end carry-out of the addition is
transferred to flip-flop E (extended AC bit).
• The clock transition at the end of the cycle transfers the content of the bus into the
designated destination register and the output of the adder and logic circuit into AC.
• Three control lines, S2, S1, and S0 control which register the bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory
 INSTRUCTION FORMAT
• A computer instruction is often divided into two parts

1. An opcode (Operation Code) that specifies the operation for that instruction
2. An address that specifies the registers and/or locations in memory to use for that operation

• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12
bit to specify which memory address this instruction will use.
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3
bits for the instruction’s opcode
Instruction Format

15 14 12 11 0

I Opcode Address

Addressing
mode
 ADDRESSING MODES :
• The address field of an instruction can represent either
• Direct address: the address in memory of the data to use (the address of the operand), or
• Indirect address: the address in memory of the address in memory of the data to use
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

• Effective Address (EA)

• The address, that can be directly used without modification to access an operand for a computation-
type instruction, or as the target address for a branch-type instruction
Direct address :

Occurs When the Operand Part Contains the Address of

Needed Data.

1. Address part of IR is placed on the bus and loaded

back into the AR

2. Address is selected in memory and its Data placed on

the bus to be loaded into the Data Register to be used for
requested instructions

34
Direct address

35
Indirect address :

Occurs When the Operand Contains the Address of the Address

of Needed Data.

1. Address part of IR is placed on the bus and loaded back

into the AR

2. Address is selected in memory and placed on the bus to be

loaded Back into the AR

3. New Address is selected in memory and placed on the bus

to be loaded into the DR to use later

36
Indirect address

37
Effective address:
• Effective address: Address where an operand is physically located

Effective address: 457 Effective address: 1350

38
 Direct and Indirect addressing example

Addressing
Mode

39
 Addressing Mode :
• It specifies how & from where the operands are obtained for instruction.

Instruction Field Format

Opcode Address (Operand)

Opcode : The operation field of an instruction specifies the operation to be performed.

• This operation must be executed on some data stored in computer registers or memory words.
• The way the operands are select during program execution is dependent on addressing mode of the
instruction.

Benefits of Addressing Mode :

• To reduce the number of bits of the instruction
• To give programming versatility to the user by providing such facilities as pointers to memory, counters for
loop control, indexing of data, & program relocation.

Opcode Mode Address (Operand)

Addressing Mode :

1. Implied Mode (Implicit Mode)

2. Immediate Mode (1 to 6)Non-computable Mode
3. Direct address mode (No any computation required)
4. Indirect address mode
5. Register mode / Register Direct mode
6. Register indirect mode
7. Autoincrement or Autodecrement mode
8. Indexed / Index Register mode (7 to 10) Computable Mode
9. PC- Relative address mode (computation required)
10.Base Register address mode
1. Implied Mode (Implicit Mode) :

• The opcode definition itself defines the operand.

• Operand is specified implicitly in the definition of instruction.
• Used for zero address and one address instructions.

• INCA – Increment Accumulator : AC  AC + 1

• CMA – Complement Accumulator
(For special register, not provide address field to CPU)

Opcode Address Opcode Mode Address

2. Immediate Mode:

• The address field of instruction specifies the operand value.

• Operand is specified in the instruction itself.
• Instructions has an operand field rather than an address field.
• Useful for initializing registers to a constant value.

Opcode Mode Address (Operand)

immediate Operand value

E.g. MVI R1, 05H

instruction move immediate number 05H to R1 register.
 3. Direct Addressing Mode : (Absolute Addressing Mode)
• The address field of instruction specifies the effective address.
• Effective address (EA) is the physical memory location where operand
is stored.
• Actual address is given in the instruction.
• Use to access variable.

Opcode Mode Address

LOAD R1, 100 Load the content of memory address 100 to register R1. E.g. ADD 457
 4. Indirect Addressing Mode :
• The address field of instruction specifies the address of effective
address.
• Mode is used to implement pointer.
• 2 times memory access required.

printf(“………”,*p);

EA = 800

EA = M [x]
5. Register Mode: (Register Direct Mode)
• The address field of instruction specifies a register which holds operand.
• Operand is present in the register.
• Register number is written in instruction.
• One register access required to fetch operand.

• ADD R1 R2
R1  R1 + R2

Opcode Mode Address ()

• E.g. MOV AX,BX
move value from BX to AX register
Register No
 6. Register Indirect Mode :
• The address field of instruction specifies the register
which holds effective address.
• Register contains address of operand rather than operands itself.
• Used to shorten the instruction length.

1 register + 1 memory access required to get

Memory operand.

E.g. MOV [R1], R2

value of R2 is moved to the memory location
specified in R1.
ADD R1,(R2) : R1  R1 + M[(R2)]
Assume a system with 4GB main memory & CPU has 64 general purpose registers.

MM address = 32 bit
Register references = 6 bit
 7. Autoincrement or Autodecrement Mode :
• Variant of register indirect mode.
• The content of register is automatically incremented or decremented to access
the sequential data (for same type operation).
• Used to access table of content (array) sequentially.
• Content of register (effective address) is Automatically increment or decrement.

for (i=o; i>30; i++)

• Compiler not generate different 30
{ instruction for this for loop.
some operation on A[i];
• Just increment/ decrement register value to
}
access sequentially data from memory.

Opcode Mode Address

Auto increment → post increment
Auto decrement → pre decrement
 8. Indexed Addressing Mode : (Index Register Mode)
• Access the particular element of array.
• Use to access or implement array efficiently.
• Multiple register required to implement.
• Any element can be accessed without change in instruction.
Opcode Address
BA = 100

100 101 102 103 104

EA = Base + Indexed Register value

= 100 +4 = 104
CPU want to access A[3] element.

What is the effective address of element A[3] ?

Loc( A[3]) = Base add. + size (data type) * 3 (Index of Array element)
Loc( A[3]) = Base add. + W * 3 (W= size of each element)

Loc( A[i]) = Base add. + W * I (ith element)

Compiler will generate instruction

Index register = W * I

EA = Base + Indexed Register value

One time access memory.

This mode does not support

relocation.

Because of relocation the

base address should be
updated in instruction.
9. PC-Relative Addressing Mode :
• PC value added in address field value(offset) of instruction to get
effective address.
• This mode is used for branch instruction.
• It is used for intra-segment branching. Target add. = PC + offset (Displacement)
Branch instruction :
• Assume, CPU is executing instruction I2.

• PC= 202

• After decoding of instruction CPU known that I2 is branch instruction.

• Consider I2 is conditional branch instruction.

True False

Branch Taken Branch Not Taken (Next instruction in sequence

I3 is executed)
Target instruction executed
PC = 207 (target address) No change in PC = 202

• If condition is true → I8 is target instruction.

• It’s (I8 instruction) address is known as target address.

• If unconditional branch instruction then always CPU update PC value by

Target address.
• Now to find target address CPU will find how many number location
(instruction) want to skip.

Target add. = PC + Relative No. of location to skip (offset)

Target add. = PC + offset (Displacement)
Target add. = 202 + 5 = 207

For forward jumping → offset value positive

backward jumping → offset value negative
• How Branch instruction executed:

• Before fetch of I2 PC= 201

• After fetch of I2 PC= 202

• Decode → CPU check instr. It’s a branch instruction.

• EA calculation → EA = 202 + 5 = 207

• Execution → CPU check the condition & update PC value if condition

is true.
 10. Base Register Addressing Mode :
• Base register value added in address field value (offset) of instruction
to get effective address.
• Used in program relocation.
• It is used for inter-segment branching.
• Main memory size limited – So process swap in & swap out frequently
• Change the location of process in main memory
 Target add. = Base register value + address of instruction

Target add. = PC + offset (Displacement)

PC-relative mode & Base Register mode are support relocation. (Not required change in instruction code)
Example:
Questions:

250
302+250= 552
200
1. Target add. = PC + offset
450 = 301 + offset
offset = 149

2. Before fetch – 300

After fetch – 301
After Execution - 450
 Instruction Set :
• Instruction : A group of bits which instructs computer to perform some
operation.
Instruction Format
Opcode Operands info.

• Ex – A CPU has 8 –bits instruction. (Assume 3 –bits opcode)

Opcode - 3 Operands - 5
Instruction – 8 bits

• Maximum opcode – 23 =8
• Maximum 8 distinct instruction can be supported by CPU.

• ISA (instruction set architecture) :

• Collections of all the instruction CPU supports.
BASIC COMPUTER INSTRUCTIONS :

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
 BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC Memory-Reference Instructions (OP-code = 000 ~ 110)
LDA 2xxx Axxx Load AC from memory 15 14 12 11 0
STA 3xxx Bxxx Store content of AC into memory I Opcode Address
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E Register-Reference Instructions (OP-code = 111, I = 0)
CIR 7080 Circulate right AC and E 15 12 11 0
CIL 7040 Circulate left AC and E
0 1 1 1 Register operation
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC Input-Output Instructions (OP-code =111, I = 1)
SKI F200 Skip on input flag
SKO F100 Skip on output flag 15 12 11 0
ION F080 Interrupt on 1 1 1 1 I/O operation
IOF F040 Interrupt off
Basic working principle of the Control Unit with
timing diagram:
• Three Components of Control unit are:
1. Two decoders (3x8 , 4x 16)
2. A sequence counter
3. Control logic gates
• An instruction read from memory is placed in the instruction register (IR). In control unit the IR is
divided into three parts: I bit, the operation code (12-14)bit, and bits 0 through 11.
• The operation code in bits 12 through 14 are decoded with a 3 X 8 decoder.
• Bit-15 of the instruction is transferred to a flip-flop designated by the symbol I.
• The eight outputs of the decoder are designated by the symbols D0 through D7. Bits 0 through
11 are applied to the control logic gates. The 4‐bit sequence counter can count in binary from 0
through 15.The outputs of counter are decoded into 16 timing signals T0 through T15.
• The sequence counter SC can be incremented or cleared synchronously. Most of the time, the
counter is incremented to provide the sequence of timing signals out of 4 X 16 decoder. Once in
awhile, the counter is cleared to 0, causing the next timing signal to be T0.
• As an example, consider the case where SC is incremented to provide timing signals T0, T1, T2,
T3 and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active. This is
expressed symbolically by the statement
D3T4: SC ← 0
Timing Diagram:

• The timing diagram figure shows the time relationship of the control signals.
• The sequence counter SC responds to the positive transition of the clock.
• Initially, the CLR input of SC is active.

• The first positive transition of the clock clears SC to 0, which in turn activates the timing T0 out of the
decoder. T0 is active during one clock cycle.
• The positive clock transition labeled T0 in the diagram will trigger only those registers whose control
inputs are connected to timing signal T0.
• SC is incremented with every positive clock transition, unless its CLR input is active.

• This procedures the sequence of timing signals T0, T1, T2, T3 and T4, and so on. If SC is not cleared, the
timing signals will continue with T5, T6, up to T15 and back to T0.
• The last three waveforms shows how SC is cleared when D3T4 = 1. Output D3 from the operation
decoder becomes active at the end of timing signal T2. When timing signal T4 becomes active, the
output of the AND gate that implements the control function D3T4 becomes active.

• This signal is applied to the CLR input of SC. On the next positive clock transition the counter is cleared to
0. This causes the timing signal T0 to become active instead of T5 that would have been active if SC were
incremented instead of cleared.
 Instruction Execution Cycle :

• A program residing in the memory unit of the computer consists of a sequence of

instructions. In the basic computer each instruction cycle consists of the following
phases:

1. Fetch an instruction from memory

2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the next
instruction
• This process continues unless a HALT instruction is encountered.

• Note: Every different processor has its own (different) instruction cycle
 • Fetch and Decode

• Initially, the program counter PC is loaded with the address of first instruction in the
program.
• The sequence counter SC is cleared to 0, providing a decoded timing signal T0.
• After each clock pulse, SC is incremented by 1.
• The following microoperation for fetch & decode phases can be specified by the following
resister transfer statements.

T0: AR  PC (S0S1S2=010, T0=1)

T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

• Only AR is connected to address inputs of memory, AR  PC with timing signal T0.

• The instruction read from memory, IR  M [AR] with timing signal T1 & at the same time
PC  PC + 1
• At the time T2, the operation code in IR is decoded, the indirect bit I is transferred to flip-
flop & address part of instruction is transferred to AR.
• SC is incremented after each clock cycle pulse to produce the sequence T0, T1, T2.
Just for your reference
(Not prepare)
• The flowchart presents an initial configuration for the instruction cycle and shows how
the control determines the instruction type after the decoding.
• Decoder output D7= 1, the instruction must be register-reference or input-output type.
• If D7 = 0, the operation code must be one of the other seven values 110, specifying a
memory reference instruction. (000 – 110)
• Control then inspects the value of the first bit of the instruction, which now available in
flip-flop I.
• If D7 = 0 and I = 1, we have a memory-reference instruction with an indirect address. It
is then necessary to read the effective address from memory.
• The three instruction types are subdivided into four separate paths. The selected
operation is activated with the clock transition associated with timing signal T3.This can be
symbolized as follows:
D7 I
0 1 D’7 I T3 : AR  M[AR]
0 0 D’7 I ‘T3 : Nothing
1 0 D7 I ‘T3 : Execute a register-reference instr.
1 1
D7 I T3 : Execute an input-output instr.
• When a memory-reference instruction with I = 0 is encountered, it is not necessary to do
anything since the effective address is already in AR.

• However, the sequence counter SC must be incremented when D’7 I T3 = 1, so that the
execution of the memory-reference instruction can be continued with timing variable T4.

• A register-reference or input-output instruction can be executed with the clock associated

with timing signal T3. After the instruction is executed, SC is cleared to 0 and control returns
to the fetch phase with T0 =1. SC is either incremented or cleared to 0 with every positive
clock transition.
Reduced Instruction Set Architecture (RISC)

• RISC is the way to make hardware simpler whereas CISC is the

single instruction that handles multiple work.
• The main idea behind this is to simplify hardware by using an
instruction set composed of a few basic steps for loading,
evaluating, and storing operations just like a load command
will load data, a store command will store the data.
Characteristics of RISC:-
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved.
Advantages of RISC:-
• Simpler instructions: RISC processors use a smaller set of simple
instructions, which makes them easier to decode and execute quickly. This
results in faster processing times.
• Faster execution: Because RISC processors have a simpler instruction set,
they can execute instructions faster than CISC processors.
• Lower power consumption: RISC processors consume less power than
CISC processors, making them ideal for portable devices.
Disadvantages of RISC:-
• More instructions required: RISC processors require more instructions to
perform complex tasks than CISC processors.
• Increased memory usage: RISC processors require more memory to store
the additional instructions needed to perform complex tasks.
• Higher cost: Developing and manufacturing RISC processors can be more
expensive than CISC processors.
Complex Instruction Set Architecture (CISC)
• The main idea is that a single instruction will do all loading,
evaluating, and storing operations just like a multiplication command
will do stuff like loading data, evaluating, and storing it, hence it’s
complex.
Characteristics of CISC:-
• Complex instruction, hence complex instruction decoding.
• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to get executed.
• Less number of general-purpose registers as operations get
performed in memory itself.
• Complex Addressing Modes.
• More Data types.
Advantages of CISC:-
• Reduced code size: CISC processors use complex instructions that can perform
multiple operations, reducing the amount of code needed to perform a task.
• More memory efficient: Because CISC instructions are more complex, they
require fewer instructions to perform complex tasks, which can result in more
memory-efficient code.
• Widely used: CISC processors have been in use for a longer time than RISC
processors, so they have a larger user base and more available software.

Disadvantages of CISC:-
• Slower execution: CISC processors take longer to execute instructions because
they have more complex instructions and need more time to decode them.
• More complex design: CISC processors have more complex instruction sets,
which makes them more difficult to design and manufacture.
• Higher power consumption: CISC processors consume more power than RISC
processors because of their more complex instruction sets.
Example:
• Suppose we have to add two 8-bit numbers.
• CISC approach: There will be a single command or instruction
for this like ADD which will perform the task.
• RISC approach: Here programmer will write the first load
command to load data in registers then it will use a suitable
operator and then it will store the result in the desired location.
• So, add operation is divided into parts i.e. load, operate, store
due to which RISC programs are longer and require more
memory to get stored but require fewer transistors due to less
complex command.
 RISC CISC
Reduced Instruction Set Computer Complex Instruction Set Computer

Less number of instructions. Large number of instructions.

Fixed length instruction format. Variable length instruction format.

Few number of addressing modes. More number of addressing modes.

Less cost More cost

Less powerful More powerful

An instruction executed in a single clock cycle. Instruction takes more than one clock cycle

Manipulation directly in register. Manipulation directly in memory.

Requires more number of registers Requires less number of registers

Uses both hardwired and microprogrammed

Uses only Hardwired control unit
control unit
 RISC CISC
Code size is large Code size is small

RISC is highly pipelined. CISC is less pipelined.

Can perform only Register to Register Arithmetic Can perform REG to REG or REG to MEM or MEM
operations to MEM

An instruction fit in one word. Instructions are larger than the size of one word

RISC is Reduced Instruction Cycle. CISC is Complex Instruction Cycle.

The number of instructions are less as compared The number of instructions are more as compared
to CISC. to RISC.

It consumes the low power. It consumes more/high power.