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ES9018S

Reference 32-bit Audio DAC

Analog Reinvented Product Datasheet

The SABRE32 Reference audio DAC series is the world’s highest performance 32-bit audio DAC solution targeted for consumer applications such
as Blu-ray players, audio pre-amplifiers, A/V receivers and professional applications such as recording systems, mixer consoles and digital audio
workstations.

Part 32-bit I2S / DSD SPDIF Jitter

Description Package DNR (dB) THD (dB)
Number DAC Input Input Reduction
SABRE32 Reference 135 (mono)
ES9018 64-LQFP –120 Yes Yes Yes Yes
8-Channel Audio DAC 129 (8-Ch)

With ESS’ patented 32-bit HyperStreamTM DAC architecture and Time Domain Jitter Eliminator, the SABRE32 Reference Stereo DAC delivers an
unprecedented DNR of up to 135dB and THD+N of –120dB, the industry’s highest performance level that will satisfy the most demanding audio
enthusiasts.

The SABRE32 Reference audio DAC’s 32-bit HyperStreamTM architecture can handle full 32-bit PCM data via I2S input, as well as DSD or SPDIF
data. The SABRE32 Reference supports up to 1.536MHz input sampling rates and consumes less than 100mW.

The SABRE32 Reference DACs set the standard for HD audio performance, SABRE SOUNDTM, in a cost-effective, easy-to-use form factor for
today’s most demanding digital-audio applications.

Feature Description
Patented 32-bit HyperStreamTM DAC
Industry’s highest performance 32-bit audio DAC with unprecedented dynamic range and
o Up to 135dB DNR
ultra-low distortion
–120dB THD+N

Patented Time Domain Jitter Eliminator Unmatched audio clarity free from input clock jitter

64-bit accumulator and 32-bit processing Distortion free signal processing

Universal digital input for up to 1.536MHz1 sampling Supports SPDIF, PCM (I2S, MSB / LSB justified 16-32-bit) or DSD input with DVD Audio
rate and SACD compatibility.
Click-free soft mute and volume control
Programmable filter characteristics for PCM / DSD
Integrated DSP functions
Programmable Zero detect
De-emphasis for 32kHz, 44.1kHz, and 48kHz sampling
Mono, stereo, 8-channel output in current- or voltage-mode based on performance
Customizable output configuration
criterion

Customizable filter characteristics User-programmable filter allowing custom roll-off response

100mW power consumption Simplifies power supply design

APPLICATIONS
• Blu-ray / SACD / DVD-Audio player • Audio preamplifier and receiver

• A/V processor • Professional audio recording systems and mixing consoles

• Digital audio workstation

2.3

ES9018S Product Datasheet

Table of Contents
APPLICATIONS................................................................................................................................................................................................................ 1
Functional Block Diagram ................................................................................................................................................................................................. 4
Application Diagram.......................................................................................................................................................................................................... 5
Pin Layout ......................................................................................................................................................................................................................... 6
Pin Descriptions ................................................................................................................................................................................................................ 7
5V Tolerant Pins ............................................................................................................................................................................................................... 8
Functional Descriptions .................................................................................................................................................................................................... 9
Notations for Sampling Rates....................................................................................................................................................................................... 9
PCM, SPDIF and DSD Pin Connections ...................................................................................................................................................................... 9
PCM Audio Format .................................................................................................................................................................................................. 9
Feature Descriptions....................................................................................................................................................................................................... 11
Soft Mute .................................................................................................................................................................................................................... 11
Automute .................................................................................................................................................................................................................... 11
Volume Control........................................................................................................................................................................................................... 11
Master Trim ................................................................................................................................................................................................................ 11
All Mono Mode ........................................................................................................................................................................................................... 11
De-emphasis .............................................................................................................................................................................................................. 12
OSF Bypass ............................................................................................................................................................................................................... 12
SPDIF Data Select ..................................................................................................................................................................................................... 12
Programmable Filter ................................................................................................................................................................................................... 12
System Clock (XI / MCLK) .......................................................................................................................................................................................... 12
Data Clock .................................................................................................................................................................................................................. 13
Built-in Digital Filters................................................................................................................................................................................................... 13
Sample Rate Calculation ............................................................................................................................................................................................ 13
DAC-bar Phase .......................................................................................................................................................................................................... 13
DPLL Lock Reset ....................................................................................................................................................................................................... 13
DPLL Frequency Phase Flip ...................................................................................................................................................................................... 13
PCM Audio Interface Formats .................................................................................................................................................................................... 13
Audio Interface Formats ................................................................................................................................................................................................. 14
Serial Control Interface ................................................................................................................................................................................................... 15
Register Map .................................................................................................................................................................................................................. 17
Register Listing ............................................................................................................................................................................................................... 19
Read Write Registers ................................................................................................................................................................................................. 19
Read Only Registers .................................................................................................................................................................................................. 32
Read Write Registers ................................................................................................................................................................................................. 33
FIR Programmable Filters............................................................................................................................................................................................... 37

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 2
2.3

ES9018S Product Datasheet

C++ Sample Code for writing custom coefficients to either stage. ............................................................................................................................. 38
Application Diagrams ...................................................................................................................................................................................................... 39
Recommended Differential, Current-Mode External Op-Amp Circuit ......................................................................................................................... 39
ES9018 Stereo Quad-differential Current Mode ........................................................................................................................................................ 39
Absolute Maximum Ratings ............................................................................................................................................................................................ 41
Recommended Operating Conditions............................................................................................................................................................................. 41
DC Electrical Characteristics .......................................................................................................................................................................................... 41
MCLK Timing .................................................................................................................................................................................................................. 42
Audio Interface Timing .................................................................................................................................................................................................... 42
Recommended Power-Up Sequence ............................................................................................................................................................................. 43
Analog Performance ....................................................................................................................................................................................................... 44
PCM DE-EMPHASIS FILTER RESPONSE (32kHz) ...................................................................................................................................................... 46
PCM DE-EMPHASIS FILTER RESPONSE (44.1kHz) ................................................................................................................................................... 46
PCM DE-EMPHASIS FILTER RESPONSE (48kHz) ...................................................................................................................................................... 47
PCM Sharp Roll-Off Filter Response .............................................................................................................................................................................. 47
PCM Slow Roll-Off Filter Response................................................................................................................................................................................ 48
DSD Filter Response ...................................................................................................................................................................................................... 48
64-Pin LQFP Mechanical Dimensions ............................................................................................................................................................................ 49
Reflow Process Considerations ...................................................................................................................................................................................... 50
Manual Soldering ....................................................................................................................................................................................................... 51
Ordering Information ....................................................................................................................................................................................................... 53
Revision History .............................................................................................................................................................................................................. 54

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 3
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ES9018S Product Datasheet

List of Figures
Figure 1 - Functional Block Diagram ................................................................................................................................................................................ 5
Figure 2 - Application Diagram ......................................................................................................................................................................................... 5
Figure 3 – Pin Layout........................................................................................................................................................................................................ 6
Figure 4 - Audio Interface Formats ................................................................................................................................................................................. 14
Figure 5 - I2C Addresses ................................................................................................................................................................................................ 15
Figure 6 - I2C timing ....................................................................................................................................................................................................... 16
Figure 7 - Recommended Differential, Current-Mode External Op-Amp Circuit ............................................................................................................. 39
Figure 8 - Sabre 32 Reference DAC in stereo “quad-differential” current mode ............................................................................................................ 39
Figure 9 - Sabre32 Reference DAC in 8-Channel differential current mode .................................................................................................................. 40
Figure 10 - PCM Sharp Roll-Off Filter Response ........................................................................................................................................................... 47
Figure 11 - PCM Slow Roll-Off Filter Response ............................................................................................................................................................. 48
Figure 12 - DSD Filter Response .................................................................................................................................................................................... 48
Figure 13 - 64-Pin LQFP Mechanical Dimensions .......................................................................................................................................................... 49
Figure 14 - IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1) ......................................................................................................................... 50

List of Tables
Table 1 - Pin Descriptions................................................................................................................................................................................................. 8
Table 2 - Notations for Sampling Rates ............................................................................................................................................................................ 9
Table 3 - PCM pin connections......................................................................................................................................................................................... 9
Table 4 - SPDIF pin connections ...................................................................................................................................................................................... 9
Table 5 - DSD pin connections ....................................................................................................................................................................................... 10
Table 6 - Automute configurations .................................................................................................................................................................................. 11
Table 7 - MCLK configurations ....................................................................................................................................................................................... 12
Table 8 - PCM Audio Interface Formats ......................................................................................................................................................................... 13
Table 9 – Absolute Maximum Ratings ............................................................................................................................................................................ 41
Table 10 - Recommended Operating Conditions ........................................................................................................................................................... 41
Table 11 - DC Electrical Characteristics ......................................................................................................................................................................... 41
Table 12 - Analog Performance ...................................................................................................................................................................................... 45
Table 13 - PCM DE-EMPHASIS FILTER RESPONSE (32kHz) ..................................................................................................................................... 46
Table 14 - PCM DE-EMPHASIS FILTER RESPONSE (44.1kHz) .................................................................................................................................. 46
Table 15 - PCM DE-EMPHASIS FILTER RESPONSE (48kHz) ..................................................................................................................................... 47
Table 16 - RPC-1 Classification reflow profile ................................................................................................................................................................ 52
Table 17 - RPC-2 Pb-Free Process - Classification Temperatures (Tc)......................................................................................................................... 52
Table 18 - Ordering Information...................................................................................................................................................................................... 53

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 4
2.3

ES9018S Product Datasheet

Functional Block Diagram

AUTOMUTE

ADDR
RESET

SDA
SCL
CONTROL INTERFACE Reference
ES9018
DATA[8:1] DSD/PCM OVERSAMPLING FILTER
Interface Fast/Slow roll-off (PCM)
DATA_CLK 50/60/70kHz (DSD) Jitter HyperstreamTM Dynamic DAC[8:1]
De-emphasis (PCM) Reduction DAC Matching
Volume Control DACB[8:1]
(8x) (8x)
Soft Mute
SPDIF in SPDIF Zero Detect DPLL
Receiver

AVCC
MCLK VREF
POWER SUPPLY
AGND

DGND
DVCC

Figure 1 - Functional Block Diagram

Application Diagram
FL

Blu-Ray Player FR

Audio LFE
DSP
Universal DVD/DVD-Audio/ ES9018
SL
SACD Player Sabre32 Reference
64 -LQFP
SR

Home Theater Receiver

Figure 2 - Application Diagram

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 5
2.3

ES9018S Product Datasheet

Pin Layout

Figure 3 – Pin Layout

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 6
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ES9018S Product Datasheet

Pin Descriptions
Pin Name I/O Description
1 VDD_L - Analog Power (+1.2V) for Left channels
2 DAC1 O Differential Positive Analog Output 1
3 DAC1B O Differential Negative Analog Output 1
4 DAC3B O Differential Negative Analog Output 3
5 DAC3 O Differential Positive Analog Output 3
6 AGND_L - Analog Ground for Left channels
7 AVCC_L - Analog Power (+3.3V) for Left channels
8 RESET I Global Reset Input, Active High
9 GND - Digital Ground
10 AVCC_L - Analog Power (+3.3V) for Left channels
11 AGND_L - Analog Ground for Left channels
12 DAC5 O Differential Positive Analog Output 5
13 DAC5B O Differential Negative Analog Output 5
14 DAC7B O Differential Negative Analog Output 7
15 DAC7 O Differential Positive Analog Output 7
16 VDD_L - Analog Power (+1.2V) for Left channels
17 AVCC_L - Analog Power (+3.3V) for Left channels
18 AGND_L - Analog Ground for Left channels
19 GND - Digital Ground
20 VDD - Digital Power (+1.2V) for core of chip
21 SDA I/O I2C Serial Data Input / Output
22 SCL I I2C Serial Clock Input
23 XO O Crystal oscillator output
24 XI (MCLK) I Crystal oscillator input (Note: can also just be a clock input)
25 DVCC_B - Digital Power (+3.3V) for bottom pad ring of chip
26 LOCK O Lock output
27 N.C. Not connected (leave open)
28 N.C. Not connected (leave open)
29 VDD - Digital Power (+1.2V) for core of chip
30 GND - Digital Ground
31 AGND_R - Analog Ground for Right channels
32 AVCC_R - Analog Power (+3.3V) for Right channels
33 VDD_R - Analog Power (+1.2V) for Right channels
34 DAC8 O Differential Positive Analog Output 8
35 DAC8B O Differential Negative Analog Output 8
36 DAC6B O Differential Negative Analog Output 6
37 DAC6 O Differential Positive Analog Output 6
38 AGND_R - Analog Ground for Right channels
39 AVCC_R - Analog Power (+3.3V) for Right channels
40 AUTMOMUTE O Automute
41 ADDR I Chip Address Select

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 7
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ES9018S Product Datasheet

42 AVCC_R - Analog Power (+3.3V) for Right channels

43 AGND_R - Analog Ground for Right channels
44 DAC4 O Differential Positive Analog Output 4
45 DAC4B O Differential Negative Analog Output 4
46 DAC2B O Differential Negative Analog Output 2
47 DAC2 O Differential Positive Analog Output 2
48 VDD_R - Analog Power (+1.2V) for Right channels
49 AVCC_R - Analog Power (+3.3V) for Right channels
50 AGND_R - Analog Ground for Right channels
51 GND - Digital Ground
52 DATA8 I DSD Data8 OR SPDIF Input8
53 DATA7 I DSD Data7 OR SPDIF Input7
54 DATA6 I DSD Data6 OR SPDIF Input6
55 DATA5 I DSD Data5 OR PCM Data CH7/CH8 OR SPDIF Input5
56 DATA4 I DSD Data4 OR PCM Data CH5/CH6 OR SPDIF Input4
57 DATA3 I DSD Data3 OR PCM Data CH3/CH4 OR SPDIF Input3
58 DATA2 I DSD Data2 OR PCM Data CH1/CH2 OR SPDIF Input2
59 DATA1 I DSD Data1 OR PCM Frame Clock OR SPDIF Input1
60 DATA_CLK I PCM Bit Clock OR DSD Bit Clock
61 VDD - Digital Power (+1.2V) for core of chip
62 DVCC_T - Digital Power (+3.3V) for top pad ring of chip
63 AGND_L - Analog Ground for Left channels
64 AVCC_L - Analog Power (+3.3V) for Left channels
Table 1 - Pin Descriptions

5V Tolerant Pins
The following pins are 5V tolerant:
• DATA_CLK
• DATA 1-8
• SCL
• SDA
• ADDR
• RESET

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 8
2.3

ES9018S Product Datasheet

Functional Descriptions
Notations for Sampling Rates
Mode fs Fs
DSD DATA_CLK / 64 DSD data rate
Serial (PCM) Normal Mode DATA_CLK / 64 DATA_CLK / 64
Serial (PCM) OSF Bypass Mode DATA_CLK / 8 DATA_CLK / 8
SPDIF SPDIF Sampling Rate SPDIF Sampling Rate
Table 2 - Notations for Sampling Rates

PCM, SPDIF and DSD Pin Connections

The following tables show how the pins are used for PCM and DSD audio formats.

PCM Audio Format

Notes:
• XI clock (MCLK) must be > 192 x Fs (for Fs  200kHz) when using PCM input (normal mode)
• XI clock (MCLK) must be > 256 x Fs (200kHz < Fs  384kHz) when using PCM input (normal mode)
• XI clock (MCLK) must be > 24 x Fs (Fs  1.536MHz) when using PCM input (OSF bypass mode)

Pin Name Description

DATA1 Frame clock
DATA[2:5] 8-channel PCM serial data
DATA_CLK Bit clock for PCM audio format
Table 3 - PCM pin connections

SPDIF Audio Formant

Note: XI clock (MCLK) must be > 386 x Fs (for Fs  200kHz) when using SPDIF input

Pin Name Description

Up to 8 SPDIF inputs can be connected to an 8-to-1 mux internal to
DATA[1:8]
SABRE32 Reference, selectable via register SPDIF Source
Table 4 - SPDIF pin connections

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 9
2.3

ES9018S Product Datasheet

DSD Audio Format

Note: XI clock (MCLK) must be > 3 x Fs (Fs = 2.8224MHz x1, x2, or x4) when using DSD input

Pin Name Description

DATA[1:8] 8-channel DSD data input
DATA_CLK Bit clock for DSD data input
Table 5 - DSD pin connections

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 10
2.3

ES9018S Product Datasheet

Feature Descriptions
Soft Mute
When Mute is asserted the output signal will ramp to the – level. When Mute is reset the attenuation level will ramp back up to the previous level set
by the volume control register. Asserting Mute will not change the value of the volume control register. The ramp rate is 0.0078125 x fs dB/s, where
fs = DATA_CLK / 64 in PCM serial or DSD modes, or SPDIF sampling rate in SPDIF mode.

Automute
During an automute condition the ramping of the volume of each DAC to – can now be programmatically enabled or disabled.
o In PCM serial mode, “AUTOMUTE” will become active once the audio data is continuously below the threshold set by <Register Automute_lev>,
for a length of time defined by 2096896 / (<Register#9> x DATA_CLK) Seconds.
o In SPDIF mode, “AUTOMUTE” will become active once the audio data is continuously below the threshold set by <Register Automute_lev>, for
a length of time defined by 2096896 / (<Register#9> x (64 x Fs) Seconds, where Fs is the SPDIF sampling rate.
o In the DSD Mode, “AUTOMUTE” will become active when any 8 consecutive values in the DSD stream have as many 1’s and 0’s for a length of
time defined by 2096896 / (<Register Automute_time> x DATA_CLK) Seconds. The following table summarizes the conditions.

Mode Detection Condition Time

Data is continuously lower than <Register
PCM 2096896 / (<Register Automute_time > x DATA_CLK)
Automute_lev>

Data is continuously lower than <Register 2096896 / (<Register Automute_time > x (64 x Fs))
SPDIF
Automute_lev> where Fs is the SPDIF sampling rate
Equal number of 1s and 0s in every 8 bits of
DSD 2096896 / (<Register Automute_time > x DATA_CLK)
data
Table 6 - Automute configurations

Volume Control
Each output channel has its own attenuation circuit. The attenuation for each channel is controlled independently. Each channel can be attenuated
from 0dB to –127dB in 0.5dB steps.
Each 0.5dB step transition takes 64 intermediate levels. The result being that the level changes are done using small enough steps so that no
switching noise occurs during the transition of the volume control. When a new volume level is set, the attenuation circuit will ramp softly to the new
level.

Master Trim
The master trim sets the 0dB reference level for the volume control of each DAC. The master trim is programmable via registers 20-23 and is a 32bit
signed number. Therefore it should never exceed 32'h7FFFFFFF (as this is full-scale signed).

All Mono Mode

The SABRE32 can be put into an all mono mode where all eight DACs are driven from the same source. This can be useful for high-end audio
applications. The source data for all eight DACs can be programmatically configured to be either PCM CH1 or CH2.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 11
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ES9018S Product Datasheet

De-emphasis
The de-emphasis feature is included for audio data that has utilized the 50/15s pre-emphasis for noise reduction. There are three de-emphasis
filters, one for 32kHz, one for 44.1kHz, and one for 48kHz.

The de-emphasis filter can automatically be applied when an SPDIF stream sets the de-emphasis flag. It will auto detect the sample rate (32k,
44.1k, 48k) in either consumer or professional formats and then apply the correct de-emphasis filter. The automatic enabling of the de-emphasis
filter can be disabled in Register 17 <en_auto>.

OSF Bypass
The oversampling FIR filter can be bypassed, sourcing data directly into the IIR filter. ESS recommends using 8 x Fs as the input. For example, an
external signal at 44.1kHz can be oversampled externally to 8 x 44.1kHz = 352.8kHz and then applied to the serial decoder in either I 2S, LJ or RJ
format. The maximum sample rate that can be applied is 1.536MHz (8 x 192kHz).

SPDIF Data Select

An SPDIF source multiplexer allows for up to eight SPDIF sources to be connected to the data pins on the SABRE32 Reference. The SABRE32
Reference uses an internal programmable register to select the appropriate data pin to decode.

SPDIF input can be automatically decoded when there is valid SPDIF data if Register 17 <spdif_autodetect> is enabled.

Programmable Filter
The FIR filter can be programmed with custom coefficients to achieve an arbitrary frequency response that suits the needs of the product. The two
stage interpolated filter exploits the symmetry of the coefficients to achieve a very sharp frequency response while using only 64 coefficients for the
stage one filter and 14 coefficients for the stage two filter. Custom coefficients can be enabled via register 37 <prog_coeff_enabled> and can be
programmed via the method explained in the FIR Programmable Filters section.

The length of the stage 2 filter is configurable to either 27 or 28 coefficients via register 17 <fir_length>.

System Clock (XI / MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry. Maximum MCLK frequency is 100MHz. The system
clock must also satisfy:

Data Type Valid MCLK Frequencies

DSD Data 100MHz > MCLK > 3 x Fs, Fs = 2.8224MHz (x 1, 2, or 4)
100MHz > MCLK > 192 x Fs, Fs  200kHz, or
Serial Normal Mode
100MHz > MCLK > 256 x Fs, 200kHz < Fs  384kHz
Serial OSF Bypass Mode 100MHz > MCLK > 24 x Fs, Fs  1.536MHz
SPDIF Data 100MHz > MCLK > 386 x Fs, Fs  200kHz
Table 7 - MCLK configurations

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 12
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ES9018S Product Datasheet

Data Clock
DATA_CLOCK must be 64 x Fs for SERIAL, Fs for DSD modes, and is not required for SPDIF mode. This pin should be pulled low if not used.

Built-in Digital Filters

There are numerous applications for a stereo DAC so for added flexibility; two digital filter settings are possible, sharp roll-off and a slow roll-off for
PCM mode. For DSD mode, there are four available filters with cutoffs at 47kHz, 50kHz, 60kHz, and 70kHz.

Sample Rate Calculation

The DPLL number can be read back from the SABRE32 Reference, allowing for calculation of the sample rate. The sample rate can be calculated
using: Fin = (DPLL_NUM x Fcrystal) / 232. Fin must be divided by 64 for I2S data.

DAC-bar Phase
Each DAC-bar phase can be configured to be in phase with DAC. This allows for the outputs of the DAC to be summed to drive an amplifier.

DPLL Lock Reset

The DPLL can be forced to relock, which is useful when the sample rate has been changed. This can be done by setting Register 17
<dpll_lock_rst_reg> high to force the reset, and then low to resume normal operation.

DPLL Frequency Phase Flip

The DPLL can be set to lock to either the rising or falling edge of the clock. This can be set using Register 17 <fin_phase_flip>.

PCM Audio Interface Formats

Several interface formats are provided so that direct connection to common audio processors is possible. The available formats and their
accompanying diagrams are listed in the following table. The audio interface format can be set by programming the registers.

Format Description Figure

0 MSB First, Left Justified, up to 32-bit data 1A
1 I2S, up to 32-bit data 3A
2 MSB First, Right Justified, 32-bit data 2A
3 MSB First, Right Justified, 24-bit data 2B
4 MSB First, Right Justified, 20-bit data 2C
5 MSB First, Right Justified, 16-bit data 2D
6 DSD Normal Mode 4A
7 DSD Phase Mode 4B
Table 8 - PCM Audio Interface Formats

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 13
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ES9018S Product Datasheet

Audio Interface Formats

Several interface formats are provided so that direct connection to common audio processors is possible. The available formats are shown in the
following diagrams. The audio interface format can be set by programming the registers.

LRCLK RIGHT
LEFT

BCLK
SIN
31 30 29 2 1 0 31 30 29 2 1 0 31 30 FIGURE 1A
32-bit MSB LSB MSB LSB MSB
SIN
24-bit 23 22 21 2 1 0 23 22 21 2 1 0 23 22 FIGURE 1A
MSB LSB MSB LSB MSB
SIN
20bit 19 18 17 2 1 0 19 18 17 2 1 0 19 18 FIGURE 1A
MSB LSB MSB LSB MSB
SIN
16bit 15 14 13 2 1 0 15 14 13 2 1 0 15 14 FIGURE 1A
MSB LSB MSB LSB MSB

LEFT JUSTIFIED FORMAT

LRCLK RIGHT
LEFT

BCLK
SIN
31 30 29 2 1 0 31 30 29 2 1 0 31 30 FIGURE 2A
32-bit MSB LSB MSB LSB MSB
SIN
24-bit 23 22 21 2 1 0 23 22 21 2 1 0 FIGURE 2A
MSB LSB MSB LSB
SIN
20bit 19 18 17 2 1 0 19 18 17 2 1 0 FIGURE 2A
MSB LSB MSB LSB
SIN
16bit 15 14 13 2 1 0 15 14 13 2 1 0 FIGURE 2A
MSB LSB MSB LSB

RIGHT JUSTIFIED FORMAT

LRCLK RIGHT
LEFT

BCLK
SIN
31 30 29 2 1 0 31 30 29 2 1 0 31 30 FIGURE 3A
32-bit MSB LSB MSB LSB MSB
SIN
24-bit 23 22 21 2 1 0 23 22 21 2 1 0 23 22 FIGURE 3A
MSB LSB MSB LSB MSB
SIN
20bit 19 18 17 2 1 0 19 18 17 2 1 0 19 18 FIGURE 3A
MSB LSB MSB LSB MSB
SIN
16bit 15 14 13 2 1 0 15 14 13 2 1 0 15 14 FIGURE 3A
MSB LSB MSB LSB MSB

I2S FORMAT

DCLK
D1
D.. D0 D1 D2 D3 D4 FIGURE 4A
D2
DSD NORMAL MODE

DCLK
D1
D.. D.. D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 FIGURE 4B
D2
DSD PHASE MODE

Figure 4 - Audio Interface Formats

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 14
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ES9018S Product Datasheet

Serial Control Interface

The registers inside the chip are programmed via an I2C interface. The diagram below shows the timing for this interface. The chip address can be
set to 2 different settings via the “ADDR” pin. Table 7 below summarizes this.

ADDR CHIP ADDRESS

0 0x90
1 0x92

Figure 5 - I2C Addresses

Notes:
The “ADDR” pin is used to create the CHIP ADDRESS. (0x90, 0x92)
The first byte after the chip address is the “ADDRESS” this is the register address.
The second byte after the CHIP ADDRESS is the “DATA” this is the data to be programmed into the register at the previous “ADDRESS”.
Compatible with I2C-bus specification version 2.1 Standard-mode/Fast-mode.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 15
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ES9018S Product Datasheet

Start Start Stop Start

Parameter Symbol Standard-Mode Fast-Mode Unit

MIN MAX MIN MAX
SCL Clock Frequency fSCL 0 100 0 400 kHz
START condition hold time tHD,STA 4.0 - 0.6 - s

LOW period of SCL tLOW 4.7 - 1.3 - s

HIGH period of SCL tHIGH 4.0 - 0.6 - s
START condition setup time (repeat) tSU,STA 4.7 - 0.6 - s
SDA hold time from SCL falling tHD,DAT 0.3 - 0.3 - s
SDA setup time from SCL rising tSU,DAT 250 - 100 - ns
Rise time of SDA and SCL tr - 1000 300 ns
Fall time of SDA and SCL tf - 300 300 ns
STOP condition setup time tSU,STO 4 - 0.6 - s
Bus free time between transmissions tBUF 4.7 - 1.3 - s
Capacitive load for each bus line Cb - 400 - 400 pF

Figure 6 - I2C timing

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2.3

ES9018S Product Datasheet

Register Map
Addr Addr Register 7 6 5 4 3 2 1 0
(Hex) (Dec)
0x0 0 VOLUME OF DAC 0 VOLUME_DAC0
0x1 1 VOLUME OF DAC 1 VOLUME_DAC1
0x2 2 VOLUME OF DAC 2 VOLUME_DAC2
0x3 3 VOLUME OF DAC 3 VOLUME_DAC3
0x4 4 VOLUME OF DAC 4 VOLUME_DAC4
0x5 5 VOLUME OF DAC 5 VOLUME_DAC5
0x6 6 VOLUME OF DAC 6 VOLUME_DAC6
0x7 7 VOLUME OF DAC 7 VOLUME_DAC7
0x8 8 AUTOMUTE LEVEL SPDIF_ENAB AUTOMUTE_LEVEL
LE
0x9 9 AUTOMUTE TIME AUTOMUTE_TIME
0xA 10 MODE CONTROL 1 SERIAL_DATA_LENGTH SERIAL_DATA_MODE RESERVED JITTER_RED BYPASS_DEE MUTE_DAC
UCTION_EN MPHASIS_FI
ABLE LTER
0xB 11 MODE CONTROL 2 RESERVED DPLL_BANDWIDTH DE_EMPHASIS_SELECT
0xC 12 RESERVED RESERVED
0xD 13 DAC POLARITY POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D
AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1
0xE 14 IIR BANDWIDTH AND FIR SOURCE_DA SOURCE_DA SOURCE_DA SOURCE_DA RESERVED IIR_BANDWIDTH FIR_ROLLOF
ROLLOFF C8 C7 C4 C3 F_SPEED
0xF 15 RESERVED RESERVED
0x10 16 AUTOMUTE LOOPBACK RESERVED AUTOMUTE RESERVED
_LOOPBACK
0x11 17 MODE CONTROL 5 MONO_CH_ OSF_BYPASS DPLL_LOCK_ AUTO_DEE SPDIF_AUTO FIR_LENGTH FIN_PHASE_ ALL_MONO
SEL RST_REG MPH DETECT FLIP
0x12 18 SPDIF SOURCE SPDIF_SOURCE
0x13 19 DACB POLARITY POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D POLARITY_D
AC8B AC7B AC6B AC5B AC4B AC3B AC2B AC1B
0x14 20 MASTER TRIM MASTER_TRIM
0x15 21 MASTER TRIM MASTER_TRIM
0x16 22 MASTER TRIM MASTER_TRIM
0x17 23 MASTER TRIM MASTER_TRIM
0x18 24 PHASE SHIFT RESERVED PHASE_SHIFT
0x19 25 DPLL MODE CONTROL RESERVED DPLL_BW_D DPLL_BW_1
EFAULTS 28X
0x1A 26 RESERVED RESERVED
0x1B 27 STATUS RESERVED DSD_PCM SPDIF_VALID SPDIF_EN LOCK
0x1C 28 DPLL NUM DPLL_NUM
0x1D 29 DPLL NUM DPLL_NUM
0x1E 30 DPLL NUM DPLL_NUM
0x1F 31 DPLL NUM DPLL_NUM
0x25 37 FIR COEFFICIENTS RESERVED STAGE1_PR STAGE1_PR RESERVED STAGE2_PR STAGE2_PR
OG_COEFF_ OGRAMMIN OG_COEFF_ OGRAMMIN
ENABLED G_ENABLED ENABLED G_ENABLED
0x26 38 STAGE 1 FIR COEFFICIENTS STAGE1_FIR_COEFFICIENTS
0x27 39 STAGE 1 FIR COEFFICIENTS STAGE1_FIR_COEFFICIENTS
0x28 40 STAGE 1 FIR COEFFICIENTS STAGE1_FIR_COEFFICIENTS
0x29 41 STAGE 1 FIR COEFFICIENTS STAGE1_FIR_COEFFICIENTS
0x2A 42 RESERVED RESERVED
0x2B 43 RESERVED RESERVED
0x2C 44 RESERVED RESERVED
0x2D 45 RESERVED RESERVED
0x30 48 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x31 49 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x32 50 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x33 51 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x34 52 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x35 53 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x36 54 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x37 55 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x38 56 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA
0x39 57 SPDIF CHANNEL STATUS SPDIF_CHANNEL_STATUS_DATA
DATA

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ES9018S Product Datasheet

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ES9018S Product Datasheet

Bits Mnemonic Description

[7:0] VOLUME_DAC0 Volume in dBs = -REG_VALUE/2

Register 1: VOLUME OF DAC 1

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC1 Volume in dBs = -REG_VALUE/2

Register 2: VOLUME OF DAC 2

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC2 Volume in dBs = -REG_VALUE/2

Register 3: VOLUME OF DAC 3

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC3 Volume in dBs = -REG_VALUE/2

Register 4: VOLUME OF DAC 4

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC4 Volume in dBs = -REG_VALUE/2

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ES9018S Product Datasheet

Register 5: VOLUME OF DAC 5

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC5 Volume in dBs = -REG_VALUE/2

Register 6: VOLUME OF DAC 6

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC6 Volume in dBs = -REG_VALUE/2

Register 7: VOLUME OF DAC 7

Bits [7:0]
Default 8'd0

Bits Mnemonic Description

[7:0] VOLUME_DAC7 Volume in dBs = -REG_VALUE/2

Register 8: AUTOMUTE LEVEL

Bits [7] [6:0]
Default 1'b0 7'd104

Bits Mnemonic Description

[7] SPDIF_ENABLE SPDIF input select.
• 1'b0: Use either I2S or DSD input
• 1'b1: Use SPDIF input
[6:0] AUTOMUTE_LEVEL Automute trigger point select.
Automute trigger point in dB's = -REG_VALUE

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ES9018S Product Datasheet

Register 9: AUTOMUTE TIME

Bits [7:0]
Default 8'd4

Bits Mnemonic Description

[7:0] AUTOMUTE_TIME Automute time control.
• 8’d0: Longest time
• 8’d4: Default
• 8’d255: Shortest time
•

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ES9018S Product Datasheet

Register 10: MODE CONTROL 1

Bits [7:6] [5:4] [3] [2] [1] [0]
Default 2'b11 2'b00 1'b1 1'b1 1'b1 1'b0

Bits Mnemonic Description

[7:6] SERIAL_DATA_LENGTH Serial data length control.
• 2'b00: 24 Bit
• 2'b01: 20 Bit
• 2'b10: 16 Bit
• 2'b11: 32 Bit
[5:4] SERIAL_DATA_MODE Serial data mode select.
• 2'b00: I2S
• 2'b01: LJ
• 2'b10: RJ
• 2'b11: I2S
[3] RESERVED NA
[2] JITTER_REDUCTION_ENABLE Jitter reduction enable.
1'b0: Bypass and stop JITTER_REDUCTION
1'b1: Use JITTER_REDUCTION
[1] BYPASS_DEEMPHASIS_FILTER De-emphasize filter enable.
1'b0: Use De-emphasize filter
1'b1: Bypass De-emphasize filter
[0] MUTE_DAC DAC mute control.
• 1'b0: Unmute all DACs
• 'b1: Mute all DACs

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ES9018S Product Datasheet

Register 11: MODE CONTROL 2

Bits [7:5] [4:2] [1:0]
Default 3'b100 3'b001 2'b01

Bits Mnemonic Description

[7:5] RESERVED NA
[4:2] DPLL_BANDWIDTH DPLL bandwidth control.
• 3'b000: No Bandwidth
• 3'b001: Lowest Bandwidth
• 3'b010: Low Bandwidth
• 3'b011: Med-Low Bandwidth
• 3'b100: Medium Bandwidth
• 3'b101: Med-High Bandwidth
• 3'b110: High Bandwidth
• 3'b111: Highest Bandwidth
[1:0] DE_EMPHASIS_SELECT De-emphasis frequency select
• 2'b00: 32 kHz
• 2'b01: 44.1 kHz
• 2'b10: 48 kHz
• 2'b11: RESERVED

Register 12: RESERVED

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ES9018S Product Datasheet

Register 13: DAC POLARITY

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0

Bits Mnemonic Description

[7] POLARITY_DAC8 Polarity control for DAC 8.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[6] POLARITY_DAC7 Polarity control for DAC 7.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[5] POLARITY_DAC6 Polarity control for DAC 6.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[4] POLARITY_DAC5 Polarity control for DAC 5.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[3] POLARITY_DAC4 Polarity control for DAC 4.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[2] POLARITY_DAC3 Polarity control for DAC 3.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[1] POLARITY_DAC2 Polarity control for DAC 2.
• 1'b0: In-Phase
• 1'b1: Anti-Phase
[0] POLARITY_DAC1 Polarity control for DAC 1.
• 1'b0: In-Phase
• 1'b1: Anti-Phase

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ES9018S Product Datasheet

Register 14: IIR BANDWIDTH AND FIR ROLLOFF

Bits [7] [6] [5] [4] [3] [2:1] [0]
Default 1'b0 1'b0 1'b0 1'b0 1'b1 2'b01 1'b1

Bits Mnemonic Description

[7] SOURCE_DAC8 DAC 8 source control.
• 1'b0: DAC8
• 1'b1: DAC6
[6] SOURCE_DAC7 DAC 7 source control.
• 1'b0: DAC7
• 1'b1: DAC5
[5] SOURCE_DAC4 DAC 4 source control.
• 1'b0: DAC4
• 1'b1: DAC2
[4] SOURCE_DAC3 DAC 3 source control.
• 1'b0: DAC3
• 1'b1: DAC1
[3] RESERVED NA
[2:1] IIR_BANDWIDTH IRR bandwidth control.
• 2'b00: Normal (for least in-band ripple for PCM data set
to Normal)
• 2'b01: 50k
• 2'b10: 60k
• 2'b11: 70k
[0] FIR_ROLLOFF_SPEED FIR roll off speed control
• 1'b0: Slow Rolloff
• 1'b1: Fast Rolloff

Register 15: RESERVED

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ES9018S Product Datasheet

Register 16: AUTOMUTE LOOPBACK

Bits [7:4] [3] [2:0]
Default 4'd0 1'b0 3'b000

Bits Mnemonic Description

[7:4] RESERVED NA
[3] AUTOMUTE_LOOPBACK Automute volume ramp down control.
• 1'b1: Ramp volume to -infinity upon automute
condition
• 1'b0: Do not ramp volume down upon automute
condition
[2:0] RESERVED NA

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ES9018S Product Datasheet

Register 17: MODE CONTROL 5

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1 1'b0 1'b0

Bits Mnemonic Description

[7] MONO_CH_SEL Channel select when ALL_MONO mode is enabled.
• 1'b1: Use the right channel when ALL_MONO mode is
enabled
• 1'b0: Use the left channel when ALL_MONO mode is
enabled
[6] OSF_BYPASS Polarity control for DAC 7.
• 1'b0: Use the OSF filter (normal operation)
• 1'b1: Send data directly from the I2S receiver to the
IIR filter at 8x.
Note: Setting to 1 will cause the signal to bypass the FIR
filters as well as the de-emphasis… filter but will still apply to
the volume controls.
[5] DPLL_LOCK_RST_REG DPLL_LOCK manual override.
• 1'b0: Normal Operation
• 1'b1: Manually override the DPLL_LOCK. This will
force the Jitter Eliminator to relock the signal.
[4] AUTO_DEEMPH SPDIF automatic de-emphasis control.
• 1'b0: De-emphasis filter is not automatically applied
• 1'b1: De-emphasis in SPDIF mode is automatically
applied with the correct frequency if 44.1k/48k/32k are
detected in the SPDIF channel status bits.
[3] SPDIF_AUTODETECT Automatic SPDIF input detection control.
• 1'b0: Must manually select SPDIF input.
• 1'b1: Automatically detect SPDIF input
Note: This should only be set if I2S data will not be applied to
the pins
[2] FIR_LENGTH 2nd stage FIR filter coefficient length control.
• 1'b1: 2nd stage FIR filter is 28 coefficients in length
• 1'b0: 2nd stage FIR filter is 27 coefficients in length
[1] FIN_PHASE_FLIP DPLL phase invert
• 1'b0: Do not invert the phase to the DPLL
• 1'b1: Invert the phase to the DPLL
[0] ALL_MONO Overall DAC true mono source enable.
• 1'b0: Normal 8 channel mode
• 1'b1: All 8 DACs are sourced from one source for true
mono.
Note: The channel to use as the source is selected by the
MONO_CH_SELECT register.

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ES9018S Product Datasheet

Register 18: SPDIF SOURCE

Bits [7:0]
Default 8'd1

Bits Mnemonic Description

[7:0] SPDIF_SOURCE This register chooses the SPDIF source. The Sabre32
Reference has an 8-to-1 multiplexer which allows up to 8
SPDIF inputs to be connected to the data pins.
• 8'd1: data1
• 8'd2: data2
• 8'd4: data3
• 8'd8: data4
• 8'd16: data5
• 8'd32: data6
• 8'd64: data7
• 8'd128: data8

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ES9018S Product Datasheet

Register 19: DACB POLARITY

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0

Bits Mnemonic Description

[7] POLARITY_DAC8B DAC8 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[6] POLARITY_DAC7B DAC7 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[5] POLARITY_DAC6B DAC6 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[4] POLARITY_DAC5B DAC5 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[3] POLARITY_DAC4B DAC4 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[2] POLARITY_DAC3B DAC3 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[1] POLARITY_DAC2B DAC2 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase
[0] POLARITY_DAC1B DAC1 polarity control.
• 1'b0: Anti-phase (normal operation)
• 1'b1: In-phase

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ES9018S Product Datasheet

Register 23-20: MASTER TRIM

Bits [31:0]
Default 32'h7FFFFFFF

Bits Mnemonic Description

[31:0] MASTER_TRIM This is a 32 bit value that sets the 0dB level for all volume
controls. This is a signed number, so it should never exceed
32'h7FFFFFFF (which is 2^31-1).
• 32’h00000000: Minimum
• 32’h7FFFFFFF: Maximum
Note: Register 23 contains the MSBs, Register 20 contains
the LSBs

Register 24: PHASE SHIFT

Bits [7:4] [3:0]
Default 4'd3 4'd0

Bits Mnemonic Description

[7:4] RESERVED NA
[3:0] PHASE_SHIFT Phase shift control.
• 4'd0: default
• 4'd1: default + 1/clk delay
• 4'd2: default + 2/clk delay
• 4'd3: default + 3/clk delay
• 4'd4: default + 4/clk delay
• 4'd5: default + 5/clk delay
• 4'd6: default + 6/clk delay
• 4'd7: default + 7/clk delay
• 4'd8: default + 8/clk delay
• 4'd9: default + 9/clk delay
• 4'd10: default + 10/clk delay
• 4'd11: default + 11/clk delay
• 4'd12: default + 12/clk delay
• 4'd13: default + 13/clk delay
• 4'd14: default + 14/clk delay
• 4'd15: default + 15/clk delay

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ES9018S Product Datasheet

Register 25: DPLL MODE CONTROL

Bits [7:2] [1] [0]
Default 6'd0 1'b1 1'b0

Bits Mnemonic Description

[7:2] RESERVED NA
[1] DPLL_BW_DEFAULTS DPLL default bandwidth settings.
• 1'b1: Use the best DPLL_BANDWIDTH settings.
• 1'b0: Allow all settings
[0] DPLL_BW_128X • 1'b1: Multiply the DPLL_BANDWIDTH setting by 128
• 1'b0: Use the DPLL_BANDWIDTH setting
• 1'b1: Multiply the DPLL_BANDWIDTH setting by 128

Register 26: RESERVED

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ES9018S Product Datasheet

Read Only Registers

Bits Mnemonic Description

[7:4] RESERVED NA
[3] DSD_PCM DSD or PCM status bit.
• 1'b1: DSD mode
• 1'b0: I2S or SPDIF mode
[2] SPDIF_VALID Valid SPDIF data status bit.
• 1'b1: The SPDIF data is valid
• 1'b0: The SPDIF data is invalid
[1] SPDIF_EN SPDIF enabled status bit.
• 1'b0: SPDIF mode is currently disabled.
• 1'b1: SPDIF mode is currently enabled.
Note: This can be done manually by setting SPDIF_EN_R
(Register 8) or by having SPDIF_AUTODETECT enabled with
valid SPDIF data on the input.
[0] LOCK Jitter Eliminator lock status bit.
• 1'b1:The Jitter Eliminator is locked to an incoming
signal
• 1'b0: The Jitter Eliminator is not locked to an incoming
signal

Register 31-28: DPLL NUM

Bits [31:0]
Default -

Bits Mnemonic Description

[31:0] DPLL_NUM This is a read-only 32 bit value that can be used to calculate
the sample rate. The sample rate can be calculated using:
Note: Fin must be divided by 64 for I2S data.
𝐷𝑃𝐿𝐿_𝑁𝑈𝑀 ∗ 𝐹𝑐𝑟𝑦𝑠𝑡𝑎𝑙
𝐹𝑖𝑛 =
232

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ES9018S Product Datasheet

Read Write Registers

Bits Mnemonic Description

[7:6] RESERVED NA
[5] STAGE1_PROG_COEFF_ENABLED Stage 1 FIR filter custom coefficient control.
• 1'b1: The stage 1 interpolating FIR filter will use the
downloaded (custom) coefficients.
• 1'b0: The stage 1 interpolating FIR filter will use the
built-in coefficients
[4] STAGE1_PROGRAMMING_ENABLED Stage 1 coefficients write enable.
• 1'b1: The stage 1 coefficients are set for writing. This
bit must be enabled prior to programming the stage 1
FIR coefficients.
• 1'b0: The stage 1 coefficients are not set for writing
[3:2] RESERVED NA
[1] STAGE2_PROG_COEFF_ENABLED Stage 2 FIR filter custom coefficient control.
• 1'b1: The stage 2 FIR filter will use the downloaded
(custom) coefficients.
• 1'b0: The stage 2 FIR filter will use the built-in
coefficients.
[0] STAGE2_PROGRAMMING_ENABLED Stage 2 coefficients write enable.
• 1'b1: The stage 2 coefficients are set for writing. This
bit must be enabled prior to programming the
RESERVED.
• 1'b0: The stage 2 coefficients are not set for writing.

Register 41-38: STAGE 1 FIR COEFFICIENTS

Bits [31:0]
Default -

Bits Mnemonic Description

[31:0] STAGE1_FIR_COEFFICIENTS These 32 bits are used for writing the stage 1 FIR coefficients.
See the programming section for more information.

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ES9018S Product Datasheet

Register 45-42: STAGE 2 FIR COEFFICIENTS

Bits [31:0]
Default -

Bits Mnemonic Description

[31:0] STAGE2_FIR_COEFFICIENTS These 32 bits are used for writing the stage 1 FIR coefficients.
See the programming section for more information.

Register 71-48: SPDIF CHANNEL STATUS DATA

Bits [191: 0]
Default -

Bits Mnemonic Description

[191: 0] SPDIF_CHANNEL_STATUS_DATA These registers allow read back of the SPDIF channel status.
The status definition is different for the customer configuration
(Table 7) and professional configuration (Table 8)

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ES9018S Product Datasheet

SPDIF CHANNEL STATUS - Consumer configuration (Base Address = 48)

Address [7] [6] [5] [4] [3] [2] [1] [0]
Offset

0 Reserved Reserved 0: 2Channel Reserved 0: No-Preemph 0: Copyright 0: Audio 0: Consumer

1: 4Channel 1: Pre-emphasis 1: Non-Copyright 1: Data 1: Professional

1 Category Code
0x00: General
0x01: Laser-Optical
0x02: D/D Converter
0x03: Magnetic
0x04: Digital Broadcast
0x05: Musical Instrument
0x06: Present A/D Converter
0x08: Solid State Memory
0x16: Future A/D Converter
0x19: DVD
0x40: Experimental

3 Reserved Reserved Clock Accuracy Sample Frequency

0x0:Level 2 1000ppm 0x0: 44.1k
0x1:Level 1 50ppm 0x2: 48k
0x2:Level 3 variable pitch shifted 0x3: 32k
0x4: 22.05k
0x6: 24k
0x8: 88.2k
0xA: 96k
0xC: 176.4k
0xE: 192k

4 Reserved Reserved Reserved Reserved Word Length: Word Field Size

5-23 Reserved

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ES9018S Product Datasheet

SPDIF CHANNEL STATUS - Professional configuration (Base Address = 48)

Address [7] [6] [5] [4] [3] [2] [1] [0]
Offset

0 sampling frequency: lock: emphasis: 0: Audio 0: Consumer

00: not indicated (or see byte 4) 0: locked 000: Emphasis not indicated 1: Non-audio 1: Professional
10: 48kHz 1: unlocked 001: No emphasis
01: 44.1kHz 011: CD-type emphasis
11: 32kHz 111: J-17 emphasis

1 User bit management: Channel mode:

0000: no indication 0000: not indicated (default to 2 channel)
1000: 192-bit block as channel status 1000: 2 channel
0100: As defined in AES18 0100: 1 channel (monophonic)
1100: user-defined 1100: primary / secondary
0010: As in IEC60958-3 (consumer) 0010: stereo
1010: reserved for user applications
0110: reserved for user applications
1110: SCDSR (see byte 3 for ID)
0001: SCDSR (stereo left)
1001: SCDSR (stereo right)
1111: Multichannel (see byte 3 for ID)

2 alignment level: Source Word Length: Use of aux sample word:

00: not indicated If max=20bits |If max=24bits 000: not defined, audio max 20 bits
10: –20dB FS 000=Not indicated |000=Not indicated 100: used for main audio, max 24 bits
01: –18.06dB FS 100 = 23bits |100 = 19bits 010: used for coord, audio max 20 bits
010 = 22bits |010 = 18bits 110: reserved
110 = 21bits |110 = 17bits
001 = 20bits |001 = 16bits
101 = 24bits |101 = 20bits

3 Channel identification:
if bit 7 = 0 then channel number is 1 plus the numeric value of bits 0-6 (bit reversed).
if bit 7 = 1 then bits 4–6 define a multichannel mode and bits 0–3 (bit reversed) give the channel number within that mode.

4 fs scaling: Sample frequency (fs): Reserved DARS (Digital audio reference signal):
0: no scaling 0000: not indicated 00: not a DARS
1: apply factor of 0001: 24kHz 01: DARS grade 2 (10ppm)
1 / 1.001 to value 0010: 96kHz 10: DARS grade 1 (1ppm)
1001: 22.05kHz 11: Reserved
1010: 88.2kHz
1011: 176.4kHz
0011: 192kHz
1111: User defined

5 Reserved

6-9 alphanumerical channel origin: four-character label using 7-bit ASCII with no parity. Bits 55, 63, 71, 79 = 0.

10-13 alphanumerical channel destination: four-character label using 7-bit ASCII with no parity. Bits 87, 95, 103, 111 = 0.

14-17 local sample address code: 32-bit binary number representing the sample count of the first sample of the channel status block.

18-21 time of day code: 32-bit binary number representing time of source encoding in samples since midnight

22 reliability flags
0: data in byte range is reliable
1: data in byte range is unreliable

23 CRCC
00000000: not implemented
X: error check code for bits 0–183

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 36
2.3

ES9018S Product Datasheet

FIR Programmable Filters

The SABRE32 Reference has a two-stage interpolating filter with both built-in and programmable coefficients. Each stage can be programmed and
enabled independently. Each channel can also have a different filter per stage.

Each stage of the FIR filter either uses the built-in coefficients, or the programmable coefficients. Register 37 bits 5 and 1 are used for setting the
filter coefficient sources.

Programming the filter requires passing every coefficient for all 8 channels to the SABRE32 Reference via I2C. Stage 1 and Stage 2 must be
programmed independently. Programming starts by enabling the appropriate enable_programming bit in register 37.

The FIR can only be programmed when DATA_CLK is available and when the DAC is locked.

To program stage 1, bit 4 of register 37 must be set high. Then the 32bit coefficients are written to registers 41 (Bits [31:24]), 40 (Bits[23:16]), 39
(Bits[15:8]), 38 (Bits[7:0]) in that order. The first write to these 4 consecutive register is the 32-bit value for Channel1, coefficient1. The next write to
these 4 consecutive registers is the 32-bit value for Channel2, coefficient1. After 8 writes to these 4 consecutive registers, coefficient 2 for all 8 filters
is ready to be input. There are 64 coefficients to write for Stage 1. So that is 4 bytes per coefficient, 8 channels and 64 coefficients for a total of
2048 bytes to program the stage 1. Once complete, zero must be written to register 38. Bit 4 of register 37 must then be set low to finalize the
programming.

To program stage 2, bit 0 of register 37 must be set high. Then the 32bit coefficients are written to registers 45 (Bits [31:24]), 44 (Bits [23:16]), 43
(Bits [15:8]), 42 (Bits [7:0]), in that order. The first write to these 4 consecutive register is the 32-bit value for Channel1, coefficient1. The next write
to these 4 consecutive registers is the 32-bit value for Channel2, coefficient1. After 8 writes to these 4 consecutive registers, coefficient 2 for all 8
filters is ready to be input. There are 16 coefficients to write for Stage 2. So that is 4 bytes per coefficient, 8 channels and 16 coefficients for a total
of 512 bytes to program the stage 1. Once complete, zero must be written to register 42. Bit 0 of register 37 must then be set low to finalize the
programming.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 37
2.3

ES9018S Product Datasheet

C++ Sample Code for writing custom coefficients to either stage.

void CLoadCoeffDlg::ProgramStage(int nStage)
{
BYTE WE;
BYTE WritePort[4];
BYTE WriteData[4];
int nTotal;
if(nStage==0){ //programming stage 1
WE=0x10;
WritePort[0]=41;
WritePort[1]=40;
WritePort[2]=39;
WritePort[3]=38;
nTotal=64;
}
else{ //programming stage 2
WE=0x01;
WritePort[0]=45;
WritePort[1]=44;
WritePort[2]=43;
WritePort[3]=42;
nTotal=16;
}
if(!m_pParent->WriteRegisters(1, 37, &WE))
return;
for(int nCIndex=0; nCIndex<nTotal; nCIndex++){
for(int nCh=0; nCh<8; nCh++){
DWORD nCoeff;
if(nStage==0)
nCoeff=CoeffCh[nCh].CoeffStage1[nCIndex];
else
nCoeff=CoeffCh[nCh].CoeffStage2[nCIndex];
WriteData[0]=(BYTE)(nCoeff>>24)&0xff;
WriteData[1]=(BYTE)((nCoeff>>16)&0xff);
WriteData[2]=(BYTE)((nCoeff>>8)&0xff);
WriteData[3]=(BYTE)((nCoeff)&0xff);
if(!m_pParent->WriteRegisters(4, WritePort, WriteData))
return;
}
}
WE=0x00;
if(nStage == 0) WriteRegisters(1, 38, &WE);
else if(nStage == 1) WriteRegisters(1, 42, &WE);
if(!m_pParent->WriteRegisters(1, 37, &WE));
}

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 38
2.3

ES9018S Product Datasheet

Application Diagrams
Recommended Differential, Current-Mode External Op-Amp Circuit

Figure 7 - Recommended Differential, Current-Mode External Op-Amp Circuit

ES9018 Stereo Quad-differential Current Mode

(DNR: 133dB, THD: –120dB)

Figure 8 - Sabre 32 Reference DAC in stereo “quad-differential” current mode

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 39
2.3

ES9018S Product Datasheet

(DNR: 129dB, THD: –120dB)

Figure 9 - Sabre32 Reference DAC in 8-Channel differential current mode

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 40
2.3

ES9018S Product Datasheet

Absolute Maximum Ratings

PARAMETER RATING
Storage temperature –65C to +105C
Voltage range for 5V tolerant pins –0.5V to +5.5V
–0.5V to (DVCC_T+0.5V) or
Voltage range for all other pins
–0.5V to (DVCC_B+0.5V)
Table 9 – Absolute Maximum Ratings

WARNING: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended
periods may affect device reliability.
WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.

Recommended Operating Conditions

PARAMETER SYMBOL CONDITIONS
Operating temperature TA 0C to 70C
Digital core supply voltage VDD 1.2V  5%, 37mA nominal (Note 1)
Digital power supply voltage DVCC_T, DVCC_B 3.3V  5%, 7mA nominal (Note 1)
Analog power supply voltage AVCC_L, AVCC_R 3.3V  5%, 25mA nominal (Note 1)
Table 10 - Recommended Operating Conditions

Note: fs = 48kHz, MCLK = 40MHz, I2S input, output unloaded

DC Electrical Characteristics
SYMBOL PARAMETER MIN MAX UNIT COMMENTS
DVCC_T or All inputs TTL levels except CLK
2.0 V
VIH High-level input voltage DVCC_B and 5V tolerant input pins
2.0 5.5 V All 5V tolerant inputs
VIL Low-level input voltage –0.3 0.8 V All input TTL levels except CLK
VCLKH CLK high-level input 2.0 DVCC_B+0.25 V
TTL level input
VCLKL CLK low-level input –0.3 0.8 V
VOH High-level output voltage 3.0 V IOH = 1mA
VOL Low-level-output voltage 0.45 V IOL = 4mA
ILI Input leakage current 15
A
ILO Output leakage current 15
CIN Input capacitance 10
pF fc = 1MHz
CO Input/output capacitance 12
CCLK CLK capacitance 5 pF fc = 1MHz
Table 11 - DC Electrical Characteristics

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 41
2.3

ES9018S Product Datasheet

MCLK Timing
tMCH

MCLK
tMCL
tMCY

Parameter Symbol Min Max Unit

MCLK pulse width high TMCH 4.5 ns
MCLK pulse width low TMCL 4.5 ns
MCLK cycle time TMCY 10 ns
MCLK duty cycle 45:55 55:45

Audio Interface Timing

tDCY

DATA_CLK
tDCH tDCL

tDH tDS

DATA[8:1] Valid Invalid Valid

Parameter Symbol Min Max Unit

DATA_CLK pulse width high tDCH 4.5 ns
DATA_CLK pulse width low tDCL 4.5 ns
DATA_CLK cycle time tDCY 10 ns
DATA_CLK duty cycle 45:55 55:45
DATA set-up time to DATA_CLK rising edge tDS 2 ns
DATA hold time to DATA_CLK rising edge tDH 2 ns

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 42
2.3

ES9018S Product Datasheet

Recommended Power-Up Sequence

The ES9018S must be reset after power-up to ensure correct operation. Reset can be performed using a reset controller in some configurations or
via a system software reset. The active-HI reset pin provides a high input-impedance with no internal pull-up or pull-down. To reset the ES9018S,
the reset input should be pulled high for a minimum of 1ms after all external power supplies (and XI/MCLK if supplied externally) are stabilized.
Following the reset signal, the input can be held low indefinitely.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 43
2.3

ES9018S Product Datasheet

Analog Performance
Test Conditions (unless otherwise stated)
1. TA = 25oC, AVCC = +3.3V, DVCC = +1.2V, fs = 44.1kHz, MCLK = 27MHz and 32-bit data
2. SNR/DNR: A-weighted over 20Hz-20kHz in averaging mode
3. THD+N: un-weighted over 20Hz-20kHz bandwidth

PARAMETER CONDITIONS MIN TYP MAX UNIT

Resolution 32 Bits
> 192 x Fs (for Fs  200kHz)
MCLK (PCM normal mode) Hz
> 256 x Fs (200kHz < Fs  384kHz)
MCLK (PCM OSF bypass mode) > 24 x Fs Hz
MCLK (DSD mode) > 3 x Fs Hz
MCLK (SPDIF mode) > 386 x Fs Hz
DYNAMIC PERFORMANCE
DNR (mono differential current mode) –60dBFS 135 dB-A
DNR (stereo differential current mode) –60dBFS 133 dB-A
DNR (8-Ch differential current mode) –60dBFS 129 dB-A
DNR (8-Ch differential voltage mode) –60dBFS 120 dB-A
THD+N (differential current mode) 0dBFS –120 dB
THD+N (differential voltage mode) 0dBFS –108 dB
MCLK > 192 x Fs 200
PCM sampling freq (Fs, normal mode) kHz
MCLK > 256 x Fs 384
PCM sampling freq (Fs, OSF bypass) MCLK > 24 x Fs 1.536 MHz
ANALOG OUTPUT
3.05
Differential (+ or –) voltage output range Full-scale out Vp-p
(0.924 x AVCC)
1.65
Differential (+ or –) voltage output offset Bipolar zero out V
(AVCC / 2)
Differential (+ or –) current output range
Full-scale out 3.903 mAp-p
(Note *1)
Bipolar zero out
Differential (+ or –) current output offset 2.112 – (1000 x Vg) /
to virtual ground mA
(Note *1) 834
at voltage Vg (V)
Digital Filter Performance
De-emphasis error 0.2 dB
Mute Attenuation 127 dB

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 44
2.3

ES9018S Product Datasheet

PCM Filter Characteristics (Sharp Roll Off)

0.003dB 0.454 x fs Hz
Pass band
–3dB 0.49 x fs Hz
Stop band < –115dB 0.546 x fs Hz
Group Delay 35 / fs s
PCM Filter Characteristics (Slow Roll Off)
0.05dB 0.308 x fs Hz
Pass band
–3dB 0.454 x fs Hz
Stop band < –100dB 0.814 x fs Hz
Group Delay 6.25 / fs s
DSD Filter Characteristics
Pass band –3dB 50 / 60 / 70 kHz
Stop band attenuation 18 dB/oct
Table 12 - Analog Performance

Note
*1. Differential (+ or –) current output is equivalent to a differential (+ or –) voltage source in series with an 834 11% resistor. The
differential (+ or –) voltage source has a peak-to-peak output range of (0.924 x AVCC) = 3.05V and an output offset of (AVCC / 2) = 1.65V
with a 3.3V AVCC.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 45
2.3

ES9018S Product Datasheet

PCM DE-EMPHASIS FILTER RESPONSE (32kHz)

Table 13 - PCM DE-EMPHASIS FILTER RESPONSE (32kHz)

PCM DE-EMPHASIS FILTER RESPONSE (44.1kHz)

Table 14 - PCM DE-EMPHASIS FILTER RESPONSE (44.1kHz)

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 46
2.3

ES9018S Product Datasheet

PCM DE-EMPHASIS FILTER RESPONSE (48kHz)

Table 15 - PCM DE-EMPHASIS FILTER RESPONSE (48kHz)

PCM Sharp Roll-Off Filter Response

Figure 10 - PCM Sharp Roll-Off Filter Response

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 47
2.3

ES9018S Product Datasheet

PCM Slow Roll-Off Filter Response

Figure 11 - PCM Slow Roll-Off Filter Response

DSD Filter Response

Figure 12 - DSD Filter Response

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 48
2.3

ES9018S Product Datasheet

64-Pin LQFP Mechanical Dimensions

D
D1

E1
E

Pin 1

A1 L b e L1
e1

MILLIMETERS
Symbol Description Min. Nom. Max.
D Lead-to Lead, X-axis 11.75 12.00 12.25
D1 Package's Outside, X-axis 9.90 10.00 10.10
E Lead-to Lead, Y-axis 11.75 12.00 12.25
E1 Package's Outside, Y-axis 9.90 10.00 10.10
A1 Board Standoff 0.05 0.10 0.15
A2 Package Thickness 1.35 1.40 1.45
b Lead Width 0.17 0.22 0.27
e Lead Pitch 0.50 BSC
e1 Lead Gap 0.23 0.28 0.33
L Foot Length 0.45 0.60 0.75
L1 Lead Length 1.00
Co-planarity 0.102
Foot Angle 0º 7º
No. of Leads in X-axis 16
No. of Leads in Y-axis 16
No. of Leads Total 64
Package Type LQFP

Figure 13 - 64-Pin LQFP Mechanical Dimensions

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 49
2.3

ES9018S Product Datasheet

Reflow Process Considerations

For lead-free soldering, the characterization and optimization of the reflow process is the most important factor you need to consider.
The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperature of 235°C to ensure good wetting. The
maximum reflow temperature is in the 245°C to 260°C range, depending on the package size (Table RPC-2). This narrows the process window for
lead-free soldering to 10°C to 20°C.
The increase in peak reflow temperature in combination with the narrow process window makes the development of an optimal reflow profile a
critical factor for ensuring a successful lead-free assembly process. The major factors contributing to the development of an optimal thermal profile
are the size and weight of the assembly, the density of the components, the mix of large and small components, and the paste chemistry being used.
Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other critical locations on the
board to ensure that all components are heated to temperatures above the minimum reflow temperatures and that smaller components do not
exceed the maximum temperature limits (Table RPC-2).

To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by ESS are based on the
JEDEC/IPC standard J-STD-020 revision D.1.

Figure 14 - IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)

Note: Reflow is allowed 3 times. Caution must be taken to ensure time between re-flow runs does not exceed the allowed time by the moisture sensitivity label. If
the time elapsed between the re-flows exceeds the moisture sensitivity time bake the board according to the moisture sensitivity label instructions.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 50
2.3

ES9018S Product Datasheet

Manual Soldering
Allowed up to 2 times with maximum temperature of 350 degrees no longer than 3 seconds.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 51
2.3

ES9018S Product Datasheet

RPC-1 Classification reflow profile

Profile Feature Pb-Free Assembly
Preheat/Soak
Temperature Min (Tsmin) 150°C
Temperature Max (Tsmax) 200°C
Time (ts) from (Tsmin to Tsmax) 60-120 seconds
Ramp-up rate (TL to Tp) 3°C / second max.
Liquidous temperature (TL) 217°C
Time (tL) maintained above TL 60-150 seconds
For users Tp must not exceed the classification temp in Table RPC-
2.
Peak package body temperature (Tp)
For suppliers Tp must equal or exceed the Classification temp in
Table RPC-2.
Time (tp)* within 5°C of the specified
classification temperature (Tc), see Figure 30* seconds
RPC-1
Ramp-down rate (Tp to TL) 6°C / second max.
Time 25°C to peak temperature 8 minutes max.
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Table 16 - RPC-1 Classification reflow profile

Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug). If parts are reflowed in other
than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ±2°C of the live-bug Tp and still meet the Tc requirements, otherwise, the profile shall
be adjusted to achieve the latter. To accurately measure actual peak package body temperatures refer to JEP140 for recommended thermocouple use.
Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly profiles should be developed
based on specific process needs and board designs and should not exceed the parameters in Table RPC-1.
For example, if Tc is 260°C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260°C. The time above 255°C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260°C. The time above 255°C must not exceed 30 seconds.classification profile requirements.

RPC-2 Pb-Free Process - Classification Temperatures (Tc)

Package Thickness Volume mm3, <350 Volume mm3, 350 to 2000 Volume mm3, >2000
<1.6 mm 260°C 260°C 260°C
1.6 mm - 2.5 mm 260°C 250°C 245°C
>2.5 mm 250°C 245°C 245°C
Table 17 - RPC-2 Pb-Free Process - Classification Temperatures (Tc)

Note 1: At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the values specified in Table
RPC-2. The use of a higher Tp does not change the classification temperature (Tc).
Note 2: Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or non-integral heat sinks.
Note 3: The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes reduces the thermal gradients
between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 52
2.3

ES9018S Product Datasheet

Ordering Information
Part Number Description Package
ES9018S Sabre32 Reference 8-channel Audio DAC 64-pin LQFP

The letter S at the end of the part number identifies the package type LQFP.
Table 18 - Ordering Information

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 53
2.3

ES9018S Product Datasheet

Revision History
Revision Date Notes
Initial January 21, 2009 Initial version
Update Register #15 default value
Update Audio Interface Timing
1.0 January 23, 2009
Update Level Linearity Error Performance
Add details to FIR Programmable Filters and Registers sections
1.1 March 13, 2009 Add ES9012
1.2 February 11, 2010 Corrected Sample Rate Calculation formula
1.21 July 26, 2012 Update feature table
Update Analog Performance table
– Maximum PCM sampling frequency
1.22 December 12, 2012 Update I2C compatible modes
Update 5V tolerant pins. Update pinout.
Update PCM Audio Interface Diagram
1.23 April 11, 2013 Correct I2C description
1.3 July 16, 2013 Add reflow profile
1.31 September 19, 2013 Correct typos and timing diagrams
1.4 June 6, 2014 Added SABRE SOUNDTM trademark
Updated ESS’ FAX number. Added medical liabilities disclaimer.
Clarified polarity of RESET input, pin 8, on page 4.
1.5 July 15, 2014
Updated supported sampling rates. ES2012 removed.
Recommended power-up sequence, timing diagram added to page 27
1.6 July 22, 2014 Pages 23 and 24, corrected the polarity of U2 on two circuit diagrams
1.7 September 16, 2014 Updated DAC output resistance from 781.25 to 834 ±11%
1.8 January 22, 2015 Cleaned up formatting and corrected typos.
1.9 February 18, 2015 Corrected formulae on Analog Performance table.
Removed incorrect note from cover page.
1.91 March 18, 2015
Updated ESS Technology contact information.
2.0 February 16, 2016 Added I2C interface timing table
2.1 March 16, 2016 Changed CCLK input capacitance from 20pF max. to 5pF max.
2.2 May 4, 2016 Pin 24 on the pin layout diagram was erroneously marked as pin 34
2.3 August 9, 2021 Formatting changes

ESS IC’s are not intended, authorized, or warranted for use as components in military applications, medical devices or life support systems. ESS assumes no liability and disclaims
any expressed, implied or statutory warranty for use of ESS IC’s in such unsuitable applications.

No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise,
without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications
are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 54

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