ABIT AN52 [NFORCE MCP68] SOCKETAM2 V.0.1

8 7 6 5 4 3 2 1
1 COVER
2 BLOCK DIAGRAM
3 RESET MAP
4 CLOCK DIAGRAM
D
5 GPIO TABLE D
6 PCI DEVICE TABLE / VID TABLE

7 AM2 940 K8CPU PART 1
12 CPU DECOUPLING
13 DDR ADD/CTL TERMINATION
14 DDR DIMM 0
15 DDR DIMM 1
C
16 DDR DIMM 2 C
17 DDR DIMM 3
18 MCP68 HT/CLKS
19 MCP68 PEX X16
20 MCP68 PEX X1/RGMII/HDMI/DAC
21 MCP68 PCI
22 MCP68 SATA / IDE
23 MCP68 AUDIO / USB / MISC
24 MCP68 PWR / GND
AN52
25 MCP68 DECOUPLING/SPI
26 PCI EXPRESS X16 CONNECTOR
27 PCI EXPRESS X1 CONNECTOR
B B
28 PCI CONNECTOR 1-2
29 PCI TERMINATION/DECOUPLING
30 SIO-W83627DHG
31 Ti43AB22A-1394
࣭
ऌ
ं
ऑࢽ
࣠
ँ
࣪
࣍
32 GBIT LAN PHY 88E1116
ए
इ
ऀ
ऌ
ं
ࣔ
࣎
33 AUDIO ALC888
34 PWM RT8801 & RT9605
35 W83303AG
36 C51/MCP51 CORE&DDRII
37 PWR CON/F-PNL/VBAT/SPKR
38 PWR SEQU & VID BUFFER
39 OVP/FAN/CPU CHANGE
A
40
41
ACPI VREG
RGB & HDMI PORT
MCP65 CRB ATX A
42 USB+RJ45/1394 CONN
43 DAC & DVI
44 K/M+FLASH+FDC+FP-USB
45 MEM VDD/MEM VTT/LAN
46 IDE 1/2 Title
47 MCP68 CORE-AUX-HT-VREGS COVER

Size Document Number Rev
48 MOUNTING HOLES Custom AN52 V0.1
Date: Friday, March 02, 2007 Sheet 1 of 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BLOCK DIAGRAM
POWER
D
SUPPLY VREG D
CONNECTOR
128-BIT 400/533/667/800MHZ
AM2 SOCKET 940 DDRII SDRAM CONN 0
THERM MONITOR
DDRII SDRAM CONN 1
DDRII SDRAM CONN 2

HT 16X16 1GHZ
PCI EXPRESS DDRII SDRAM CONN 3
PEX X16
PCI EXPRESS
PEX X1
C PCI 33MHZ C
PCI SLOT 1
NFORCE
HDA 7.1 AUDIO
MCP68 PCI SLOT 2
ALC888
692 BGA RGB
RGB
ATA 133 HDMI

HDMI
PRIMARY IDE
INTEGRATED SATA CONTROLLERS (X2) X12 USB2 BACK PANEL CONN

X4 - SATA CONN
USB2 PORTS 4-5
X2/GBIT LAN
B B
USB2 PORTS 0-3
FRONT PANEL HDR
USB2 PORTS 6-7

FLOPPY CONN
PS2/KBRD CONN
USB2 PORTS 8-9
SIO LPC BUS 33MHZ
PARALLEL CONN
W83627DHG
LPC HDR
SERIAL CONN
MII/RGMII MII/RGMII
A 4MB FLASH A
88E1116
TPM
Title
BLOCK DIAGRAM
Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AM2 SOCKET 940
CPU PWRGD
D
D
CPU RST*
PE_RESET* HT MCP RST* HT_MCP_RST*
HT MCP PWRGD HT_MCP_PWRGD

RESET MAP
PEX0 X16
C C
PEX1 X1
MCP68/65
PWR SWTCH
SIO
B B
PWR CONN PSIN* PSOUT* PWRBTN* PWR BUTTON
PS ON SLP_S3* SLP S3* PCI RST0* PCIRST_SLOT1*

PSON* SUSB*
PCI RST1* PCIRST_SLOT2*
PWR GOOD POWER_GOOD PWRGD
PCI RST2*
PCI RST3* PCIRST_IDE*
LPC_RST* LPCRST_FLASH*
PWRGD SB PWRGD_SB PWRGD_SB
LPCRST_SIO*
CIRCUIT
MIIRESET* HDA_RESET*
SIO FLASH PRI IDE PCI SLOT 2 PCI SLOT 1
A A
LAN_PHY AUDIO_PHY
RESET* RESET*
Title
RESET MAP
Custom AN-M2 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AM2 SOCKET 940

CHANNEL A0 0-63
HT_CPU_TXCLK0 MEMORY_A0_CLK[2:0] DIMM 0
HT_CPU_TXCLK0* MEMORY_A0_CLK[2:0]*
HT_CPU_RXCLK0
HT_CPU_RXCLK0* MEMORY_B0_CLK[2:0]
D MEMORY_B0_CLK[2:0]* DIMM 1 D
HT_CPU_TXCLK1 CHANNEL B0 64-127
HT_CPU_TXCLK1*
HT_CPU_RXCLK1
HT_CPU_RXCLK1* CHANNEL A1 0-63
MEMORY_A1_CLK[2:0] DIMM 2
MEMORY_A1_CLK[2:0]*
CPUCLK_IN* MEMORY_B1_CLK[2:0]
CPUCLK_IN MEMORY_B1_CLK[2:0]* DIMM 3
CHANNEL B1 64-127
CLKOUT_200MHZ PE0_REFCLK
CLKOUT_200MHZ* PE0_REFCLK* PE0 X16
C C
HT_CPU_RXCLK1*
HT_CPU_RXCLK1 PE1_REFCLK
HT_CPU_TXCLK1* PE1_REFCLK* PE1 X1
HT_CPU_TXCLK1
HT_CPU_RXCLK0*
HT_CPU_RXCLK0
HT_CPU_TXCLK0*
HT_CPU_TXCLK0
14MHZ OR 24MHZ*
BUF_SIO
MCP68/65 SIO
LPC_CLK0 PCI SLOT 1
PCI_CLK0
PCI_CLK1
B PCI_CLK2 B
PCI_CLK3 PCI SLOT 2
PCI_CLK4
PCI_CLKIN
TPM
LPC_CLK1
FLASH LPC
HDA_BITCLK HDA HEADER
CODEC
32.0 KHZ RTC_XTAL
XTAL_IN RGMII_TXCLK
RGMII_RXCLK LAN
25 MHZ PHY
A BUF_25MHZ A
XTAL_OUT
Title
CLOCK DIAGRAM
Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1 SIO_PSIN* FPIO
D
PWR_ON POWER UPழऱ೯‫܂‬ D
PSIN#/GP56(68)
CPUVDD_EN 10
PWRBTN* 2 CPUVDD_EN(J2) CPUVDD_EN(12)
PSOUT#/GP57(67) PWRBTN*(G4)
CPU_VLD(J1) 12 CPU_VLD CPU_VLD(4)
W83627DHG SLP_S3*(G8) MCP55
MCPVDD/HT_EN(J4) RT8801
MEMVLD(J3)
PSON#
SLP_S5*(H8) PWRGD MCPVDD/HT_VLD(H3)
C 3 4 9 15 C
S5# MEMVLD MCP55_PWRGD HT_VLD 11

5
VCCP
RT9605B
S3# SEQ SEQ SEQ
V1P2_HT 14
S5# 5VDRV LR1_DRV

B B
S3# 13 HTVDD_EN
LR1_SEN
PS_IN#
W83304CG
PWRGD PWRGD_PS 8
PWRGD
ATX FAULT#
PS_ON* 6 W83303AD_PS_OUT* PS_OUT*
Power Supply 7
A A
Title
POWER SEQ MAP

Custom AN52 V0.1
8 7 6 5 4 3 2 1
(14.1A) RT8801B+RT9605A
VCC12A VCCP(1.35V) CPU
(100A)
108N03(3)+108N03*2(3)
(6.45A)
VCC12 VCC12 PCI/3 FAN/4 PCIEx16/1 PCIEx1/2

(1.5A) (1.2A) (2.75A) (1A)
(8.15A)
PCI/1 PCIEx16/1 PCIEx1/2 MCP65S ALC622
(1.5A) (3A) (3A) (0.62A) (0.03A)
(14.05A)
(1.2A) W83304CG
VCC3 VCC3 V1P2_LDT CPU/MCP65S
PHD55N03 (0.5A) (0.7A)
(3.38A) W83320 V1P2 MCP65S

PHD55N03(2) (6.75A)
(0.23A) W83304CG V1P2_DUAL MCP65S

55N03(1) (0.23A)
(1.32A)
(6.71A) W83304CG
(1.09A)
VCC5SB VCC5SB (0.53A) 3VDUAL MCP65S 88E3018 88E8056
PHD55N03(2) (0.56A) (0.01A) (0.52A)
(2A)
(1.25A)
W83310 VTT_MEM DIMM/4
(0.04A) (2A)
RT9179 ALC622 (15.25A)
(0.038A)
(6.87A) W83320 (14A)
VDD_MEM DIMM/4
PHD55N03(2) (14A)
(1.8V)
(0.10A)
RC1117ST V2P5_DUAL_LAN 88E3018
(0.10A)
(13.01A)
(6.14A)
W83304CG 5VDUAL (6.04A) USB X10 KB/MS ALC622
(5A) (1A) (0.038mA)
(13.01A) PHD55N03(2)
(20.81A)
(0.3A)
VCC5 VCC5 RC1117ST V2P5_VDDA CPU
(0.3A)
(7.5A)
PCI/3
(7.5A)
Title
POWER DELIVERY
Custom AN52 V0.1
5 4 3 2 1
D D
V1P2_LDT CPU produce it itself
V0.1 220PF ->2200PF
1
C85 C84 C83 C82
x0.1UF/16V-LF 0.1UF/X7R/16V-LFx0.1UF/16V-LF +1.2V_HT_CPU
2200PF/X7R/16V-LF C0603 C0603 C0603 2.5 V
X5R X5R X5R
U7A
1
16V 16V 16V CT46
10% 10% 10%
SK-C940P-M2 4.7UF/0805Y/10V-LF
2
SOCKET_940_M2 C0805
?
10V
SEC 1 OF 6 10%
V_HT V_HT
2
H1 AJ1
H2 V_HT V_HT AJ2
H5 V_HT V_HT AJ3
J H6 V_HT V_HT AJ4 I
18 HTCPU_UP[15..0] HTCPU_UP[15..0] HTCPU_DWN[15..0] HTCPU_DWN[15..0] 18

15 ˛˧˖ˣ˨˲˨ˣ˄ˈ U6 HT_RXD<15> HT_TXD<15> Y5 ˛˧˖ˣ˨˲˗˪ˡ˄ˈ 15
14 ˛˧˖ˣ˨˲˨ˣ˄ˇ
T4 HT_RXD<14> HT_TXD<14> AB6 ˛˧˖ˣ˨˲˗˪ˡ˄ˇ 14
13 ˛˧˖ˣ˨˲˨ˣ˄ˆ R6 HT_RXD<13> HT_TXD<13> AB5 ˛˧˖ˣ˨˲˗˪ˡ˄ˆ 13
12 ˛˧˖ˣ˨˲˨ˣ˄˅ P4 HT_RXD<12> HT_TXD<12> AD6 ˛˧˖ˣ˨˲˗˪ˡ˄˅ 12
11 ˛˧˖ˣ˨˲˨ˣ˄˄ M4 HT_RXD<11> HT_TXD<11> AF6 ˛˧˖ˣ˨˲˗˪ˡ˄˄ 11
10 ˛˧˖ˣ˨˲˨ˣ˄˃ L6 HT_RXD<10> HT_TXD<10> AF5 ˛˧˖ˣ˨˲˗˪ˡ˄˃ 10
9 ˛˧˖ˣ˨˲˨ˣˌ
K4 HT_RXD<9> HT_TXD<9> AH6 ˛˧˖ˣ˨˲˗˪ˡˌ 9
8 ˛˧˖ˣ˨˲˨ˣˋ J6 HT_RXD<8> HT_TXD<8> AH5 ˛˧˖ˣ˨˲˗˪ˡˋ 8
7 ˛˧˖ˣ˨˲˨ˣˊ U3 HT_RXD<7> HT_TXD<7> Y1 ˛˧˖ˣ˨˲˗˪ˡˊ 7
C 6
5
˛˧˖ˣ˨˲˨ˣˉ
˛˧˖ˣ˨˲˨ˣˈ
R1
R3
HT_RXD<6>
HT_RXD<5>
HT_TXD<6>
HT_TXD<5>
AA2
AB1
˛˧˖ˣ˨˲˗˪ˡˉ
˛˧˖ˣ˨˲˗˪ˡˈ
6
5
C
4 ˛˧˖ˣ˨˲˨ˣˇ
N1 HT_RXD<4> HT_TXD<4> AC2 ˛˧˖ˣ˨˲˗˪ˡˇ 4
3 ˛˧˖ˣ˨˲˨ˣˆ L1 HT_RXD<3> HT_TXD<3> AE2 ˛˧˖ˣ˨˲˗˪ˡˆ 3
2 ˛˧˖ˣ˨˲˨ˣ˅ L3 HT_RXD<2> HT_TXD<2> AF1 ˛˧˖ˣ˨˲˗˪ˡ˅ 2
1 ˛˧˖ˣ˨˲˨ˣ˄ J1 HT_RXD<1> HT_TXD<1> AG2 ˛˧˖ˣ˨˲˗˪ˡ˄ 1
0 ˛˧˖ˣ˨˲˨ˣ˃ J3 HT_RXD<0> HT_TXD<0> AH1 ˛˧˖ˣ˨˲˗˪ˡ˃ 0
18 HTCPU_UP*[15..0] HTCPU_UP*[15..0] HTCPU_DWN*[15..0] HTCPU_DWN*[15..0] 18

15 ˛˧˖ˣ˨˲˨ˣʽ˄ˈ V6 HT_RXD<15>* HT_TXD<15>* Y4 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˈ 15
14 ˛˧˖ˣ˨˲˨ˣʽ˄ˇ T5 HT_RXD<14>* HT_TXD<14>* AA6 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˇ 14
13 ˛˧˖ˣ˨˲˨ˣʽ˄ˆ T6 HT_RXD<13>* HT_TXD<13>* AB4 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˆ 13
12 ˛˧˖ˣ˨˲˨ˣʽ˄˅ P5 HT_RXD<12>* HT_TXD<12>* AC6 ˛˧˖ˣ˨˲˗˪ˡʽ˄˅ 12
11 ˛˧˖ˣ˨˲˨ˣʽ˄˄ M5 HT_RXD<11>* HT_TXD<11>* AE6 ˛˧˖ˣ˨˲˗˪ˡʽ˄˄ 11
10 ˛˧˖ˣ˨˲˨ˣʽ˄˃ M6 HT_RXD<10>* HT_TXD<10>* AF4 ˛˧˖ˣ˨˲˗˪ˡʽ˄˃ 10
9 ˛˧˖ˣ˨˲˨ˣʽˌ K5 HT_RXD<9>* HT_TXD<9>* AG6 ˛˧˖ˣ˨˲˗˪ˡʽˌ 9
8 ˛˧˖ˣ˨˲˨ˣʽˋ K6 HT_RXD<8>* HT_TXD<8>* AH4 ˛˧˖ˣ˨˲˗˪ˡʽˋ 8
7 ˛˧˖ˣ˨˲˨ˣʽˊ U2 HT_RXD<7>* HT_TXD<7>* W1 ˛˧˖ˣ˨˲˗˪ˡʽˊ 7
6 ˛˧˖ˣ˨˲˨ˣʽˉ T1 HT_RXD<6>* HT_TXD<6>* AA3 ˛˧˖ˣ˨˲˗˪ˡʽˉ 6
5 ˛˧˖ˣ˨˲˨ˣʽˈ R2 HT_RXD<5>* HT_TXD<5>* AA1 ˛˧˖ˣ˨˲˗˪ˡʽˈ 5
4 ˛˧˖ˣ˨˲˨ˣʽˇ P1 HT_RXD<4>* HT_TXD<4>* AC3 ˛˧˖ˣ˨˲˗˪ˡʽˇ 4
v0.2 W 3 ˛˧˖ˣ˨˲˨ˣʽˆ M1 HT_RXD<3>* HT_TXD<3>* AE3 ˛˧˖ˣ˨˲˗˪ˡʽˆ 3
Layout add Text 2 ˛˧˖ˣ˨˲˨ˣʽ˅ L2 HT_RXD<2>* HT_TXD<2>* AE1 ˛˧˖ˣ˨˲˗˪ˡʽ˅ 2

X 1 ˛˧˖ˣ˨˲˨ˣʽ˄ K1 HT_RXD<1>* HT_TXD<1>* AG3 ˛˧˖ˣ˨˲˗˪ˡʽ˄ 1
0 ˛˧˖ˣ˨˲˨ˣʽ˃ J2 HT_RXD<0>* HT_TXD<0>* AG1 ˛˧˖ˣ˨˲˗˪ˡʽ˃ 0
HTCPU_UPCLK0 N3 HT_RXCLK<0> HT_TXCLK<0> AD1 HTCPU_DWNCLK0

18 HTCPU_UPCLK0 HTCPU_UPCLK0* HT_RXCLK<0>* HT_TXCLK<0>* HTCPU_DWNCLK0*
HTCPU_DWNCLK0 18
N2 AC1
B 18 HTCPU_UPCLK0* HTCPU_DWNCLK0* 18 B
HTCPU_UPCLK1 N6 HT_RXCLK<1> HT_TXCLK<1> AD5 HTCPU_DWNCLK1
18 HTCPU_UPCLK1 HTCPU_UPCLK1* HT_RXCLK<1>* HT_TXCLK<1>* HTCPU_DWNCLK1*
HTCPU_DWNCLK1 18
18 HTCPU_UPCLK1* P6 AD4 HTCPU_DWNCLK1* 18
HTCPU_UPCNTL0 U1 HT_RXCTL<0> HT_TXCTL<0> W2 HTCPU_DWNCNTL0

18 HTCPU_UPCNTL0 HT_RXCTL<0>* HT_TXCTL<0>* HTCPU_DWNCNTL0*
HTCPU_DWNCNTL0 18
18 HTCPU_UPCNTL0* HTCPU_UPCNTL0* V1 W3 HTCPU_DWNCNTL0* 18
HTCPU_UPCNTL1 V4 HT_RXCTL<1> HT_TXCTL<1> Y6 HTCPU_DWNCNTL1
18 HTCPU_UPCNTL1 HT_RXCTL<1>* HT_TXCTL<1>* HTCPU_DWNCNTL1*
HTCPU_DWNCNTL1 18
18 HTCPU_UPCNTL1* HTCPU_UPCNTL1* V5 W6 HTCPU_DWNCNTL1* 18
I230
V1P2_LDT
R89
1 2
1
C81 51.1-1%-LF
0.1UF/X7R/16V-LF
R90
C0603
X5R 2 1
16V
10%
2
51.1-1%-LF
V0.1
A A
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
M2 CPU VDDA
@250mA
VCC5
U3 RC1117ST/SOT223-LF V2P5_VDDA FB3
SOT223 30 OHM/100MHz/3A/0603-LF
I V2P5_CPU_VDDA
IN(I) OUT(O) O 13000MA L0603 FB 2
D D
ADJ(I)
1
C16 CT24 C62
CT3 CT20
0805 R42 0805 C0603
X5R
C0805
?
C0603
X7R
G
4.7UF/0805Y/10V-LF 124-1%-LF R1 16V
10%
10V
10%
50V
10%
1%
2
4.7UF/0805Y/10V-LF 3900PF/X7R/16V-LF VDDMEM
0.1UF/X7R/16V-LF 4.7UF/0805Y/10V-LF V0.2
C29 R43
124-1%-LF R2 1R493 330-LF
2
1%
x0.1UF RN3-1 1 8 1K-8P4R-LF RN19-1 1 8 330-8P4R-LF
RN19-4 4 5 330-8P4R-LF
VDDMEM V0.2 330->1K RN19-3 3 6 330-8P4R-LF
RN19-2 2 7 330-8P4R-LF
RN3-3 1K-8P4R-LF U7B
3 6 SK-C940P-M2
RN3-2 2 7 1K-8P4R-LF
RN3-4 4 5 1K-8P4R-LF SOCKET_940_M2 V
SEC 2 OF 6 V0.1
V1P2_LDT K C10 VDDA THERMTRIP* AK7 CPU_THERMTRIP*
VDDA CPU_THERMTRIP* 18,43
R75 D10
1 2 PROCHOT* AL7 CPU_PROCHOT*
CPU_PROCHOT* 18
R0603 1% M N R117 0-LF
44.2-1%-LF HTCPU_RST* RESET* SID THERM_SID mcp55
18 HTCPU_RST* C7 AK6 THERM_SID 23
HTCPU_PWRGD PWROK SIC THERM_SIC mcp55
R81 18 HTCPU_PWRGD C9 AL6 THERM_SIC 23
1 2 HTCPU_STOP* D8 LDTSTOP* CPU_VID[5..0]
18 HTCPU_STOP* VID<5> CPU_VID[5..0] 37
R0603 1% O D2 ˖ˣ˨˲˩˜˗ˈ 5
44.2-1%-LF HT_REF1 V8 HTREF1 VID<4> D1 ˖ˣ˨˲˩˜˗ˇ 4
HT_REF0 V7 HTREF0 VID<3> C1 ˖ˣ˨˲˩˜˗ˆ 3
C PLACE WITHIN 1 INCH

35 CPU_CORE_FB
CPU_CORE_FB
A
G2 VDD_FB
VID<2>
VID<1>
E3
E2
˖ˣ˨˲˩˜˗˅
˖ˣ˨˲˩˜˗˄
2
1
C
5MIL TRACE 10MIL SPACE CPU_CORE_FB* G1 VDD_FB* VID<0> E1 ˖ˣ˨˲˩˜˗˃ 0
35 CPU_CORE_FB*
B P
ROUTE AS DIFF PAIR C TP_CPU_VDDIOFB AK11 VDDIO_FB PSI* F1 TP_CPU_PSI* Q
10/5/10 10 D TP_CPU_VDDIOFB* AL11 VDDIO_FB* R
F CPU_PRESENT* AL3 CPU_PRSNT* S CPU_PRSNT* PULL VOTLAGE
C65
CLKIN CPU_GND 38
CPU_CLK 2 1 A8 CLKIN T CAN BE ANY VOLTAGE
18 CPU_CLK
2
C0603
X7R
CLKIN* B8 CLKIN* DBREQ* A5 CPU_DBREQ* U
3900PF/X7R/16V-LF
50V
10% R67
169-1%-LF VDDMEM G NC CPU_DBRDY B6 DBRDY TDO AK10 CPU_TDO NC
1%
R0603
2
CPU_TMS AL9 TMS TEST29 C11 FBCLKOUT

C67
2
CPU_CLK* 2 1 R62 CPU_TCK AH10 TCK TEST29* D11
18 CPU_CLK* C0603
560-1%-LF CPU_TRST* TRST*
1
X7R
3900PF/X7R/16V-LF AJ10 R68
50V
10%
1%
R0603
CPU_TDI AL10 TDI 80.6-1%-LF
1%
R0603
LAYOUT: PLACE 169 OHM WITHIN 0.5INCH OF CPU CPU_TEST25 A10 TEST25 8/5/8/20
CPU_TEST25* TEST25* FBCLKOUT*
21
B10
ROUTE AS DIF 5/5/5/20 CPU_TEST19 TEST19
1
F10
R63 CPU_TEST18 E9 TEST18 LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE
2
560-1%-LF
AJ7 TEST13 LAYOUT: PLACE WITHIN 0.5 INCH OF CPU
1%
R0603 R59 R55 F6 TEST9
220-LF 220-LF
5% 5%
R0603 R0603 TP_CPU_TEST17 D6 TEST17 TEST24 AK8 TP_CPU_TEST24
TEST16 TEST23
1
TP_CPU_TEST16 E7 AH8 TP_CPU_TEST23

TP_CPU_TEST15 F8 TEST15 TEST22 AJ9 TP_CPU_TEST22
TEST14 TEST21 RN21-1 330-8P4R-LF
1
TP_CPU_TEST14 C5 AL8 CPU_TEST21 1 8

TP_CPU_TEST12 AH9 TEST12 TEST20 AJ8 TP_CPU_TEST20 NC
B E5 TEST7 TEST28 J10 B

AJ5 TEST6 TEST28* H9 VDDMEM
CPU_THERMDC AG9 TEST5/THERMDC TEST27 AK9
32 CPU_THERMDC TEST4/THERMDA TEST26
CPU_THERMDA AG8 AK5 CPU_TEST26 RN21-2 2 7 330-8P4R-LF
32 CPU_THERMDA TEST3 TEST10
VDDMEM AH7 G7 RN21-3 3 6 330-8P4R-LF
AJ6 TEST2 TEST8 D4 RN21-4 4 5 330-8P4R-LF
VDDMEM
RSVD RSVD
RN22-1 1 8 330-8P4R-LF HDT CONNECTOR AD25
AE24 RSVD RSVD
G25
G3
2
RN22-2 2 7 330-8P4R-LF AE25 RSVD RSVD G4

RN22-3 3 6 330-8P4R-LF R129 AE27 RSVD RSVD G5
RN22-4 4 5 330-8P4R-LF 220-LF AE28 RSVD RSVD H25
5%
R0603 AF31 RSVD RSVD L25
AG31 RSVD RSVD L26
AJ18 RSVD RSVD L30
CPU_DBREQ* RSVD RSVD
1
AJ20 L31
CPU_DBRDY AK3 RSVD RSVD U24
CPU_TCK AK4 RSVD RSVD V24
CPU_TMS AL4 RSVD RSVD V29
CPU_TDI B19 RSVD RSVD V31
CPU_TRST* C18 RSVD RSVD W25
CPU_TDO 3VDUAL C20 RSVD RSVD W26
E20 RSVD RSVD W30
F2 RSVD RSVD W31
1 F3 RSVD RSVD Y30
1 G24 RSVD RSVD Y31
R50 R49 I235

A 4.7K-0402-LF A
4.7K-0402-LF
2 VREG_PROCHOT
2 CPU_PROCHOT*
D
CPU_PROCHOT* 18
DISABLEΚHigh Q17 C
Q10 MMBT3904
R56
32 PROCHOT_EN* G 2N7002/100mA-LF 1 2VREG_PROCHOT_R B
R0603 5% Title
from SIO / GPIO 220-LF
S
TR-SOT23
E
MCP68/65 HT/CLKS
A3 AN52 V0.1
Date: Thursday, March 08, 2007 Sheet 8 of 42
5 4 3 2 1
5 4 3 2 1
U7C
SK-C940P-M2
SOCKET_940_M2
MEM_A_DATA[63..0] SEC 3 OF 6
13,15 MEM_A_DATA[63..0]
D 63 AE14
ˠ˘ˠ˲˔˲˗˔˧˔ˉˆ MA_DATA<63> MA_CHECK<7> K25 7 ˠ˘ˠ˲˔˲˘˖˖ˊ
MEM_A_ECC[7..0]
MEM_A_ECC[7..0] 13,15 D
62 AG14
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˅ MA_DATA<62> MA_CHECK<6> J26 6 ˠ˘ˠ˲˔˲˘˖˖ˉ
61 AG16
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˄ MA_DATA<61> MA_CHECK<5> G28 5 ˠ˘ˠ˲˔˲˘˖˖ˈ
60 AD17
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˃ MA_DATA<60> MA_CHECK<4> G27 4 ˠ˘ˠ˲˔˲˘˖˖ˇ
59 AD13
ˠ˘ˠ˲˔˲˗˔˧˔ˈˌ MA_DATA<59> MA_CHECK<3> L24 3 ˠ˘ˠ˲˔˲˘˖˖ˆ
58 AE13
ˠ˘ˠ˲˔˲˗˔˧˔ˈˋ MA_DATA<58> MA_CHECK<2> K27 2 ˠ˘ˠ˲˔˲˘˖˖˅
57 AG15
ˠ˘ˠ˲˔˲˗˔˧˔ˈˊ MA_DATA<57> MA_CHECK<1> H29 1 ˠ˘ˠ˲˔˲˘˖˖˄
56 AE16
ˠ˘ˠ˲˔˲˗˔˧˔ˈˉ MA_DATA<56> MA_CHECK<0> H27 0 ˠ˘ˠ˲˔˲˘˖˖˃
55 AG17
ˠ˘ˠ˲˔˲˗˔˧˔ˈˈ MA_DATA<55>
54 AE18
ˠ˘ˠ˲˔˲˗˔˧˔ˈˇ MA_DATA<54> MEM_A_DM[8..0]
MEM_A_DM[8..0] 13,15
53 AD21
ˠ˘ˠ˲˔˲˗˔˧˔ˈˆ MA_DATA<53> MA_DM<8> J25 8 ˠ˘ˠ˲˔˲˗ˠˋ
52 AG22
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˅ MA_DATA<52> MA_DM<7> AF15 7 ˠ˘ˠ˲˔˲˗ˠˊ
51 AE17
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˄ MA_DATA<51> MA_DM<6> AF19 6 ˠ˘ˠ˲˔˲˗ˠˉ
50 AF17
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˃ MA_DATA<50> MA_DM<5> AJ25 5 ˠ˘ˠ˲˔˲˗ˠˈ
49 AF21
ˠ˘ˠ˲˔˲˗˔˧˔ˇˌ MA_DATA<49> MA_DM<4> AH29 4 ˠ˘ˠ˲˔˲˗ˠˇ
48 AE21
ˠ˘ˠ˲˔˲˗˔˧˔ˇˋ MA_DATA<48> MA_DM<3> B29 3 ˠ˘ˠ˲˔˲˗ˠˆ
47 AF23
ˠ˘ˠ˲˔˲˗˔˧˔ˇˊ MA_DATA<47> MA_DM<2> E24 2 ˠ˘ˠ˲˔˲˗ˠ˅
46 AE23
ˠ˘ˠ˲˔˲˗˔˧˔ˇˉ MA_DATA<46> MA_DM<1> E18 1 ˠ˘ˠ˲˔˲˗ˠ˄
45 AJ26
ˠ˘ˠ˲˔˲˗˔˧˔ˇˈ MA_DATA<45> MA_DM<0> H15 0 ˠ˘ˠ˲˔˲˗ˠ˃
44 AG26
ˠ˘ˠ˲˔˲˗˔˧˔ˇˇ MA_DATA<44>
43 AE22
ˠ˘ˠ˲˔˲˗˔˧˔ˇˆ MA_DATA<43> MEM_A_DQS[8..0]
MEM_A_DQS[8..0] 13,15
42 AG23
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˅ MA_DATA<42> MA_DQS<8> J28 8 ˠ˘ˠ˲˔˲˗ˤ˦ˋ
41 AH25
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˄ MA_DATA<41> MA_DQS<7> AD15 7 ˠ˘ˠ˲˔˲˗ˤ˦ˊ
40 AF25
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˃ MA_DATA<40> MA_DQS<6> AG18 6 ˠ˘ˠ˲˔˲˗ˤ˦ˉ
39 AJ28
ˠ˘ˠ˲˔˲˗˔˧˔ˆˌ MA_DATA<39> MA_DQS<5> AG24 5 ˠ˘ˠ˲˔˲˗ˤ˦ˈ
38 AJ29
ˠ˘ˠ˲˔˲˗˔˧˔ˆˋ MA_DATA<38> MA_DQS<4> AG27 4 ˠ˘ˠ˲˔˲˗ˤ˦ˇ
37 AF29
ˠ˘ˠ˲˔˲˗˔˧˔ˆˊ MA_DATA<37> MA_DQS<3> D29 3 ˠ˘ˠ˲˔˲˗ˤ˦ˆ
36 AE26
ˠ˘ˠ˲˔˲˗˔˧˔ˆˉ MA_DATA<36> MA_DQS<2> C25 2 ˠ˘ˠ˲˔˲˗ˤ˦˅
C 35
34
AJ27
ˠ˘ˠ˲˔˲˗˔˧˔ˆˈ
AH27
ˠ˘ˠ˲˔˲˗˔˧˔ˆˇ
MA_DATA<35>
MA_DATA<34>
MA_DQS<1>
MA_DQS<0>
E19
F15
1 ˠ˘ˠ˲˔˲˗ˤ˦˄
0 ˠ˘ˠ˲˔˲˗ˤ˦˃ C
33 AG29
ˠ˘ˠ˲˔˲˗˔˧˔ˆˆ MA_DATA<33>
32 AF27
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˅ MA_DATA<32> MEM_A_DQS*[8..0]
MEM_A_DQS*[8..0] 13,15
31 E29
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˄ MA_DATA<31> MA_DQS<8>* J27 8 ˠ˘ˠ˲˔˲˗ˤ˦ʽˋ
30 E28
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˃ MA_DATA<30> MA_DQS<7>* AE15 7 ˠ˘ˠ˲˔˲˗ˤ˦ʽˊ
29 D27
ˠ˘ˠ˲˔˲˗˔˧˔˅ˌ MA_DATA<29> MA_DQS<6>* AG19 6 ˠ˘ˠ˲˔˲˗ˤ˦ʽˉ
28 C27
ˠ˘ˠ˲˔˲˗˔˧˔˅ˋ MA_DATA<28> MA_DQS<5>* AG25 5 ˠ˘ˠ˲˔˲˗ˤ˦ʽˈ
27 G26
ˠ˘ˠ˲˔˲˗˔˧˔˅ˊ MA_DATA<27> MA_DQS<4>* AG28 4 ˠ˘ˠ˲˔˲˗ˤ˦ʽˇ
26 F27
ˠ˘ˠ˲˔˲˗˔˧˔˅ˉ MA_DATA<26> MA_DQS<3>* C29 3 ˠ˘ˠ˲˔˲˗ˤ˦ʽˆ
25 C28
ˠ˘ˠ˲˔˲˗˔˧˔˅ˈ MA_DATA<25> MA_DQS<2>* D25 2 ˠ˘ˠ˲˔˲˗ˤ˦ʽ˅
24 E27
ˠ˘ˠ˲˔˲˗˔˧˔˅ˇ MA_DATA<24> MA_DQS<1>* F19 1 ˠ˘ˠ˲˔˲˗ˤ˦ʽ˄
23 F25
ˠ˘ˠ˲˔˲˗˔˧˔˅ˆ MA_DATA<23> MA_DQS<0>* G15 0 ˠ˘ˠ˲˔˲˗ˤ˦ʽ˃
22 E25
ˠ˘ˠ˲˔˲˗˔˧˔˅˅ MA_DATA<22>
21 E23
ˠ˘ˠ˲˔˲˗˔˧˔˅˄ MA_DATA<21> MEM_A0_CLK[2..0]
MEM_A0_CLK[2..0] 13,17
20 D23
ˠ˘ˠ˲˔˲˗˔˧˔˅˃ MA_DATA<20> MA0_CLK<0> U27 0 ˠ˘ˠ˲˔˃˲˖˟˞˃ MEM_A0_CLK*[2..0]
MEM_A0_CLK*[2..0] 13,17
19 E26
ˠ˘ˠ˲˔˲˗˔˧˔˄ˌ MA_DATA<19> MA0_CLK<0>* U26 0 ˠ˘ˠ˲˔˃˲˖˟˞ʽ˃
18 C26
ˠ˘ˠ˲˔˲˗˔˧˔˄ˋ MA_DATA<18>
17 G23
ˠ˘ˠ˲˔˲˗˔˧˔˄ˊ MA_DATA<17> MA0_CLK<1> G19 1 ˠ˘ˠ˲˔˃˲˖˟˞˄
16 F23
ˠ˘ˠ˲˔˲˗˔˧˔˄ˉ MA_DATA<16> MA0_CLK<1>* H19 1 ˠ˘ˠ˲˔˃˲˖˟˞ʽ˄
15 E22
ˠ˘ˠ˲˔˲˗˔˧˔˄ˈ MA_DATA<15>
14 E21
ˠ˘ˠ˲˔˲˗˔˧˔˄ˇ MA_DATA<14> MA0_CLK<2> AG21 2 ˠ˘ˠ˲˔˃˲˖˟˞˅
13 F17
ˠ˘ˠ˲˔˲˗˔˧˔˄ˆ MA_DATA<13> MA0_CLK<2>* AG20 2 ˠ˘ˠ˲˔˃˲˖˟˞ʽ˅
12 G17
ˠ˘ˠ˲˔˲˗˔˧˔˄˅ MA_DATA<12> MEM_A1_CLK[2..0]
MEM_A1_CLK[2..0] 15,17
11 G22
ˠ˘ˠ˲˔˲˗˔˧˔˄˄ MA_DATA<11> MA1_CLK<0> V27 0 ˠ˘ˠ˲˔˄˲˖˟˞˃ MEM_A1_CLK*[2..0]
MEM_A1_CLK*[2..0] 15,17
10 F21
ˠ˘ˠ˲˔˲˗˔˧˔˄˃ MA_DATA<10> MA1_CLK<0>* W27 0 ˠ˘ˠ˲˔˄˲˖˟˞ʽ˃
9 G18
ˠ˘ˠ˲˔˲˗˔˧˔ˌ MA_DATA<9>
8 E17
ˠ˘ˠ˲˔˲˗˔˧˔ˋ MA_DATA<8> MA1_CLK<1> G20 1 ˠ˘ˠ˲˔˄˲˖˟˞˄
7 G16
ˠ˘ˠ˲˔˲˗˔˧˔ˊ MA_DATA<7> MA1_CLK<1>* G21 1 ˠ˘ˠ˲˔˄˲˖˟˞ʽ˄
6 E15 MA_DATA<6>
B 5
ˠ˘ˠ˲˔˲˗˔˧˔ˉ
G13
ˠ˘ˠ˲˔˲˗˔˧˔ˈ MA_DATA<5> MA1_CLK<2> AE20 2 ˠ˘ˠ˲˔˄˲˖˟˞˅ B
4 H13
ˠ˘ˠ˲˔˲˗˔˧˔ˇ MA_DATA<4> MA1_CLK<2>* AE19 2 ˠ˘ˠ˲˔˄˲˖˟˞ʽ˅
3 H17
ˠ˘ˠ˲˔˲˗˔˧˔ˆ MA_DATA<3>
2 E16
ˠ˘ˠ˲˔˲˗˔˧˔˅ MA_DATA<2> MEM_A_BA[2..0]
MEM_A_BA[2..0] 13,15,17
1 E14
ˠ˘ˠ˲˔˲˗˔˧˔˄ MA_DATA<1> MA_BANK<2> N25 2 ˠ˘ˠ˲˔˲˕˔˅
0 G14
ˠ˘ˠ˲˔˲˗˔˧˔˃ MA_DATA<0> MA_BANK<1> Y27 1 ˠ˘ˠ˲˔˲˕˔˄
MEM_A_ADD[15..0] MA_BANK<0> AA27 0 ˠ˘ˠ˲˔˲˕˔˃
13,15,17 MEM_A_ADD[15..0]
15ˠ˘ˠ˲˔˲˔˗˗˄ˈ
M27 MA_ADD<15> MA_RAS* AA26 MEM_A_RAS*
MEM_A_CAS* MEM_A_RAS* 13,15,17
14ˠ˘ˠ˲˔˲˔˗˗˄ˇ
N24 MA_ADD<14> MA_CAS* AB25
MEM_A_WE* MEM_A_CAS* 13,15,17
13ˠ˘ˠ˲˔˲˔˗˗˄ˆ
AC26 MA_ADD<13> MA_WE* AB27 MEM_A_WE* 13,15,17
12ˠ˘ˠ˲˔˲˔˗˗˄˅
N26 MA_ADD<12> MEM_A0_CS*[1..0]
MEM_A0_CS*[1..0] 13,17
11ˠ˘ˠ˲˔˲˔˗˗˄˄
P25 MA_ADD<11> MA0_CS<1>* AC25 1 ˠ˘ˠ˲˔˃˲˖˦ʽ˄
10ˠ˘ˠ˲˔˲˔˗˗˄˃
Y25 MA_ADD<10> MA0_CS<0>* AA24 0 ˠ˘ˠ˲˔˃˲˖˦ʽ˃
9ˠ˘ˠ˲˔˲˔˗˗ˌN27 MA_ADD<9> MEM_A1_CS*[1..0]
MEM_A1_CS*[1..0] 15,17
8ˠ˘ˠ˲˔˲˔˗˗ˋR24 MA_ADD<8> MA1_CS<1>* AD27 1 ˠ˘ˠ˲˔˄˲˖˦ʽ˄
7ˠ˘ˠ˲˔˲˔˗˗ˊP27 MA_ADD<7> MA1_CS<0>* AA25 0 ˠ˘ˠ˲˔˄˲˖˦ʽ˃
6ˠ˘ˠ˲˔˲˔˗˗ˉR25 MA_ADD<6>
5ˠ˘ˠ˲˔˲˔˗˗ˈR26 MA_ADD<5> MA_CKE<1> L27 MEM_A1_CKE
MEM_A0_CKE MEM_A1_CKE 15,17
4ˠ˘ˠ˲˔˲˔˗˗ˇR27 MA_ADD<4> MA_CKE<0> M25 MEM_A0_CKE 13,17
3ˠ˘ˠ˲˔˲˔˗˗ˆT25 MA_ADD<3>
2ˠ˘ˠ˲˔˲˔˗˗˅U25 MA_ADD<2> MA0_ODT<0> AC28 MEM_A0_ODT
MEM_A1_ODT MEM_A0_ODT 13,17
1ˠ˘ˠ˲˔˲˔˗˗˄T27 MA_ADD<1> MA1_ODT<0> AC27 MEM_A1_ODT 15,17
0ˠ˘ˠ˲˔˲˔˗˗˃
W24 MA_ADD<0>
I160
A A
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
U7D
SK-C940P-M2
SOCKET_940_M2
MEM_B_ECC[7..0]
MEM_B_DATA[63..0] SEC 4 OF 6
14,16 MEM_B_DATA[63..0] MEM_B_ECC[7..0] 14,16
63 ˠ˘ˠ˲˕˲˗˔˧˔ˉˆ
AH13 MB_DATA<63> MB_CHECK<7> K29 7ˠ˘ˠ˲˕˲˘˖˖ˊ
62 ˠ˘ˠ˲˕˲˗˔˧˔ˉ˅
AL13 MB_DATA<62> MB_CHECK<6> K31 6ˠ˘ˠ˲˕˲˘˖˖ˉ
D 61 ˠ˘ˠ˲˕˲˗˔˧˔ˉ˄
AL15
60 ˠ˘ˠ˲˕˲˗˔˧˔ˉ˃
AJ15
MB_DATA<61>
MB_DATA<60>
MB_CHECK<5>
MB_CHECK<4>
G30
G29
5ˠ˘ˠ˲˕˲˘˖˖ˈ
4ˠ˘ˠ˲˕˲˘˖˖ˇ
D
59 ˠ˘ˠ˲˕˲˗˔˧˔ˈˌ
AF13 MB_DATA<59> MB_CHECK<3> L29 3ˠ˘ˠ˲˕˲˘˖˖ˆ
58 ˠ˘ˠ˲˕˲˗˔˧˔ˈˋ
AG13 MB_DATA<58> MB_CHECK<2> L28 2ˠ˘ˠ˲˕˲˘˖˖˅
57 ˠ˘ˠ˲˕˲˗˔˧˔ˈˊ
AL14 MB_DATA<57> MB_CHECK<1> H31 1ˠ˘ˠ˲˕˲˘˖˖˄
56 ˠ˘ˠ˲˕˲˗˔˧˔ˈˉ
AK15 MB_DATA<56> MB_CHECK<0> G31 0ˠ˘ˠ˲˕˲˘˖˖˃
55 ˠ˘ˠ˲˕˲˗˔˧˔ˈˈ
AL16 MB_DATA<55>
54 ˠ˘ˠ˲˕˲˗˔˧˔ˈˇ
AL17 MB_DATA<54> MEM_B_DM[8..0]
MEM_B_DM[8..0] 14,16
53 ˠ˘ˠ˲˕˲˗˔˧˔ˈˆ
AK21 MB_DATA<53> MB_DM<8> J29 8ˠ˘ˠ˲˕˲˗ˠˋ
52 ˠ˘ˠ˲˕˲˗˔˧˔ˈ˅
AL21 MB_DATA<52> MB_DM<7> AJ14 7ˠ˘ˠ˲˕˲˗ˠˊ
51 ˠ˘ˠ˲˕˲˗˔˧˔ˈ˄
AH15 MB_DATA<51> MB_DM<6> AH17 6ˠ˘ˠ˲˕˲˗ˠˉ
50 ˠ˘ˠ˲˕˲˗˔˧˔ˈ˃
AJ16 MB_DATA<50> MB_DM<5> AJ23 5ˠ˘ˠ˲˕˲˗ˠˈ
49 ˠ˘ˠ˲˕˲˗˔˧˔ˇˌ
AH19 MB_DATA<49> MB_DM<4> AK29 4ˠ˘ˠ˲˕˲˗ˠˇ
48 ˠ˘ˠ˲˕˲˗˔˧˔ˇˋ
AL20 MB_DATA<48> MB_DM<3> C30 3ˠ˘ˠ˲˕˲˗ˠˆ
47 ˠ˘ˠ˲˕˲˗˔˧˔ˇˊ
AJ22 MB_DATA<47> MB_DM<2> A23 2ˠ˘ˠ˲˕˲˗ˠ˅
46 ˠ˘ˠ˲˕˲˗˔˧˔ˇˉ
AL22 MB_DATA<46> MB_DM<1> B17 1ˠ˘ˠ˲˕˲˗ˠ˄
45 ˠ˘ˠ˲˕˲˗˔˧˔ˇˈ
AL24 MB_DATA<45> MB_DM<0> B13 0ˠ˘ˠ˲˕˲˗ˠ˃
44 ˠ˘ˠ˲˕˲˗˔˧˔ˇˇ
AK25 MB_DATA<44>
43 ˠ˘ˠ˲˕˲˗˔˧˔ˇˆ
AJ21 MB_DATA<43> MEM_B_DQS[8..0]
MEM_B_DQS[8..0] 14,16
42 ˠ˘ˠ˲˕˲˗˔˧˔ˇ˅
AH21 MB_DATA<42> MB_DQS<8> J31 8ˠ˘ˠ˲˕˲˗ˤ˦ˋ
41 ˠ˘ˠ˲˕˲˗˔˧˔ˇ˄
AH23 MB_DATA<41> MB_DQS<7> AK13 7ˠ˘ˠ˲˕˲˗ˤ˦ˊ
40 ˠ˘ˠ˲˕˲˗˔˧˔ˇ˃
AJ24 MB_DATA<40> MB_DQS<6> AK17 6ˠ˘ˠ˲˕˲˗ˤ˦ˉ
39 ˠ˘ˠ˲˕˲˗˔˧˔ˆˌ
AL27 MB_DATA<39> MB_DQS<5> AK23 5ˠ˘ˠ˲˕˲˗ˤ˦ˈ
38 ˠ˘ˠ˲˕˲˗˔˧˔ˆˋ
AK27 MB_DATA<38> MB_DQS<4> AL28 4ˠ˘ˠ˲˕˲˗ˤ˦ˇ
37 ˠ˘ˠ˲˕˲˗˔˧˔ˆˊ
AH31 MB_DATA<37> MB_DQS<3> D31 3ˠ˘ˠ˲˕˲˗ˤ˦ˆ
36 ˠ˘ˠ˲˕˲˗˔˧˔ˆˉ
AG30 MB_DATA<36> MB_DQS<2> C24 2ˠ˘ˠ˲˕˲˗ˤ˦˅
35 ˠ˘ˠ˲˕˲˗˔˧˔ˆˈ
AL25 MB_DATA<35> MB_DQS<1> D17 1ˠ˘ˠ˲˕˲˗ˤ˦˄
34 ˠ˘ˠ˲˕˲˗˔˧˔ˆˇ
AL26 MB_DATA<34> MB_DQS<0> C14 0ˠ˘ˠ˲˕˲˗ˤ˦˃
33 ˠ˘ˠ˲˕˲˗˔˧˔ˆˆ
AJ30 MB_DATA<33>
MEM_B_DQS*[8..0]
C 32 ˠ˘ˠ˲˕˲˗˔˧˔ˆ˅
AJ31
31 ˠ˘ˠ˲˕˲˗˔˧˔ˆ˄
E31
MB_DATA<32>
MB_DATA<31> MB_DQS<8>* J30 8ˠ˘ˠ˲˕˲˗ˤ˦ʽˋ
MEM_B_DQS*[8..0] 14,16 ROUTE AS A 15MIL TRACE C
30 ˠ˘ˠ˲˕˲˗˔˧˔ˆ˃
E30 MB_DATA<30> MB_DQS<7>* AJ13 7ˠ˘ˠ˲˕˲˗ˤ˦ʽˊ
29 ˠ˘ˠ˲˕˲˗˔˧˔˅ˌ
B27 MB_DATA<29> MB_DQS<6>* AJ17 6ˠ˘ˠ˲˕˲˗ˤ˦ʽˉ
28 ˠ˘ˠ˲˕˲˗˔˧˔˅ˋ
A27 MB_DATA<28> MB_DQS<5>* AL23 5ˠ˘ˠ˲˕˲˗ˤ˦ʽˈ
27 ˠ˘ˠ˲˕˲˗˔˧˔˅ˊ
F29 MB_DATA<27> MB_DQS<4>* AL29 4ˠ˘ˠ˲˕˲˗ˤ˦ʽˇ VDDMEM
26 ˠ˘ˠ˲˕˲˗˔˧˔˅ˉ
F31 MB_DATA<26> MB_DQS<3>* C31 3ˠ˘ˠ˲˕˲˗ˤ˦ʽˆ
2
25 ˠ˘ˠ˲˕˲˗˔˧˔˅ˈ
A29 MB_DATA<25> MB_DQS<2>* C23 2ˠ˘ˠ˲˕˲˗ˤ˦ʽ˅
24 ˠ˘ˠ˲˕˲˗˔˧˔˅ˇ
A28 MB_DATA<24> MB_DQS<1>* C17 1ˠ˘ˠ˲˕˲˗ˤ˦ʽ˄ BR28
23 ˠ˘ˠ˲˕˲˗˔˧˔˅ˆ
A25 MB_DATA<23> MB_DQS<0>* C13 0ˠ˘ˠ˲˕˲˗ˤ˦ʽ˃ 100-1%-LF
1%
22 ˠ˘ˠ˲˕˲˗˔˧˔˅˅
A24 MB_DATA<22> R0603
21 ˠ˘ˠ˲˕˲˗˔˧˔˅˄
C22 MB_DATA<21> L
20 ˠ˘ˠ˲˕˲˗˔˧˔˅˃
D21 MB_DATA<20> M_VREF F12 MEM_CPU_VREF
12
19 ˠ˘ˠ˲˕˲˗˔˧˔˄ˌ
A26 MB_DATA<19>
1
18 ˠ˘ˠ˲˕˲˗˔˧˔˄ˋ MB_DATA<18> MEM_B0_CLK[2..0] BC49 BC50
B25 MEM_B0_CLK[2..0] 14,17 0.1UF/X7R/16V-LF
BR27
1000PF/X7R/16V-LF 100-1%-LF
17 ˠ˘ˠ˲˕˲˗˔˧˔˄ˊ
B23 MB_DATA<17> MB0_CLK<0> U31 0ˠ˘ˠ˲˕˃˲˖˟˞˃ MEM_B0_CLK*[2..0]
MEM_B0_CLK*[2..0] 14,17 1%
16 ˠ˘ˠ˲˕˲˗˔˧˔˄ˉ
A22 MB_DATA<16> MB0_CLK<0>* U30 0 ˠ˘ˠ˲˕˃˲˖˟˞ʽ˃ C0603
X5R
C0603
X7R
R0603
15 ˠ˘ˠ˲˕˲˗˔˧˔˄ˈ
B21 MB_DATA<15> 16V
10%
25V
10%
14 ˠ˘ˠ˲˕˲˗˔˧˔˄ˇ MB_DATA<14> MB0_CLK<1>
2
A20 A18 1ˠ˘ˠ˲˕˃˲˖˟˞˄
13 ˠ˘ˠ˲˕˲˗˔˧˔˄ˆ MB_DATA<13> MB0_CLK<1>*
1
C16 A19 1 ˠ˘ˠ˲˕˃˲˖˟˞ʽ˄
12 ˠ˘ˠ˲˕˲˗˔˧˔˄˅
D15 MB_DATA<12>
11 ˠ˘ˠ˲˕˲˗˔˧˔˄˄
C21 MB_DATA<11> MB0_CLK<2> AJ19 2ˠ˘ˠ˲˕˃˲˖˟˞˅
10 ˠ˘ˠ˲˕˲˗˔˧˔˄˃
A21 MB_DATA<10> MB0_CLK<2>* AK19 2 ˠ˘ˠ˲˕˃˲˖˟˞ʽ˅ V0.1 15-1%ohm ->100-1%ohm
9ˠ˘ˠ˲˕˲˗˔˧˔ˌA17 MB_DATA<9> MEM_B1_CLK[2..0]
MEM_B1_CLK[2..0] 16,17
8ˠ˘ˠ˲˕˲˗˔˧˔ˋA16 MB_DATA<8> MB1_CLK<0> W29 0ˠ˘ˠ˲˕˄˲˖˟˞˃ MEM_B1_CLK*[2..0]
MEM_B1_CLK*[2..0] 16,17
7ˠ˘ˠ˲˕˲˗˔˧˔ˊB15 MB_DATA<7> MB1_CLK<0>* W28 0 ˠ˘ˠ˲˕˄˲˖˟˞ʽ˃
6ˠ˘ˠ˲˕˲˗˔˧˔ˉA14 MB_DATA<6>
5ˠ˘ˠ˲˕˲˗˔˧˔ˈE13 MB_DATA<5> MB1_CLK<1> C19 1ˠ˘ˠ˲˕˄˲˖˟˞˄
4ˠ˘ˠ˲˕˲˗˔˧˔ˇF13 MB_DATA<4> MB1_CLK<1>* D19 1 ˠ˘ˠ˲˕˄˲˖˟˞ʽ˄
3ˠ˘ˠ˲˕˲˗˔˧˔ˆ
C15 MB_DATA<3>
B 2ˠ˘ˠ˲˕˲˗˔˧˔˅A15 MB_DATA<2> MB1_CLK<2> AL19 2ˠ˘ˠ˲˕˄˲˖˟˞˅ B
1ˠ˘ˠ˲˕˲˗˔˧˔˄A13 MB_DATA<1> MB1_CLK<2>* AL18 2 ˠ˘ˠ˲˕˄˲˖˟˞ʽ˅
0ˠ˘ˠ˲˕˲˗˔˧˔˃
D13 MB_DATA<0>
MEM_B_BA[2..0]
MEM_B_ADD[15..0] MEM_B_BA[2..0] 14,16,17
MB_BANK<2> N31 2ˠ˘ˠ˲˕˲˕˔˅
14,16,17 MEM_B_ADD[15..0] 15ˠ˘ˠ˲˕˲˔˗˗˄ˈ
N28 MB_ADD<15> MB_BANK<1> AA31 1ˠ˘ˠ˲˕˲˕˔˄
14ˠ˘ˠ˲˕˲˔˗˗˄ˇ
N29 MB_ADD<14> MB_BANK<0> AA28 0ˠ˘ˠ˲˕˲˕˔˃
13ˠ˘ˠ˲˕˲˔˗˗˄ˆ
AE31 MB_ADD<13>
12ˠ˘ˠ˲˕˲˔˗˗˄˅
N30 MB_ADD<12> MB_RAS* AB29 MEM_B_RAS*
MEM_B_CAS* MEM_B_RAS* 14,16,17
11ˠ˘ˠ˲˕˲˔˗˗˄˄P29 MB_ADD<11> MB_CAS* AC29
MEM_B_WE* MEM_B_CAS* 14,16,17
10ˠ˘ˠ˲˕˲˔˗˗˄˃
AA29 MB_ADD<10> MB_WE* AC30
LAYOUT: 5MIL TRACE 10 MIL SPACE MEM_B_WE* 14,16,17
9ˠ˘ˠ˲˕˲˔˗˗ˌP31 MB_ADD<9> MEM_B0_CS*[1..0]
LAYOUT: PLACE WITHIN 1 INCH OF CPU MEM_B0_CS*[1..0] 14,17
8ˠ˘ˠ˲˕˲˔˗˗ˋR29 MB_ADD<8> MB0_CS<1>* AE30 1ˠ˘ˠ˲˕˃˲˖˦ʽ˄
7ˠ˘ˠ˲˕˲˔˗˗ˊR28 MB_ADD<7> MB0_CS<0>* AC31 0ˠ˘ˠ˲˕˃˲˖˦ʽ˃
6ˠ˘ˠ˲˕˲˔˗˗ˉR31 MB_ADD<6> MEM_B1_CS*[1..0]
MEM_B1_CS*[1..0] 16,17
5ˠ˘ˠ˲˕˲˔˗˗ˈR30 MB_ADD<5> MB1_CS<1>* AE29 1ˠ˘ˠ˲˕˄˲˖˦ʽ˄
VDDMEM 4ˠ˘ˠ˲˕˲˔˗˗ˇT31 MB_ADD<4> MB1_CS<0>* AB31 0ˠ˘ˠ˲˕˄˲˖˦ʽ˃
3ˠ˘ˠ˲˕˲˔˗˗ˆT29 MB_ADD<3>
2
2ˠ˘ˠ˲˕˲˔˗˗˅U29 MB_ADD<2> MB_CKE<1> M31 MEM_B1_CKE

MEM_B0_CKE MEM_B1_CKE 16,17
R118 1ˠ˘ˠ˲˕˲˔˗˗˄U28 MB_ADD<1> MB_CKE<0> M29 MEM_B0_CKE 14,17
40.2-1%-LF 0ˠ˘ˠ˲˕˲˔˗˗˃
AA30 MB_ADD<0>
1%
R0603 MB0_ODT<0> AD29 MEM_B0_ODT
MEM_B1_ODT MEM_B0_ODT 14,17
MB1_ODT<0> AD31
CPU_MEMZN MEM_B1_ODT 16,17
AH11 M_ZN
CPU_MEMZP M_ZP VTT_SENSE H
21
AJ11 E12 MEM_VTT_SENSE
I234
R116
40.2-1%-LF
1%
A A
R0603
V0.1 39.2-1%ohm ->40.2-1%ohm

1
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
A
B
C
D
VCCP
U7F
5
5
SK-C940P-M2
SOCKET_940_M2 U7E
SK-C940P-M2
SEC 6 OF 6
Z
A3 VSS VSS H22 SOCKET_940_M2
A7 VSS VSS H24 SEC 5 OF 6
A9 VSS VSS H26 A4 VDD VDD N18
A11 VSS VSS H28 A6 VDD VDD P7
AA4 VSS VSS H30 AA8 VDD VDD P9
AA5 VSS VSS J4 AA10 VDD VDD P11
AA15 VSS VSS J13 AB7 VDD VDD R4
AA21 VSS VSS J19 AC4 VDD VDD R10
AA23 VSS VSS J21 AC5 VDD VDD R12
AB2 VSS VSS J23 AC8 VDD VDD R14
AB3 VSS VSS K2 AC10 VDD VDD R16
AB8 VSS VSS K3 AD2 VDD VDD R18
AB10 VSS VSS K8 AD3 VDD VDD R20
AB12 VSS VSS K10 AD7 VDD VDD T2
AB14 VSS VSS K12 AD9 VDD VDD T3
AB16 VSS VSS K14 AE10 VDD VDD T7
AB18 VSS VSS K16 AF7 VDD VDD T9
AB20 VSS VSS K18 AF9 VDD VDD T11
AB22 VSS VSS K20 AG4 VDD VDD T13
AC7 VSS VSS K22 AG5 VDD VDD T15
AC9 VSS VSS K24 AG7 VDD VDD T17
AC11 VSS VSS K26 AH2 VDD VDD T19
AC13 VSS VSS K28 AH3 VDD VDD T21
AC15 VSS VSS K30 B3 VDD VDD U8
4
4
AC17 VSS VSS L7 B5 VDD VDD U10

AC19 VSS VSS L9 B7 VDD VDD U12
AC21 VSS VSS L11 C2 VDD VDD U14
AC23 VSS VSS L13 C4 VDD VDD U16
AD8 VSS VSS L15 C6 VDD VDD U18
AD10 VSS VSS L17 C8 VDD VDD U20
AD12 VSS VSS L19 D3 VDD VDD V9
AD20 VSS VSS M8 D9 VDD VDD V15
AD22 VSS VSS M10 E4 VDD VDD V17
AD24 VSS VSS M12 E6 VDD VDD V19
AE4 VSS VSS M14 E8 VDD VDD V21
AE5 VSS VSS M16 E10 VDD VDD W4
AE9 VSS VSS M18 F5 VDD VDD W5
AE11 VSS VSS M20 F7 VDD VDD W8
AF2 VSS VSS M22 F9 VDD VDD W10
AF3 VSS VSS N4 F11 VDD VDD W12
AF8 VSS VSS N5 G6 VDD VDD W14
AF16 VSS VSS N13 H7 VDD VDD Y2
AF22 VSS VSS N19 J8 VDD VDD Y9
AF28 VSS VSS P2 J16 VDD VDD Y15
AG10 VSS VSS P3 J18 VDD VDD Y17
AG11 VSS VSS P8 J20 VDD VDD Y19
AH14 VSS VSS P10 J22 VDD VDD Y21
AH16 VSS VSS P12 J24 VDD VDD AA20
3
3
AH18 VSS VSS P14 K7 VDD VDD AA22

AH20 VSS VSS P16 K9 VDD VDD AB13
AH28 VSS VSS R7 K17 VDD VDD AB21
AH30 VSS VSS R9 K19 VDD VDD AB23
AK2 VSS VSS R11 K21 VDD VDD AC12
AK14 VSS VSS R13 K23 VDD VDD AC14
AK16 VSS VSS R15 L4 VDD VDD AC16
AK24 VSS VSS R23 L12 VDD VDD AD11
AK26 VSS VSS T8 L14 VDD VDD AD23
AK28 VSS VSS T10 L16 VDD VDD AE12
AK30 VSS VSS T12 L18 VDD VDD AF11
AL5 VSS VSS T14 M2 VDD VDD L20
B4 VSS VSS T16 M3 VDD VDD L22
B9 VSS VSS T18 M7 VDD VDD M21
B11 VSS VSS T20 M9 VDD VDD M23
B14 VSS VSS T22 M11 VDD VDD N20
B16 VSS VSS U4 M13 VDD VDD N22
B18 VSS VSS U5 M15 VDD VDD P21
B20 VSS VSS U7 M17 VDD VDD P23
B22 VSS VSS U9 M19 VDD VDD R22
B24 VSS VSS U11 N8 VDD VDD T23
B26 VSS VSS U13 N10 VDD VDD U22
B28 VSS VSS U15 N12 VDD VDD V23
B30 VSS VSS U17 N14 VDD VDD W22
C3 VSS VSS U19 N16 VDD VDD Y23
D14 VSS VSS U21
D16 VSS VSS U23
2
2
D18 VSS VSS V2 AB24 VDDIO VDDIO P28

D20 VSS VSS V3 AB26 VDDIO VDDIO P30
D22 VSS VSS V10 AB28 VDDIO VDDIO T24
D24 VSS VSS V12 AB30 VDDIO VDDIO T26
D26 VSS VSS V14 AC24 VDDIO VDDIO T28
D28 VSS VSS V16 AD26 VDDIO VDDIO T30
D30 VSS VSS V18 AD28 VDDIO VDDIO V25
E11 VSS VSS V20 AD30 VDDIO VDDIO V26
F4 VSS VSS V22 AF30 VDDIO VDDIO V28
F14 VSS VSS W7 M24 VDDIO VDDIO V30
F16 VSS VSS W9 M26 VDDIO VDDIO Y24
F22 VSS VSS W15 P24 VDDIO VDDIO Y29
Title
Size
VSS VSS VDDIO

Date:
F24 W17 P26

A3
F26 VSS VSS W19

F28 VSS VSS W21 A12 VTT VTT AH12
F30 VSS VSS W23 B12 VTT VTT AJ12
G9 VSS VSS Y8 C12 VTT VTT AK12
G11 VSS VSS Y10 D12 VTT VTT AL12
H8 VSS VSS Y12 AG12 VTT
H10 VSS VSS Y14
H12 VSS VSS Y16 I108
H14 VSS VSS Y18
Document Number
H16 VSS VSS Y20

H18 VSS VSS Y22
Friday, March 02, 2007
VTTMEM
1 PADVSS PADVSS 3
2 PADVSS PADVSS 4
AN52
1
1
VDDMEM
MCP68/65 HT/CLKS
Sheet
11
of
42
Rev
V0.1
A
B
C
D
5 4 3 2 1
PLACE NEAR CPU, BETWEEN CPU AND DIMM PLACE NEAR THE CPU SOCKET PLACE NEAR CPU SOCKET ALONG VTT POUR
D VDDMEM V1P2 V1P2_LDT VTTMEM D

CT23
1
BCT3 BCT14 C12 C189 BC39 BC42 C163 BCT2 CT36 C93 C87 CT43 CT16 CT47 CT22 C222 C142 C38 C50 C44 4.7UF/0805Y/10V-LF C171 C143
4.7UF/0805Y/10V-LF
4.7UF/0805Y/10V-LF
0.22UF/16V-LF 0.22UF/16V-LF 0.22UF/16V-LF 180PF-LF 180PF-LF 4.7UF/0805Y/10V-LF
4.7UF/0805Y/10V-LF
0.22UF/16V-LF 0.22UF/16V-LF 4.7UF/0805Y/10V-LF 4.7UF/0805Y/10V-LF
4.7UF/0805Y/10V-LF
0.22UF/16V-LF 0.22UF/16V-LF 0.22UF/16V-LF 0.22UF/16V-LF1000PF/X7R/16V-LF 1000PF/X7R/16V-LF 1000PF/X7R/16V-LF
C0805 C0805 C0603 C0603 C0603 C0603 C0603 C0805 C0805 C0603 C0603 C0805 4.7UF/0805Y/10V-LF
C0805 C0805 C0805 C0603 C0603 C0603 C0603 C0603 C0805 C0603 C0603
? ? X7R X7R X7R C0G C0G ? ? X7R X7R ? ? ? ? X7R X7R X7R X7R X7R ? X7R X7R
6.3V 6.3V 16V 16V 16V 50V 50V 6.3V 6.3V 16V 16V 6.3V 6.3V 6.3V 6.3V 16V 16V 16V 16V 6.3V 6.3V 6.3V 6.3V
2 10% 10% 10% 10% 10% 5% 5% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
PLACE UNDER THE CPU SOCKET
VCCP VDDMEM
1
1
BCT6 BCT11 BCT10 BCT16 BCT15 BCT18 BCT17 BCT5 BCT7 BCT4 BCT9 BCT8 BCT13 BCT12 C71 C230 BC37 BC36 BC51 CT42 CT21 BC45
C 10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
10UF/X5R/6.3V/0805-LF
0.22UF/16V-LF 0.22UF/16V-LF 0.22UF/16V-LF 0.01UF/X7R/16V-LF
10PF/NPO/50V-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF C
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0603 C0603 C0603 C0603 C0603 C0805 C0805 0.22UF/16V-LF
C0603
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X7R X7R X7R X7R ? X5R X5R X7R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 16V 16V 16V <VOLTAGE> 50V 6.3V 6.3V 16V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 5% 20% 20% 10%
2
2
PLACE NEAR DIMM SOCKET ALONG VTT POUR INBETWEEN RPACKS
VTTMEM
1
1
C66 C164 C179 C174 C172 C170 C154 C146 C135 C131 C127 C98 C86 C103 C117 C80 C75
0.1UF/X7R/16V-LF0.1UF/X7R/16V-LF0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF0.1UF/X7R/16V-LF0.1UF/X7R/16V-LF0.1UF/X7R/16V-LF0.1UF/X7R/16V-LF
VDDMEM C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
C0603
X7R
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
X0.1UF/X7R/16V-LF X0.1UF/X7R/16V-LF X0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF X0.1UF/X7R/16V-LF
2
2
B B
VCCP
1
CT28 CT27 CT26 CT6 CT45 CT9 CT34 CT35 CT25 CT17 CT14 CT29 CT18 CT38 CT37 CT39 CT40
10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
6.3V 6.3V 6.3V 6.3V 6.3V10UF/X5R/6.3V/0805-LF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
PLACE NEAR DIMM SOCKET ALONG VTT POUR 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF X10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF X10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF
2
2
VTTMEM
VCCP
1
C51 C35 C223 C201 CT30 C188 C190 C52 C40 C193
1000PF/X7R/16V-LF 0.1UF/X7R/16V-LF 4.7UF/0805Y/10V-LF 180PF-LF 1000PF/X7R/16V-LF 180PF-LF X0.01UF/X7R/16V-LF 0.01UF/X7R/16V-LF
1
1
C0603 C0603 C0603 C0603 C0805 C0603 C0603 C0603 C0603 C0603 C58 BC46 C55 BC40 C48 BC47 C68 BC41 C69 C226 BC48 C57 BC43 C56 BC38 BC44 C49 C47 C70 C42
X7R X5R X5R X5R ? C0G X7R C0G X7R X7R
6.3V X0.1UF/X7R/16V-LF
16V 16V X0.1UF/X7R/16V-LF
16V 6.3V 50V 6.3V 50V <VOLTAGE> <VOLTAGE> 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.1UF/X7R/16V-LF 0.01UF/X7R/16V-LF 0.01UF/X7R/16V-LF 0.01UF/X7R/16V-LF 0.01UF/X7R/16V-LF 0.01UF/X7R/16V-LF
10% 10% 10% 10% 10% 5% 10% 5% 10% 10%
2
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
16V 16V 16V 16V 16V 16V 16V 0.1UF/X7R/16V-LF
16V 16V 16V <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> 0.01UF/X7R/16V-LF
<VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE>
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
X0.1UF/X7R/16V-LF X0.1UF/X7R/16V-LF X0.1UF/X7R/16V-LF X0.1UF/X7R/16V-LF 0.01UF/X7R/16V-LF X0.01UF/X7R/16V-LF X0.01UF/X7R/16V-LF X0.01UF/X7R/16V-LF
2
2
A A
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
VTT_P VTT_N VTT_VREF
0 0 (VDDR / 2)*102%_0.922
D 0 1 (VDDR / 2)*98%_0.882 D
1 0 (VDDR / 2)*100%_0.899 *
1 1 (VDDR / 2)*96%_0.856
DIMM 1 CLOSEST DIMM TO CPU

CHANNEL "A" LOWER 64 BITS
V0.1
VDDMEM +1.8V_SUS
2
SMB_MEM_SCL
14,15,16,23,35,43 SMB_MEM_SCL
SMB_MEM_SDA
14,15,16,23,35,43 SMB_MEM_SDA
C19 R34
MEM_A0_ODT 200-1%-LF
9,17 MEM_A0_ODT 0.1UF/16V-LF
MEM_A_BA[2..0]
9,15,17 MEM_A_BA[2..0]
MEM_VREF
1
MEM_VREF 14,15,16
MEM_A0_CKE ˠ˘ˠ˲˔˲˕˔˃
ˠ˘ˠ˲˔˲˕˔˄
ˠ˘ˠ˲˔˲˕˔˅
9,17 MEM_A0_CKE
0
1
2
C26
MEM_A0_CS*[1..0]
9,17 MEM_A0_CS*[1..0] 0.1UF/16V-LF
2
MEM_A_CAS* ˠ˘ˠ˲˔˃˲˖˦ʽ˃
ˠ˘ˠ˲˔˃˲˖˦ʽ˄ R37 R36
9,15,17 MEM_A_CAS*
1
0
1
C 9,15,17 MEM_A_RAS*
9,15,17 MEM_A_WE*
MEM_A_RAS*
MEM_A_WE*
R33
4.02K-1%-LF
2.26K-1%-LF C24 C23
0.1UF/16V/0402-LF C
C0402
C0402
Q6 X7R X5R
16V 0.1UF/16V/0402-LF
MEM_A0_CLK*[2..0] 210-1%-LF 25V
10% 10%
D
9,17 MEM_A0_CLK*[2..0]
Q7
2
2N7002/100mA-LF
MEM_A0_CLK[2..0]
1
ˠ˘ˠ˲˔˃˲˖˟˞ʽ˃
ˠ˘ˠ˲˔˃˲˖˟˞ʽ˄
ˠ˘ˠ˲˔˃˲˖˟˞ʽ˅
9,17 MEM_A0_CLK[2..0]
0
1
2
46 VTT_P G G VTT_N 46
ˠ˘ˠ˲˔˃˲˖˟˞˃
ˠ˘ˠ˲˔˃˲˖˟˞˄
ˠ˘ˠ˲˔˃˲˖˟˞˅ 2N7002/100mA-LF
0
1
2
S
MEM_A_ECC[7..0]
9,15 MEM_A_ECC[7..0]
MEM_A_DQS*[8..0]
9,15 MEM_A_DQS*[8..0]
MEM_A_DQS[8..0] ˠ˘ˠ˲˔˲˘˖˖˃
ˠ˘ˠ˲˔˲˘˖˖˄
ˠ˘ˠ˲˔˲˘˖˖˅
ˠ˘ˠ˲˔˲˘˖˖ˆ
ˠ˘ˠ˲˔˲˘˖˖ˇ
ˠ˘ˠ˲˔˲˘˖˖ˈ
ˠ˘ˠ˲˔˲˘˖˖ˉ
ˠ˘ˠ˲˔˲˘˖˖ˊ
9,15 MEM_A_DQS[8..0]
0
1
2
3
4
5
6
7
MEM_A_DM[8..0] ˠ˘ˠ˲˔˲˗ˤ˦ʽ˃
ˠ˘ˠ˲˔˲˗ˤ˦ʽ˄
ˠ˘ˠ˲˔˲˗ˤ˦ʽ˅
ˠ˘ˠ˲˔˲˗ˤ˦ʽˆ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˇ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˈ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˉ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˊ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˋ
9,15 MEM_A_DM[8..0]
0
1
2
3
4
5
6
7
8
MEM_A_ADD[15..0] ˠ˘ˠ˲˔˲˗ˤ˦˃
ˠ˘ˠ˲˔˲˗ˤ˦˄
ˠ˘ˠ˲˔˲˗ˤ˦˅
ˠ˘ˠ˲˔˲˗ˤ˦ˆ
ˠ˘ˠ˲˔˲˗ˤ˦ˇ
ˠ˘ˠ˲˔˲˗ˤ˦ˈ
ˠ˘ˠ˲˔˲˗ˤ˦ˉ
ˠ˘ˠ˲˔˲˗ˤ˦ˊ
ˠ˘ˠ˲˔˲˗ˤ˦ˋ VCC3 VDDMEM
9,15,17 MEM_A_ADD[15..0]
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˔˲˗ˠ˃
ˠ˘ˠ˲˔˲˗ˠ˄
ˠ˘ˠ˲˔˲˗ˠ˅
ˠ˘ˠ˲˔˲˗ˠˆ
ˠ˘ˠ˲˔˲˗ˠˇ
ˠ˘ˠ˲˔˲˗ˠˈ
ˠ˘ˠ˲˔˲˗ˠˉ
ˠ˘ˠ˲˔˲˗ˠˊ
ˠ˘ˠ˲˔˲˗ˠˋ
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˔˲˔˗˗˃
ˠ˘ˠ˲˔˲˔˗˗˄
ˠ˘ˠ˲˔˲˔˗˗˅
ˠ˘ˠ˲˔˲˔˗˗ˆ
ˠ˘ˠ˲˔˲˔˗˗ˇ
ˠ˘ˠ˲˔˲˔˗˗ˈ
ˠ˘ˠ˲˔˲˔˗˗ˉ
ˠ˘ˠ˲˔˲˔˗˗ˊ
ˠ˘ˠ˲˔˲˔˗˗ˋ
ˠ˘ˠ˲˔˲˔˗˗ˌ
ˠ˘ˠ˲˔˲˔˗˗˄˃
ˠ˘ˠ˲˔˲˔˗˗˄˄
ˠ˘ˠ˲˔˲˔˗˗˄˅
ˠ˘ˠ˲˔˲˔˗˗˄ˆ
ˠ˘ˠ˲˔˲˔˗˗˄ˇ
ˠ˘ˠ˲˔˲˔˗˗˄ˈ
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
188
183
182
180
179
177
176
196
174
173
125
134
146
155
202
211
223
232
164
105
114
104
113
161
162
167
168
126
135
147
156
203
212
224
233
165
185
137
220
186
138
221
192
193
171
190
195
102
239
240
101
119
120
238
172
178
184
187
189
197
170
175
181
191
194
63
61
60
58
70
57
16
28
37
84
93
46
15
27
36
83
92
45
42
43
48
49
19
73
74
76
52
71
54
77
68
55
18
53
59
64
67
69
51
56
62
72
75
78
7
1
A12
A13
A14
A15
A11
A16/BA2
CK0
CK1
CK2
CKE1
SCL
CKE0
CK0*
CK1*
CK2*
SA0
SA1
A0
A1
A3
A6
A8
A9
BA1
A2
A4
A5
A7
BA0
TEST
SA2
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A10/AP
DQS0
DQS1
DQS6
DQS7
DQS2
DQS3
PAR_IN
DQS4
DQS5
S0*
S1*
SDA
DQS0*
DQS1*
DQS6*
DQS7*
DQS2*
DQS3*
DQS4*
DM0/DQS9
DQS5*
ODT0
VREF
NC/DQS8
ODT1
VDDQ
WE*
RAS*
CAS*
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC/DQS8*
NC/DQS9*
RESET*
VDDSPD
DM7/DQS16
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM8/DQS17
NC/CB4
NC/CB5
NC/CB6
NC/CB7
NC/CB0
NC/CB1
NC/CB2
NC/CB3
NC/DQS10*
NC/DQS11*
NC/DQS12*
NC/DQS13*
NC/DQS15*
NC/DQS16*
NC/DQS17*
NC/DQS14*
ERR_OUT*
DIMM240
B B
1.8V
SK-D240P
DIMM1
Default
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ47
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ42
DQ43
DQ48
DQ49
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
I278
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
10
12
13
21
22
24
25
30
31
33
34
39
40
80
81
86
87
89
90
95
96
98
99
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
3
4
9
2
5
8
ˠ˘ˠ˲˔˲˗˔˧˔˃
ˠ˘ˠ˲˔˲˗˔˧˔˄
ˠ˘ˠ˲˔˲˗˔˧˔˅
ˠ˘ˠ˲˔˲˗˔˧˔ˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˌ
ˠ˘ˠ˲˔˲˗˔˧˔˄˃
ˠ˘ˠ˲˔˲˗˔˧˔˄˄
ˠ˘ˠ˲˔˲˗˔˧˔˄˅
ˠ˘ˠ˲˔˲˗˔˧˔˄ˆ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˇ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˈ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˉ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˊ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˋ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˌ
ˠ˘ˠ˲˔˲˗˔˧˔˅˃
ˠ˘ˠ˲˔˲˗˔˧˔˅˄
ˠ˘ˠ˲˔˲˗˔˧˔˅˅
ˠ˘ˠ˲˔˲˗˔˧˔˅ˆ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˇ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˈ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˉ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˊ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˋ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˆˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˇˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˈˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˉˆ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
MEM_A_DATA[63..0]
9,15 MEM_A_DATA[63..0]
SMB_MEM_SDA
SMB_MEM_SCL
3VDUAL 3VDUAL
K K
A A
KA KA
D9
BAV99-LF D8
A BAV99-LF A Title
MCP68/65 HT/CLKS
Prevent ESD issue A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
D D
DIMM 2 CHANNEL "B" UPPER 64 BITS
SMB_MEM_SCL
13,15,16,23,35,43 SMB_MEM_SCL SMB_MEM_SDA
13,15,16,23,35,43 SMB_MEM_SDA
MEM_B0_ODT
10,17 MEM_B0_ODT
MEM_B_BA[2..0]
10,16,17 MEM_B_BA[2..0]
MEM_B0_CKE ˠ˘ˠ˲˕˲˕˔˃
ˠ˘ˠ˲˕˲˕˔˄
ˠ˘ˠ˲˕˲˕˔˅
10,17 MEM_B0_CKE
0
1
2
MEM_B0_CS*[1..0]
10,17 MEM_B0_CS*[1..0]
MEM_B_CAS* ˠ˘ˠ˲˕˃˲˖˦ʽ˃
ˠ˘ˠ˲˕˃˲˖˦ʽ˄
10,16,17 MEM_B_CAS* MEM_B_RAS*
0
1
10,16,17 MEM_B_RAS* MEM_B_WE*
10,16,17 MEM_B_WE*
C 10,17 MEM_B0_CLK*[2..0]
MEM_B0_CLK*[2..0]
13,15,16 MEM_VREF
MEM_VREF C
1
MEM_B0_CLK[2..0] ˠ˘ˠ˲˕˃˲˖˟˞ʽ˃
ˠ˘ˠ˲˕˃˲˖˟˞ʽ˄
ˠ˘ˠ˲˕˃˲˖˟˞ʽ˅
C20
10,17 MEM_B0_CLK[2..0] 0.1UF/16V/0402-LF
0
1
2
ˠ˘ˠ˲˕˃˲˖˟˞˃
ˠ˘ˠ˲˕˃˲˖˟˞˄
ˠ˘ˠ˲˕˃˲˖˟˞˅
C0402
X5R
0
1
2
16V
10%
MEM_B_ECC[7..0]
2
10,16 MEM_B_ECC[7..0]
MEM_B_DQS*[8..0]
10,16 MEM_B_DQS*[8..0]
MEM_B_DQS[8..0] ˠ˘ˠ˲˕˲˘˖˖˃
ˠ˘ˠ˲˕˲˘˖˖˄
ˠ˘ˠ˲˕˲˘˖˖˅
ˠ˘ˠ˲˕˲˘˖˖ˆ
ˠ˘ˠ˲˕˲˘˖˖ˇ
ˠ˘ˠ˲˕˲˘˖˖ˈ
ˠ˘ˠ˲˕˲˘˖˖ˉ
ˠ˘ˠ˲˕˲˘˖˖ˊ
10,16 MEM_B_DQS[8..0]
0
1
2
3
4
5
6
7
MEM_B_DM[8..0] ˠ˘ˠ˲˕˲˗ˤ˦ʽ˃
ˠ˘ˠ˲˕˲˗ˤ˦ʽ˄
ˠ˘ˠ˲˕˲˗ˤ˦ʽ˅
ˠ˘ˠ˲˕˲˗ˤ˦ʽˆ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˇ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˈ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˉ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˊ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˋ
10,16 MEM_B_DM[8..0]
0
1
2
3
4
5
6
7
8
MEM_B_ADD[15..0] ˠ˘ˠ˲˕˲˗ˤ˦˃
ˠ˘ˠ˲˕˲˗ˤ˦˄
ˠ˘ˠ˲˕˲˗ˤ˦˅
ˠ˘ˠ˲˕˲˗ˤ˦ˆ
ˠ˘ˠ˲˕˲˗ˤ˦ˇ
ˠ˘ˠ˲˕˲˗ˤ˦ˈ
ˠ˘ˠ˲˕˲˗ˤ˦ˉ
ˠ˘ˠ˲˕˲˗ˤ˦ˊ
ˠ˘ˠ˲˕˲˗ˤ˦ˋ VCC3
10,16,17 MEM_B_ADD[15..0]
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˕˲˗ˠ˃
ˠ˘ˠ˲˕˲˗ˠ˄
ˠ˘ˠ˲˕˲˗ˠ˅
ˠ˘ˠ˲˕˲˗ˠˆ
ˠ˘ˠ˲˕˲˗ˠˇ
ˠ˘ˠ˲˕˲˗ˠˈ
ˠ˘ˠ˲˕˲˗ˠˉ
ˠ˘ˠ˲˕˲˗ˠˊ
ˠ˘ˠ˲˕˲˗ˠˋ VDDMEM
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˕˲˔˗˗˃
ˠ˘ˠ˲˕˲˔˗˗˄
ˠ˘ˠ˲˕˲˔˗˗˅
ˠ˘ˠ˲˕˲˔˗˗ˆ
ˠ˘ˠ˲˕˲˔˗˗ˇ
ˠ˘ˠ˲˕˲˔˗˗ˈ
ˠ˘ˠ˲˕˲˔˗˗ˉ
ˠ˘ˠ˲˕˲˔˗˗ˊ
ˠ˘ˠ˲˕˲˔˗˗ˋ
ˠ˘ˠ˲˕˲˔˗˗ˌ
ˠ˘ˠ˲˕˲˔˗˗˄˃
ˠ˘ˠ˲˕˲˔˗˗˄˄
ˠ˘ˠ˲˕˲˔˗˗˄˅
ˠ˘ˠ˲˕˲˔˗˗˄ˆ
ˠ˘ˠ˲˕˲˔˗˗˄ˇ
ˠ˘ˠ˲˕˲˔˗˗˄ˈ
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
188
183
182
180
179
177
176
196
174
173
125
134
146
155
202
211
223
232
164
105
114
104
113
161
162
167
168
126
135
147
156
203
212
224
233
165
185
137
220
186
138
221
192
193
171
190
195
102
239
240
101
119
120
238
172
178
184
187
189
197
170
175
181
191
194
63
61
60
58
70
57
16
28
37
84
93
46
15
27
36
83
92
45
42
43
48
49
19
73
74
76
52
71
54
77
68
55
18
53
59
64
67
69
51
56
62
72
75
78
7
1
A11
A12
A13
A14
A15
A16/BA2
CKE0
CKE1
CK2
CK1
SCL
CK0
CK2*
TEST
NC
CK1*
CK0*
SA0
SA1
VDD
VDD
VDD
VDD
VDD
A2
A4
A5
A7
BA0
VDD
SA2
VDD
VDD
VDD
VDD
VDD
A0
A1
A3
A6
A8
A9
BA1
A10/AP
PAR_IN
DQS0
S1*
DQS1
SDA
DQS2
DQS6
DQS7
DQS3
DQS4
DQS5
S0*
DM0/DQS9
NC/DQS8
DQS0*
DQS1*
DQS6*
DQS2*
DQS7*
DQS3*
DQS4*
DQS5*
WE*
CAS*
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RAS*
ODT1
VDDQ
VREF
VDDQ
VDDQ
VDDQ
VDDQ
ODT0
NC/DQS8*
NC/DQS9*
RESET*
VDDSPD
DM5/DQS14
DM6/DQS15
DM7/DQS16
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM8/DQS17
NC/CB0
NC/CB1
NC/CB2
NC/CB3
NC/CB4
NC/CB5
NC/CB6
NC/CB7
NC/DQS10*
NC/DQS11*
NC/DQS14*
NC/DQS15*
NC/DQS16*
ERR_OUT*
NC/DQS12*
NC/DQS13*
NC/DQS17*
DIMM240
1.8V
B B
SK-D240P
DIMM2
Default
DQ38
DQ10
DQ11
DQ39
DQ44
DQ45
DQ46
DQ47
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ36
DQ37
DQ42
DQ43
DQ48
DQ49
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ8
DQ9
DQ6
DQ7
?
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
10
12
13
21
22
24
25
30
31
33
34
39
40
80
81
86
87
89
90
95
96
98
99
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
3
4
9
2
5
8
ˠ˘ˠ˲˕˲˗˔˧˔˃
ˠ˘ˠ˲˕˲˗˔˧˔˄
ˠ˘ˠ˲˕˲˗˔˧˔˅
ˠ˘ˠ˲˕˲˗˔˧˔ˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˌ
ˠ˘ˠ˲˕˲˗˔˧˔˄˃
ˠ˘ˠ˲˕˲˗˔˧˔˄˄
ˠ˘ˠ˲˕˲˗˔˧˔˄˅
ˠ˘ˠ˲˕˲˗˔˧˔˄ˆ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˇ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˈ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˉ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˊ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˋ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˌ
ˠ˘ˠ˲˕˲˗˔˧˔˅˃
ˠ˘ˠ˲˕˲˗˔˧˔˅˄
ˠ˘ˠ˲˕˲˗˔˧˔˅˅
ˠ˘ˠ˲˕˲˗˔˧˔˅ˆ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˇ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˈ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˉ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˊ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˋ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˆ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˆ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˆ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˆˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˇ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˇ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˇ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˇˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˈ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˈ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˈ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˈˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˉ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˉ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˉ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˉˆ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
MEM_B_DATA[63..0]
10,16 MEM_B_DATA[63..0]
A A
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
D D
DIMM 3 CHANNEL "A" LOWER 64 BITS
SMB_MEM_SCL
13,14,16,23,35,43 SMB_MEM_SCL
SMB_MEM_SDA
13,14,16,23,35,43 SMB_MEM_SDA
MEM_A1_ODT
9,17 MEM_A1_ODT
MEM_A_BA[2..0]
9,13,17 MEM_A_BA[2..0]
MEM_A1_CKE ˠ˘ˠ˲˔˲˕˔˃
ˠ˘ˠ˲˔˲˕˔˄
ˠ˘ˠ˲˔˲˕˔˅
9,17 MEM_A1_CKE
0
1
2
MEM_A1_CS*[1..0]
9,17 MEM_A1_CS*[1..0]
MEM_A_CAS* ˠ˘ˠ˲˔˄˲˖˦ʽ˃
ˠ˘ˠ˲˔˄˲˖˦ʽ˄
9,13,17 MEM_A_CAS*
0
1
C 9,13,17 MEM_A_RAS*
9,13,17 MEM_A_WE*
MEM_A_RAS*
MEM_A_WE* C
MEM_A1_CLK*[2..0] MEM_VREF
9,17 MEM_A1_CLK*[2..0] 13,14,16 MEM_VREF
1
MEM_A1_CLK[2..0] ˠ˘ˠ˲˔˄˲˖˟˞ʽ˃
ˠ˘ˠ˲˔˄˲˖˟˞ʽ˄
ˠ˘ˠ˲˔˄˲˖˟˞ʽ˅
C17
9,17 MEM_A1_CLK[2..0] 0.1UF/16V/0402-LF
0
1
2
ˠ˘ˠ˲˔˄˲˖˟˞˃
ˠ˘ˠ˲˔˄˲˖˟˞˄
ˠ˘ˠ˲˔˄˲˖˟˞˅
C0402
X5R
0
1
2
16V
10%
MEM_A_ECC[7..0]
2
9,13 MEM_A_ECC[7..0]
MEM_A_DQS*[8..0]
9,13 MEM_A_DQS*[8..0]
MEM_A_DQS[8..0] ˠ˘ˠ˲˔˲˘˖˖˃
ˠ˘ˠ˲˔˲˘˖˖˄
ˠ˘ˠ˲˔˲˘˖˖˅
ˠ˘ˠ˲˔˲˘˖˖ˆ
ˠ˘ˠ˲˔˲˘˖˖ˇ
ˠ˘ˠ˲˔˲˘˖˖ˈ
ˠ˘ˠ˲˔˲˘˖˖ˉ
ˠ˘ˠ˲˔˲˘˖˖ˊ
9,13 MEM_A_DQS[8..0]
0
1
2
3
4
5
6
7
MEM_A_DM[8..0] ˠ˘ˠ˲˔˲˗ˤ˦ʽ˃
ˠ˘ˠ˲˔˲˗ˤ˦ʽ˄
ˠ˘ˠ˲˔˲˗ˤ˦ʽ˅
ˠ˘ˠ˲˔˲˗ˤ˦ʽˆ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˇ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˈ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˉ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˊ
ˠ˘ˠ˲˔˲˗ˤ˦ʽˋ
9,13 MEM_A_DM[8..0]
0
1
2
3
4
5
6
7
8
MEM_A_ADD[15..0] ˠ˘ˠ˲˔˲˗ˤ˦˃
ˠ˘ˠ˲˔˲˗ˤ˦˄
ˠ˘ˠ˲˔˲˗ˤ˦˅
ˠ˘ˠ˲˔˲˗ˤ˦ˆ
ˠ˘ˠ˲˔˲˗ˤ˦ˇ
ˠ˘ˠ˲˔˲˗ˤ˦ˈ
ˠ˘ˠ˲˔˲˗ˤ˦ˉ
ˠ˘ˠ˲˔˲˗ˤ˦ˊ
ˠ˘ˠ˲˔˲˗ˤ˦ˋ VCC3
9,13,17 MEM_A_ADD[15..0]
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˔˲˗ˠ˃
ˠ˘ˠ˲˔˲˗ˠ˄
ˠ˘ˠ˲˔˲˗ˠ˅
ˠ˘ˠ˲˔˲˗ˠˆ
ˠ˘ˠ˲˔˲˗ˠˇ
ˠ˘ˠ˲˔˲˗ˠˈ
ˠ˘ˠ˲˔˲˗ˠˉ
ˠ˘ˠ˲˔˲˗ˠˊ
ˠ˘ˠ˲˔˲˗ˠˋ VDDMEM
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˔˲˔˗˗˃
ˠ˘ˠ˲˔˲˔˗˗˄
ˠ˘ˠ˲˔˲˔˗˗˅
ˠ˘ˠ˲˔˲˔˗˗ˆ
ˠ˘ˠ˲˔˲˔˗˗ˇ
ˠ˘ˠ˲˔˲˔˗˗ˈ
ˠ˘ˠ˲˔˲˔˗˗ˉ
ˠ˘ˠ˲˔˲˔˗˗ˊ
ˠ˘ˠ˲˔˲˔˗˗ˋ
ˠ˘ˠ˲˔˲˔˗˗ˌ
ˠ˘ˠ˲˔˲˔˗˗˄˃
ˠ˘ˠ˲˔˲˔˗˗˄˄
ˠ˘ˠ˲˔˲˔˗˗˄˅
ˠ˘ˠ˲˔˲˔˗˗˄ˆ
ˠ˘ˠ˲˔˲˔˗˗˄ˇ
ˠ˘ˠ˲˔˲˔˗˗˄ˈ
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
188
183
182
180
179
177
176
196
174
173
125
134
146
155
202
211
223
232
164
105
114
104
113
161
162
167
168
126
135
147
156
203
212
224
233
165
185
137
220
186
138
221
192
193
171
190
195
102
239
240
101
119
120
238
172
178
184
187
189
197
170
175
181
191
194
63
61
60
58
70
57
16
28
37
84
93
46
15
27
36
83
92
45
42
43
48
49
19
73
74
76
52
71
54
77
68
55
18
53
59
64
67
69
51
56
62
72
75
78
7
1
A12
A13
A14
A15
A11
A16/BA2
CK0
CK1
CK2
CKE1
SCL
CKE0
CK0*
CK1*
CK2*
SA0
SA1
A0
A1
A3
A6
A8
A9
BA1
A2
A4
A5
A7
BA0
TEST
SA2
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A10/AP
DQS0
DQS1
DQS6
DQS7
DQS2
DQS3
PAR_IN
DQS4
DQS5
S0*
S1*
SDA
DQS0*
DQS1*
DQS6*
DQS7*
DQS2*
DQS3*
DQS4*
DM0/DQS9
DQS5*
ODT0
VREF
NC/DQS8
ODT1
VDDQ
WE*
RAS*
CAS*
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC/DQS8*
NC/DQS9*
RESET*
VDDSPD
DM6/DQS15
DM7/DQS16
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM8/DQS17
NC/CB4
NC/CB5
NC/CB6
NC/CB7
NC/CB0
NC/CB1
NC/CB2
NC/CB3
NC/DQS15*
NC/DQS10*
NC/DQS11*
NC/DQS12*
NC/DQS13*
NC/DQS16*
NC/DQS17*
NC/DQS14*
ERR_OUT*
DIMM240
B B
1.8V
SK-D240P
Default
DIMM3
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ42
DQ43
DQ48
DQ49
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
I151
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
10
12
13
21
22
24
25
30
31
33
34
39
40
80
81
86
87
89
90
95
96
98
99
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
3
4
9
2
5
8
ˠ˘ˠ˲˔˲˗˔˧˔˃
ˠ˘ˠ˲˔˲˗˔˧˔˄
ˠ˘ˠ˲˔˲˗˔˧˔˅
ˠ˘ˠ˲˔˲˗˔˧˔ˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˌ
ˠ˘ˠ˲˔˲˗˔˧˔˄˃
ˠ˘ˠ˲˔˲˗˔˧˔˄˄
ˠ˘ˠ˲˔˲˗˔˧˔˄˅
ˠ˘ˠ˲˔˲˗˔˧˔˄ˆ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˇ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˈ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˉ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˊ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˋ
ˠ˘ˠ˲˔˲˗˔˧˔˄ˌ
ˠ˘ˠ˲˔˲˗˔˧˔˅˃
ˠ˘ˠ˲˔˲˗˔˧˔˅˄
ˠ˘ˠ˲˔˲˗˔˧˔˅˅
ˠ˘ˠ˲˔˲˗˔˧˔˅ˆ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˇ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˈ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˉ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˊ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˋ
ˠ˘ˠ˲˔˲˗˔˧˔˅ˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˆ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˆˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˆˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˇ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˇˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˇˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˈ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˈˆ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˇ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˈ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˉ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˊ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˋ
ˠ˘ˠ˲˔˲˗˔˧˔ˈˌ
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˃
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˄
ˠ˘ˠ˲˔˲˗˔˧˔ˉ˅
ˠ˘ˠ˲˔˲˗˔˧˔ˉˆ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
MEM_A_DATA[63..0]
9,13 MEM_A_DATA[63..0]
A A
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
D D
DIMM 4 CHANNEL "B" UPPER 64 BITS

FURTHEST DIMM TO CPU
SMB_MEM_SCL
13,14,15,23,35,43 SMB_MEM_SCL SMB_MEM_SDA
13,14,15,23,35,43 SMB_MEM_SDA
MEM_B1_ODT
10,17 MEM_B1_ODT
MEM_B_BA[2..0]
10,14,17 MEM_B_BA[2..0]
MEM_B1_CKE ˠ˘ˠ˲˕˲˕˔˃
ˠ˘ˠ˲˕˲˕˔˄
ˠ˘ˠ˲˕˲˕˔˅
10,17 MEM_B1_CKE
0
1
2
MEM_B1_CS*[1..0]
10,17 MEM_B1_CS*[1..0]
MEM_B_CAS* ˠ˘ˠ˲˕˄˲˖˦ʽ˃
ˠ˘ˠ˲˕˄˲˖˦ʽ˄
10,14,17 MEM_B_CAS* MEM_B_RAS*
0
1
10,14,17 MEM_B_RAS* MEM_B_WE*
10,14,17 MEM_B_WE*
MEM_B1_CLK*[2..0] MEM_VREF
10,17 MEM_B1_CLK*[2..0] 13,14,15 MEM_VREF
1
MEM_B1_CLK[2..0] ˠ˘ˠ˲˕˄˲˖˟˞ʽ˃
ˠ˘ˠ˲˕˄˲˖˟˞ʽ˄
ˠ˘ˠ˲˕˄˲˖˟˞ʽ˅
C21
10,17 MEM_B1_CLK[2..0] 0.1UF/16V/0402-LF
C
0
1
2
ˠ˘ˠ˲˕˄˲˖˟˞˃
ˠ˘ˠ˲˕˄˲˖˟˞˄
ˠ˘ˠ˲˕˄˲˖˟˞˅
C0402
X5R
C
0
1
2
16V
10%
MEM_B_ECC[7..0]
2
10,14 MEM_B_ECC[7..0]
MEM_B_DQS*[8..0]
10,14 MEM_B_DQS*[8..0]
MEM_B_DQS[8..0] ˠ˘ˠ˲˕˲˘˖˖˃
ˠ˘ˠ˲˕˲˘˖˖˄
ˠ˘ˠ˲˕˲˘˖˖˅
ˠ˘ˠ˲˕˲˘˖˖ˆ
ˠ˘ˠ˲˕˲˘˖˖ˇ
ˠ˘ˠ˲˕˲˘˖˖ˈ
ˠ˘ˠ˲˕˲˘˖˖ˉ
ˠ˘ˠ˲˕˲˘˖˖ˊ
10,14 MEM_B_DQS[8..0]
0
1
2
3
4
5
6
7
MEM_B_DM[8..0] ˠ˘ˠ˲˕˲˗ˤ˦ʽ˃
ˠ˘ˠ˲˕˲˗ˤ˦ʽ˄
ˠ˘ˠ˲˕˲˗ˤ˦ʽ˅
ˠ˘ˠ˲˕˲˗ˤ˦ʽˆ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˇ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˈ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˉ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˊ
ˠ˘ˠ˲˕˲˗ˤ˦ʽˋ
10,14 MEM_B_DM[8..0]
0
1
2
3
4
5
6
7
8
MEM_B_ADD[15..0] ˠ˘ˠ˲˕˲˗ˤ˦˃
ˠ˘ˠ˲˕˲˗ˤ˦˄
ˠ˘ˠ˲˕˲˗ˤ˦˅
ˠ˘ˠ˲˕˲˗ˤ˦ˆ
ˠ˘ˠ˲˕˲˗ˤ˦ˇ
ˠ˘ˠ˲˕˲˗ˤ˦ˈ
ˠ˘ˠ˲˕˲˗ˤ˦ˉ
ˠ˘ˠ˲˕˲˗ˤ˦ˊ
ˠ˘ˠ˲˕˲˗ˤ˦ˋ VCC3
10,14,17 MEM_B_ADD[15..0]
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˕˲˗ˠ˃
ˠ˘ˠ˲˕˲˗ˠ˄
ˠ˘ˠ˲˕˲˗ˠ˅
ˠ˘ˠ˲˕˲˗ˠˆ
ˠ˘ˠ˲˕˲˗ˠˇ
ˠ˘ˠ˲˕˲˗ˠˈ
ˠ˘ˠ˲˕˲˗ˠˉ
ˠ˘ˠ˲˕˲˗ˠˊ
ˠ˘ˠ˲˕˲˗ˠˋ VDDMEM
0
1
2
3
4
5
6
7
8
ˠ˘ˠ˲˕˲˔˗˗˃
ˠ˘ˠ˲˕˲˔˗˗˄
ˠ˘ˠ˲˕˲˔˗˗˅
ˠ˘ˠ˲˕˲˔˗˗ˆ
ˠ˘ˠ˲˕˲˔˗˗ˇ
ˠ˘ˠ˲˕˲˔˗˗ˈ
ˠ˘ˠ˲˕˲˔˗˗ˉ
ˠ˘ˠ˲˕˲˔˗˗ˊ
ˠ˘ˠ˲˕˲˔˗˗ˋ
ˠ˘ˠ˲˕˲˔˗˗ˌ
ˠ˘ˠ˲˕˲˔˗˗˄˃
ˠ˘ˠ˲˕˲˔˗˗˄˄
ˠ˘ˠ˲˕˲˔˗˗˄˅
ˠ˘ˠ˲˕˲˔˗˗˄ˆ
ˠ˘ˠ˲˕˲˔˗˗˄ˇ
ˠ˘ˠ˲˕˲˔˗˗˄ˈ
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
188
183
182
180
179
177
176
196
174
173
125
134
146
155
202
211
223
232
164
105
114
104
113
161
162
167
168
126
135
147
156
203
212
224
233
165
185
137
220
186
138
221
192
193
171
190
195
102
239
240
101
119
120
238
172
178
184
187
189
197
170
175
181
191
194
63
61
60
58
70
57
16
28
37
84
93
46
15
27
36
83
92
45
42
43
48
49
19
73
74
76
52
71
54
77
68
55
18
53
59
64
67
69
51
56
62
72
75
78
7
1
A11
A12
A13
A14
A15
A16/BA2
CK2
CK0
CK1
CKE0
CKE1
SCL
CK2*
CK0*
CK1*
TEST
SA0
SA1
BA0
BA1
SA2
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
PAR_IN
DQS0
S0*
S1*
DQS1
DQS2
SDA
DQS3
DQS4
DQS5
DQS6
DQS7
DM0/DQS9
NC/DQS8
DQS0*
DQS1*
DQS2*
DQS6*
DQS3*
DQS4*
DQS5*
DQS7*
WE*
RAS*
CAS*
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
ODT0
ODT1
NC/DQS8*
NC/DQS9*
RESET*
VDDSPD
DM5/DQS14
DM6/DQS15
DM7/DQS16
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM8/DQS17
NC/CB0
NC/CB1
NC/CB2
NC/CB3
NC/CB4
NC/CB5
NC/CB6
NC/CB7
NC/DQS14*
NC/DQS15*
NC/DQS16*
NC/DQS10*
NC/DQS11*
NC/DQS12*
NC/DQS13*
NC/DQS17*
ERR_OUT*
DIMM240
1.8V
SK-D240P
B B
Default
DQ10
DQ11
DQ16
DQ17
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ61
DQ62
DQ63
DQ12
DQ13
DQ14
DQ15
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ40
DQ41
DQ42
DQ43
DQ48
DQ49
DQ58
DQ59
DQ60
DIMM4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ8
DQ9
DQ6
DQ7
?
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
10
12
13
21
22
24
25
30
31
33
34
39
40
80
81
86
87
89
90
95
96
98
99
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
3
4
9
2
5
8
ˠ˘ˠ˲˕˲˗˔˧˔˃
ˠ˘ˠ˲˕˲˗˔˧˔˄
ˠ˘ˠ˲˕˲˗˔˧˔˅
ˠ˘ˠ˲˕˲˗˔˧˔ˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˌ
ˠ˘ˠ˲˕˲˗˔˧˔˄˃
ˠ˘ˠ˲˕˲˗˔˧˔˄˄
ˠ˘ˠ˲˕˲˗˔˧˔˄˅
ˠ˘ˠ˲˕˲˗˔˧˔˄ˆ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˇ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˈ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˉ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˊ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˋ
ˠ˘ˠ˲˕˲˗˔˧˔˄ˌ
ˠ˘ˠ˲˕˲˗˔˧˔˅˃
ˠ˘ˠ˲˕˲˗˔˧˔˅˄
ˠ˘ˠ˲˕˲˗˔˧˔˅˅
ˠ˘ˠ˲˕˲˗˔˧˔˅ˆ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˇ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˈ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˉ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˊ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˋ
ˠ˘ˠ˲˕˲˗˔˧˔˅ˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˆ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˆ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˆ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˆˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˆˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˇ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˇ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˇ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˇˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˇˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˈ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˈ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˈ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˈˆ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˇ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˈ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˉ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˊ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˋ
ˠ˘ˠ˲˕˲˗˔˧˔ˈˌ
ˠ˘ˠ˲˕˲˗˔˧˔ˉ˃
ˠ˘ˠ˲˕˲˗˔˧˔ˉ˄
ˠ˘ˠ˲˕˲˗˔˧˔ˉ˅
ˠ˘ˠ˲˕˲˗˔˧˔ˉˆ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
MEM_B_DATA[63..0]
10,14 MEM_B_DATA[63..0]
A A
Title
MCP68/65 HT/CLKS
A3 AN52 V0.1
5 4 3 2 1
5 VDDMEM 4 3 2 1
VDDMEM
9,13,15 MEM_A_ADD[15..0]
MEM_A_ADD[15..0] 10,14,16 MEM_B_ADD[15..0]
MEM_B_ADD[15..0]
C91
PLACE ALL PARTS BETWEEN CPU AND DIMM
15
C89 15 2 1 MEM_A_ADD[15..0]
2
ˠ˘ˠ˲˔˲˔˗˗˄ˈ 1
C0402
ˠ˘ˠ˲˕˲˔˗˗˄ˈ
C0402 9,13,15 MEM_A_ADD[15..0]
C0G C0G VTTMEM
22PF/NPO/50V/0402-LF50V 22PF/NPO/50V/0402-LF50V
5%
C90
5% MEM_A_BA[2..0]
C88 14 9,13,15 MEM_A_BA[2..0]
14 2
ˠ˘ˠ˲˔˲˔˗˗˄ˇ 1 2
ˠ˘ˠ˲˕˲˔˗˗˄ˇ
1
C0402
C0402
C0G C0G MEM_A0_CS*[1..0]
5%
9,13 MEM_A0_CS*[1..0]
5%
C160 13 C161
13 2
ˠ˘ˠ˲˔˲˔˗˗˄ˆ 1 2
ˠ˘ˠ˲˕˲˔˗˗˄ˆ 1 MEM_A1_CS*[1..0]
C0402
C0402 9,15 MEM_A1_CS*[1..0]
C0G
C0G
5%
PLACE ALL PARTS BEHIND DIMMS
5%
C95 12 C97
12 2
ˠ˘ˠ˲˔˲˔˗˗˄˅ 1 2
ˠ˘ˠ˲˕˲˔˗˗˄˅
C0402
1
D D
C0402
C0G
C0G RN11 47-8P4R-LF
5%
5%
C101 MEM_B_ADD2 1 8
11 C99 11 2 1 MEM_B0_CKE R69 47-LF MEM_A_ADD2
2
ˠ˘ˠ˲˔˲˔˗˗˄˄
C0402
1 ˠ˘ˠ˲˕˲˔˗˗˄˄
C0402 10,14 MEM_B0_CKE 2 7
C0G C0G MEM_A1_CKE LF
MEM_A_ADD10 3 6
22PF/NPO/50V/0402-LF50V 22PF/NPO/50V/0402-LF50V 9,15 MEM_A1_CKE
MEM_B_ADD0
LF
5%
C138
5%
C140 4 5
10 10 2 1 R70 47-LF
2
ˠ˘ˠ˲˔˲˔˗˗˄˃ 1
C0402
ˠ˘ˠ˲˕˲˔˗˗˄˃
C0402
C0G
C0G RN4 47-8P4R-LF
5%
C102
5% MEM_A_ADD14 1 8 RN12 47-8P4R-LF
9
C100 9 2 1 MEM_A0_CKE MEM_A_ADD0
2
ˠ˘ˠ˲˔˲˔˗˗ˌ 1
C0402
ˠ˘ˠ˲˕˲˔˗˗ˌ
C0402 9,13 MEM_A0_CKE 2 7 1 8
C0G C0G MEM_A_BA2 3 6 MEM_A_BA1 2 7
5%
C107
5% MEM_A_ADD15 4 5 MEM_B_BA1 3 6
8 C105 8 2 1 MEM_A_BA0
2
ˠ˘ˠ˲˔˲˔˗˗ˋ 1
C0402
ˠ˘ˠ˲˕˲˔˗˗ˋ
C0402 4 5
C0G C0G
5%
C106
5% RN5 47-8P4R-LF
7 C104 7 2 1 MEM_B1_CKE RN13 47-8P4R-LF
2
ˠ˘ˠ˲˔˲˔˗˗ˊ 1
C0402
ˠ˘ˠ˲˕˲˔˗˗ˊ
C0402 10,16 MEM_B1_CKE 1 8
C0G
C0G MEM_B_ADD15 2 7 MEM_B_ADD10 1 8
22PF/NPO/50V/0402-LF50V 22PF/NPO/50V/0402-LF50V MEM_A_RAS*
5%
C116
5% MEM_A_ADD9 3 6 2 7
C114 6 9,13,15 MEM_A_RAS*
6 2
ˠ˘ˠ˲˔˲˔˗˗ˉ 1 2
ˠ˘ˠ˲˕˲˔˗˗ˉ 1
C0402
MEM_B_ADD14 4 5 MEM_B_BA0 3 6
C0402
C0G C0G MEM_A1_CS*0 4 5
5%
C113
5%
5 C115
5 2
ˠ˘ˠ˲˔˲˔˗˗ˈ 1 2
ˠ˘ˠ˲˕˲˔˗˗ˈ 1
C0402
RN6 47-8P4R-LF
C0402
C0G C0G MEM_A_ADD11 1 8 RN14 47-8P4R-LF
22PF/NPO/50V/0402-LF50V 22PF/NPO/50V/0402-LF50V MEM_B_RAS*
5%
C120
5% MEM_B_BA2 2 7 1 8
C118 4 10,14,16 MEM_B_RAS*
4 2
ˠ˘ˠ˲˔˲˔˗˗ˇ 1 2
ˠ˘ˠ˲˕˲˔˗˗ˇ
C0402
1 MEM_A_ADD7 3 6 MEM_A0_CS*0 2 7
C0402
C0G C0G MEM_A_ADD12 4 5 MEM_B1_CS*0 3 6
22PF/NPO/50V/0402-LF50V 22PF/NPO/50V/0402-LF50V MEM_A_WE*
5%
C119
5%
C121 9,13,15 MEM_A_WE* 4 5
3 3 2 1
2
ˠ˘ˠ˲˔˲˔˗˗ˆ 1
C0402
ˠ˘ˠ˲˕˲˔˗˗ˆ
C0402
C0G
C0G RN7 47-8P4R-LF
5%
C124
5% MEM_A_ADD8 1 8 RN15 47-8P4R-LF
C122 2 2 1 MEM_B_ADD12 MEM_B0_CS*0
C 2 2
ˠ˘ˠ˲˔˲˔˗˗˅
22PF/NPO/50V/0402-LF50V
1
C0402
C0G
ˠ˘ˠ˲˕˲˔˗˗˅
22PF/NPO/50V/0402-LF50V
C0402
C0G MEM_A_ADD6
2
3
7
6 10,14,16 MEM_B_WE*
MEM_B_WE*
MEM_A_CAS*
1
2
8
7 C
5%
C125
5% MEM_B_ADD9 4 5 3 6
C123 1 9,13,15 MEM_A_CAS* MEM_B_CAS*
1 2
ˠ˘ˠ˲˔˲˔˗˗˄ 1 2
ˠ˘ˠ˲˕˲˔˗˗˄ 1 4 5
C0402 C0402
C0G
10,14,16 MEM_B_CAS*
C0G
5%
5%
C137 RN8 47-8P4R-LF
0 C136 0 2 1 MEM_A_ADD5 RN16 47-8P4R-LF
2
ˠ˘ˠ˲˔˲˔˗˗˃ 1 ˠ˘ˠ˲˕˲˔˗˗˃
C0402 1 8
C0402
C0G
C0G MEM_B_ADD11 2 7 MEM_B0_ODT 1 8
22PF/NPO/50V/0402-LF50V 22PF/NPO/50V/0402-LF50V 10,14 MEM_B0_ODT MEM_A0_ODT
5%
C152
5% MEM_B_ADD5 3 6 2 7
C149 MEM_B_RAS* 9,13 MEM_A0_ODT MEM_B1_ODT
MEM_A_RAS* 2 1 10,14,16 MEM_B_RAS* 2 1 MEM_B_ADD7 4 5 3 6
9,13,15 MEM_A_RAS* C0402 C0402 10,16 MEM_B1_ODT MEM_A1_ODT
C0G
22PF/NPO/50V/0402-LF50V
C0G
9,15 MEM_A1_ODT 4 5
22PF/NPO/50V/0402-LF50V 5%
C155
5%
MEM_B_CAS* C157
MEM_A_CAS* 2 1 10,14,16 MEM_B_CAS* 2 1 RN9 47-8P4R-LF
9,13,15 MEM_A_CAS* C0402 C0402
C0G
C0G MEM_A_ADD4 1 8 RN18 47-8P4R-LF
5% 5%
C158 MEM_B_ADD8 2 7 MEM_B_ADD13 1 8
MEM_A_WE* C156 MEM_B_WE* 2 1 MEM_A_ADD3 MEM_A_ADD13
9,13,15 MEM_A_WE* 2 1
C0402
10,14,16 MEM_B_WE* C0402 3 6 2 7
C0G
C0G MEM_B_ADD6 4 5 MEM_B1_CS*1 3 6
22PF/NPO/50V/0402-LF50V MEM_B_BA[2..0] 22PF/NPO/50V/0402-LF50V
MEM_A_BA[2..0] 5%
10,14,16 MEM_B_BA[2..0] 5%
C96 MEM_A0_CS*1 4 5
9,13,15 MEM_A_BA[2..0] C94 2
2 2
ˠ˘ˠ˲˔˲˕˔˅ 1 2
ˠ˘ˠ˲˕˲˕˔˅ 1
C0402
C0402
C0G C0G RN10 47-8P4R-LF
5%
C141
5% MEM_B_ADD1 1 8 RN20 47-8P4R-LF
1
C139 1 2 1 MEM_B_ADD4 MEM_A1_CS*1
2
ˠ˘ˠ˲˔˲˕˔˄ 1
C0402
ˠ˘ˠ˲˕˲˕˔˄
C0402
2 7 1 8
C0G C0G MEM_A_ADD1 3 6 MEM_B0_CS*1 2 7
5%
5%
C151 MEM_B_ADD3 4 5 3 6
0
C150 0 2 1
2
ˠ˘ˠ˲˔˲˕˔˃ 1
C0402
ˠ˘ˠ˲˕˲˕˔˃
C0402 4 5
C0G C0G
5% 5%
MEM_A1_CLK*[2..0]
B 9,15 MEM_A1_CLK*[2..0]
9,15 MEM_A1_CLK[2..0]
MEM_A1_CLK[2..0]
10,14,16 MEM_B_ADD[15..0]
MEM_B_ADD[15..0] B
MEM_B_BA[2..0]
MEM_B0_CLK*[2..0] 10,14,16 MEM_B_BA[2..0]
C132 10,14 MEM_B0_CLK*[2..0]
MEM_A0_CLK*[2..0] 0 2 1 0ˠ˘ˠ˲˔˄˲˖˟˞ʽ˃ MEM_B0_CLK[2..0] MEM_B0_CS*[1..0]
9,13 MEM_A0_CLK*[2..0]
ˠ˘ˠ˲˔˄˲˖˟˞˃
C0402
10,14 MEM_B0_CLK[2..0] 10,14 MEM_B0_CS*[1..0]
MEM_A0_CLK[2..0]
9,13 MEM_A0_CLK[2..0] 50V
3.3PF/NPO/50V/0402-LF
5%
C128 MEM_B1_CS*[1..0]
0 0 ˠ˘ˠ˲˕˃˲˖˟˞ʽ˃ 10,16 MEM_B1_CS*[1..0]
2
ˠ˘ˠ˲˕˃˲˖˟˞˃ 1
1
C63 1ˠ˘ˠ˲˔˄˲˖˟˞ʽ˄ MEM_B1_CLK*[2..0] C0402
C130 2
ˠ˘ˠ˲˔˄˲˖˟˞˄
1 10,16 MEM_B1_CLK*[2..0] 50V
3.3PF/NPO/50V/0402-LF
0 2 1 0 ˠ˘ˠ˲˔˃˲˖˟˞ʽ˃
C0402
MEM_B1_CLK[2..0] 5%
ˠ˘ˠ˲˔˃˲˖˟˞˃
C0402 50V
3.3PF/NPO/50V/0402-LF
10,16 MEM_B1_CLK[2..0]
50V
3.3PF/NPO/50V/0402-LF
5%
1
C53 1 ˠ˘ˠ˲˕˃˲˖˟˞ʽ˄
5%
C134 2
ˠ˘ˠ˲˕˃˲˖˟˞˄ 1
2
C173 2ˠ˘ˠ˲˔˄˲˖˟˞ʽ˅ 0 2 1 0ˠ˘ˠ˲˕˄˲˖˟˞ʽ˃
C0402
C64 2
ˠ˘ˠ˲˔˄˲˖˟˞˅ 1
C0402
ˠ˘ˠ˲˕˄˲˖˟˞˃
C0402 50V
3.3PF/NPO/50V/0402-LF
1 2
ˠ˘ˠ˲˔˃˲˖˟˞˄ 1 1 ˠ˘ˠ˲˔˃˲˖˟˞ʽ˄ 5%
C0402 50V 50V
3.3PF/NPO/50V/0402-LF
3.3PF/NPO/50V/0402-LF 5%
50V
3.3PF/NPO/50V/0402-LF
5%
2
C176 2 ˠ˘ˠ˲˕˃˲˖˟˞ʽ˅
5%
C59 2
ˠ˘ˠ˲˕˃˲˖˟˞˅ 1
C0402
1 2 1 1ˠ˘ˠ˲˕˄˲˖˟˞ʽ˄
C175 CRB 1.5pf->3.3pF ˠ˘ˠ˲˕˄˲˖˟˞˄
C0402 50V
3.3PF/NPO/50V/0402-LF
2 2
ˠ˘ˠ˲˔˃˲˖˟˞˅ 1 2 ˠ˘ˠ˲˔˃˲˖˟˞ʽ˅ 5%
C0402 50V
3.3PF/NPO/50V/0402-LF
5%
?
50V
3.3PF/NPO/50V/0402-LF
5%
2
C183 2ˠ˘ˠ˲˕˄˲˖˟˞ʽ˅
CRB 1.5pf->3.3pF
CRB 1.5pf->3.3pF 2
ˠ˘ˠ˲˕˄˲˖˟˞˅ 1
C0402
50V
3.3PF/NPO/50V/0402-LF
5%
CRB 1.5pf->3.3pF
A A
Title
MCP68/65 HT/CLKS
Custom AN52 V0.1
5 4 3 2 1
8 7 6 5 4 3 2 1
U19H
BGA-692_R
MCP68
D XXXX-XXXX-XXXX
D
7 HTCPU_DWN[15..0] HTCPU_DWN[15..0] SEC 1 OF 8 HTCPU_UP[15..0] HTCPU_UP[15..0] 7
0 ˛˧˖ˣ˨˲˗˪ˡ˃AG8 HT_MCP_RXD0_P HT_MCP_TXD0_P AH23 0 ˛˧˖ˣ˨˲˨ˣ˃
1 ˛˧˖ˣ˨˲˗˪ˡ˄AG9 HT_MCP_RXD1_P HT_MCP_TXD1_P AH22 1 ˛˧˖ˣ˨˲˨ˣ˄
2 ˛˧˖ˣ˨˲˗˪ˡ˅AK9 HT_MCP_RXD2_P HT_MCP_TXD2_P AJ21 2 ˛˧˖ˣ˨˲˨ˣ˅
3 ˛˧˖ˣ˨˲˗˪ˡˆ
AJ10 HT_MCP_RXD3_P HT_MCP_TXD3_P AH21 3 ˛˧˖ˣ˨˲˨ˣˆ
4 ˛˧˖ˣ˨˲˗˪ˡˇ
AG12 HT_MCP_RXD4_P HT_MCP_TXD4_P AH19 4 ˛˧˖ˣ˨˲˨ˣˇ
5 ˛˧˖ˣ˨˲˗˪ˡˈ
AG13 HT_MCP_RXD5_P HT_MCP_TXD5_P AH18 5 ˛˧˖ˣ˨˲˨ˣˈ
6 ˛˧˖ˣ˨˲˗˪ˡˉ
AK13 HT_MCP_RXD6_P HT_MCP_TXD6_P AJ17 6 ˛˧˖ˣ˨˲˨ˣˉ
7 ˛˧˖ˣ˨˲˗˪ˡˊ
AJ14 HT_MCP_RXD7_P HT_MCP_TXD7_P AH17 7 ˛˧˖ˣ˨˲˨ˣˊ
8 ˛˧˖ˣ˨˲˗˪ˡˋ
AB10 HT_MCP_RXD8_P HT_MCP_TXD8_P AF22 8 ˛˧˖ˣ˨˲˨ˣˋ
9 ˛˧˖ˣ˨˲˗˪ˡˌ
AD10 HT_MCP_RXD9_P HT_MCP_TXD9_P AB20 9 ˛˧˖ˣ˨˲˨ˣˌ
10 ˛˧˖ˣ˨˲˗˪ˡ˄˃
AF10 HT_MCP_RXD10_P HT_MCP_TXD10_P AC20 10˛˧˖ˣ˨˲˨ˣ˄˃
11 ˛˧˖ˣ˨˲˗˪ˡ˄˄
AC12 HT_MCP_RXD11_P HT_MCP_TXD11_P AE20 11˛˧˖ˣ˨˲˨ˣ˄˄
12 ˛˧˖ˣ˨˲˗˪ˡ˄˅
AB11 HT_MCP_RXD12_P HT_MCP_TXD12_P AD18 12˛˧˖ˣ˨˲˨ˣ˄˅
13 ˛˧˖ˣ˨˲˗˪ˡ˄ˆ
AB13 HT_MCP_RXD13_P HT_MCP_TXD13_P AF18 13˛˧˖ˣ˨˲˨ˣ˄ˆ
14 ˛˧˖ˣ˨˲˗˪ˡ˄ˇ
AF14 HT_MCP_RXD14_P HT_MCP_TXD14_P AB17 14˛˧˖ˣ˨˲˨ˣ˄ˇ
15 ˛˧˖ˣ˨˲˗˪ˡ˄ˈ
AE14 HT_MCP_RXD15_P HT_MCP_TXD15_P AC16 15˛˧˖ˣ˨˲˨ˣ˄ˈ
7 HTCPU_DWN*[15..0] HTCPU_DWN*[15..0] HTCPU_UP*[15..0] HTCPU_UP*[15..0] 7

0 ˛˧˖ˣ˨˲˗˪ˡʽ˃ AH8 HT_MCP_RXD0_N HT_MCP_TXD0_N AJ23 0˛˧˖ˣ˨˲˨ˣʽ˃
1 ˛˧˖ˣ˨˲˗˪ˡʽ˄ AH9 HT_MCP_RXD1_N HT_MCP_TXD1_N AJ22 1˛˧˖ˣ˨˲˨ˣʽ˄
2 ˛˧˖ˣ˨˲˗˪ˡʽ˅ AJ9 HT_MCP_RXD2_N HT_MCP_TXD2_N AK21 2˛˧˖ˣ˨˲˨ˣʽ˅
C 3 ˛˧˖ˣ˨˲˗˪ˡʽˆ AH10 HT_MCP_RXD3_N HT_MCP_TXD3_N AG21 3˛˧˖ˣ˨˲˨ˣʽˆ C
4 ˛˧˖ˣ˨˲˗˪ˡʽˇ AH12 HT_MCP_RXD4_N HT_MCP_TXD4_N AJ19 4˛˧˖ˣ˨˲˨ˣʽˇ
5 ˛˧˖ˣ˨˲˗˪ˡʽˈ AH13 HT_MCP_RXD5_N HT_MCP_TXD5_N AJ18 5˛˧˖ˣ˨˲˨ˣʽˈ
6 ˛˧˖ˣ˨˲˗˪ˡʽˉ AJ13 HT_MCP_RXD6_N HT_MCP_TXD6_N AK17 6˛˧˖ˣ˨˲˨ˣʽˉ
7 ˛˧˖ˣ˨˲˗˪ˡʽˊ AH14 HT_MCP_RXD7_N HT_MCP_TXD7_N AG17 7˛˧˖ˣ˨˲˨ˣʽˊ
8 ˛˧˖ˣ˨˲˗˪ˡʽˋ AC10 HT_MCP_RXD8_N HT_MCP_TXD8_N AG22 8˛˧˖ˣ˨˲˨ˣʽˋ
9 ˛˧˖ˣ˨˲˗˪ˡʽˌ AE10 HT_MCP_RXD9_N HT_MCP_TXD9_N AB19 9˛˧˖ˣ˨˲˨ˣʽˌ
10 ˛˧˖ˣ˨˲˗˪ˡʽ˄˃AG10 HT_MCP_RXD10_N HT_MCP_TXD10_N AD20 10
˛˧˖ˣ˨˲˨ˣʽ˄˃
11 ˛˧˖ˣ˨˲˗˪ˡʽ˄˄AD12 HT_MCP_RXD11_N HT_MCP_TXD11_N AF20 11

˛˧˖ˣ˨˲˨ˣʽ˄˄
12 ˛˧˖ˣ˨˲˗˪ˡʽ˄˅AC11 HT_MCP_RXD12_N HT_MCP_TXD12_N AE18 12

˛˧˖ˣ˨˲˨ˣʽ˄˅
13 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˆ AB12 HT_MCP_RXD13_N HT_MCP_TXD13_N AG18 13

˛˧˖ˣ˨˲˨ˣʽ˄ˆ
14 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˇAG14 HT_MCP_RXD14_N HT_MCP_TXD14_N AB16 14

˛˧˖ˣ˨˲˨ˣʽ˄ˇ
15 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˈAD14 HT_MCP_RXD15_N HT_MCP_TXD15_N AD16 15

˛˧˖ˣ˨˲˨ˣʽ˄ˈ
7 HTCPU_DWNCLK0 HTCPU_DWNCLK0 AJ11 HT_MCP_RX_CLK0_P HT_MCP_TX_CLK0_P AH20 HTCPU_UPCLK0 HTCPU_UPCLK0 7

7 HTCPU_DWNCLK0* HTCPU_DWNCLK0* AH11 HT_MCP_RX_CLK0_N HT_MCP_TX_CLK0_N AG20 HTCPU_UPCLK0* HTCPU_UPCLK0* 7
HTCPU_DWNCLK1 AE12 HT_MCP_RX_CLK1_P HT_MCP_TX_CLK1_P AC18 HTCPU_UPCLK1 3VDUAL +3.3V_DUAL
7 HTCPU_DWNCLK1 HTCPU_UPCLK1 7
7 HTCPU_DWNCLK1* HTCPU_DWNCLK1* AF12 HT_MCP_RX_CLK1_N HT_MCP_TX_CLK1_N AB18 HTCPU_UPCLK1* HTCPU_UPCLK1* 7
2
7 HTCPU_DWNCNTL0 HTCPU_DWNCNTL0 AJ15 HT_MCP_RXCTL0_P HT_MCP_TXCTL0_P AH16 HTCPU_UPCNTL0 HTCPU_UPCNTL0 7 R282
10K-0402-LF
B 7 HTCPU_DWNCNTL0* HTCPU_DWNCNTL0* AH15 HT_MCP_RXCTL0_N HT_MCP_TXCTL0_N AG16 HTCPU_UPCNTL0* HTCPU_UPCNTL0* 7 5% B
7 HTCPU_DWNCNTL1 HTCPU_DWNCNTL1 AB14 RESERVED RESERVED AE16 HTCPU_UPCNTL1 HTCPU_UPCNTL1 7 0402_R
7 HTCPU_DWNCNTL1* HTCPU_DWNCNTL1* AC14 RESERVED RESERVED AF16 HTCPU_UPCNTL1* HTCPU_UPCNTL1* 7

V1P2_LDT HTCPU_REQ*
1
+1.2V_HT
HT_MCP_REQ* AH25
BR18 HT_MCP_STOP* AH24 HTCPU_STOP* HTCPU_STOP* 8
1 2 HTMCP_COMP_VDD AB9 HT_MCP_COMP_VDD HT_MCP_RST* AG23 HTCPU_RST* HTCPU_RST* 8
0402_R 1%
BR22 HT_MCP_PWRGD AG24 HTCPU_PWRGD HTCPU_PWRGD 8
150-1%-0402-LF
1 2 HTMCP_COMP_GND AB8 HT_MCP_COMP_GND
0402_R 1%
150-1%-LF
CLKOUT_200MHZ_P AK25 CPU_CLK CPU_CLK 8
8,43 CPU_THERMTRIP* CLKOUT_200MHZ_N AJ25 CPU_CLK* CPU_CLK* 8
8 CPU_PROCHOT* CPU_PROCHOT* AD8 PROCHOT*/GPIO20 +1.2V
V0.1 CPU_THERMTRIP_MCP65* CPU_THERMTRIP_MCP65* AE8 THERMTRIP*/GPIO58

V1P2 5MIL TRACE
+1.2V V1P2
BFB8 30 OHM/100MHz/3A/0603-LF CPU_SBVREF AF24
11500MA 0603_R FB 2 1.2V_PLLCPUHT AC15 +1.2V_PLL_CPU_HT
19,22 +3.3V_PLL +3.3V_PLL AB15 +3.3V_PLL_CPU CLKOUT_25MHZ AK26 CLKOUT25MHZ
1
BC5 BCT1 BC21 CLK200_TERM_GND AJ26 CLK200MHZ_TERMP_GND

0.1UF/16V/0402-LF 10UF/10V/0805-LF 0.1UF/16V/0402-LF CLK200MHZ_TERMP_GND
2
0402_R 0805_R 0402_R I134 V0.1
X5R X5R X5R
1
A
16V
10%
6.3V
20%
16V
10% BC24 R281 CT74 A
0.1UF/16V/0402-LF 4.7UF/0805Y/10V-LF MCP61/65 STUFF 2.37K
2
2.37K-1%-LF
1%
0402_R 0402_R 0603_R
X5R X5R
16V 6.3V
10% 20%
EMPTY MCP68 EMPTY
2
1
Title
MCP68/65 HT/CLKS
Custom AN52 V0.1
Date: Tuesday, March 06, 2007 Sheet 18 of 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
U19A
BGA-692_R
MCP68
XXXX-XXXX-XXXX
26 PE0_IN[15..0] PE0_IN[15..0] SEC 2 OF 8 PE0_OUT[15..0] PE0_OUT[15..0] 26
0 ˣ˘˃˲˜ˡ˃ H23 PE0_RX0_P PE0_TX0_P G29 0 ˣ˘˃˲ˢ˨˧˃
1 ˣ˘˃˲˜ˡ˄ H25 PE0_RX1_P PE0_TX1_P H27 1 ˣ˘˃˲ˢ˨˧˄
2 ˣ˘˃˲˜ˡ˅ K22 PE0_RX2_P PE0_TX2_P J27 2 ˣ˘˃˲ˢ˨˧˅
3 ˣ˘˃˲˜ˡˆ K24 PE0_RX3_P PE0_TX3_P J30 3 ˣ˘˃˲ˢ˨˧ˆ
4 ˣ˘˃˲˜ˡˇ K26 PE0_RX4_P PE0_TX4_P K29 4 ˣ˘˃˲ˢ˨˧ˇ PE0_REFCLK
PE0_REFCLK 26
5 ˣ˘˃˲˜ˡˈ M22 PE0_RX5_P PE0_TX5_P L29 5 ˣ˘˃˲ˢ˨˧ˈ PE0_REFCLK*
6 ˣ˘˃˲˜ˡˉ 6 ˣ˘˃˲ˢ˨˧ˉ
PE0_REFCLK* 26
M23 PE0_RX6_P PE0_TX6_P M27
7 ˣ˘˃˲˜ˡˊ M26 PE0_RX7_P PE0_TX7_P N27 7 ˣ˘˃˲ˢ˨˧ˊ
1
8 ˣ˘˃˲˜ˡˋ P22 PE0_RX8_P PE0_TX8_P N30 8 ˣ˘˃˲ˢ˨˧ˋ C293 C296
9 ˣ˘˃˲˜ˡˌ 9 ˣ˘˃˲ˢ˨˧ˌ x0.1UF-0402-LF x0.1UF-0402-LF
P26 PE0_RX9_P PE0_TX9_P P29
10 ˣ˘˃˲˜ˡ˄˃ 10ˣ˘˃˲ˢ˨˧˄˃
11 ˣ˘˃˲˜ˡ˄˄
P25 PE0_RX10_P PE0_TX10_P R29
11ˣ˘˃˲ˢ˨˧˄˄
0402_R
X5R
16V
0402_R
X5R
16V
V0.1
T23 PE0_RX11_P PE0_TX11_P T27 10% 10%
12 ˣ˘˃˲˜ˡ˄˅ 12ˣ˘˃˲ˢ˨˧˄˅
2
T26 PE0_RX12_P PE0_TX12_P U27
13 ˣ˘˃˲˜ˡ˄ˆ U23 PE0_RX13_P PE0_TX13_P U30 13ˣ˘˃˲ˢ˨˧˄ˆ
14 ˣ˘˃˲˜ˡ˄ˇ V24 PE0_RX14_P PE0_TX14_P V29 14ˣ˘˃˲ˢ˨˧˄ˇ
15 ˣ˘˃˲˜ˡ˄ˈ V27 PE0_RX15_P PE0_TX15_P W29 15ˣ˘˃˲ˢ˨˧˄ˈ
C PE0_OUT*[15..0] C
PE0_OUT*[15..0] 26
PE0_IN*[15..0] PLACE AT PEX CONNECTOR
26 PE0_IN*[15..0] 0 ˣ˘˃˲˜ˡʽ˃ 0 ˣ˘˃˲ˢ˨˧ʽ˃
H24 PE0_RX0_N PE0_TX0_N G28
1 ˣ˘˃˲˜ˡʽ˄ H26 PE0_RX1_N PE0_TX1_N H28 1 ˣ˘˃˲ˢ˨˧ʽ˄
2 ˣ˘˃˲˜ˡʽ˅ K23 PE0_RX2_N PE0_TX2_N J28 2 ˣ˘˃˲ˢ˨˧ʽ˅
3 ˣ˘˃˲˜ˡʽˆ K25 PE0_RX3_N PE0_TX3_N J29 3 ˣ˘˃˲ˢ˨˧ʽˆ
4 ˣ˘˃˲˜ˡʽˇ K27 PE0_RX4_N PE0_TX4_N K28 4 ˣ˘˃˲ˢ˨˧ʽˇ
5 ˣ˘˃˲˜ˡʽˈ L22 PE0_RX5_N PE0_TX5_N L28 5 ˣ˘˃˲ˢ˨˧ʽˈ
6 ˣ˘˃˲˜ˡʽˉ M24 PE0_RX6_N PE0_TX6_N M28 6 ˣ˘˃˲ˢ˨˧ʽˉ
7 ˣ˘˃˲˜ˡʽˊ M25 PE0_RX7_N PE0_TX7_N N28 7 ˣ˘˃˲ˢ˨˧ʽˊ
8 ˣ˘˃˲˜ˡʽˋ P23 PE0_RX8_N PE0_TX8_N N29 8 ˣ˘˃˲ˢ˨˧ʽˋ
9 ˣ˘˃˲˜ˡʽˌ P27 PE0_RX9_N PE0_TX9_N P28 9 ˣ˘˃˲ˢ˨˧ʽˌ
10 ˣ˘˃˲˜ˡʽ˄˃ P24 PE0_RX10_N PE0_TX10_N R28 10ˣ˘˃˲ˢ˨˧ʽ˄˃
11 ˣ˘˃˲˜ˡʽ˄˄ T24 PE0_RX11_N PE0_TX11_N T28 11ˣ˘˃˲ˢ˨˧ʽ˄˄
12 ˣ˘˃˲˜ˡʽ˄˅ T25 PE0_RX12_N PE0_TX12_N U28 12ˣ˘˃˲ˢ˨˧ʽ˄˅ 3VDUAL
13 ˣ˘˃˲˜ˡʽ˄ˆ V23 PE0_RX13_N PE0_TX13_N U29 13ˣ˘˃˲ˢ˨˧ʽ˄ˆ
1
14 ˣ˘˃˲˜ˡʽ˄ˇ V25 PE0_RX14_N PE0_TX14_N V28 14ˣ˘˃˲ˢ˨˧ʽ˄ˇ
15 ˣ˘˃˲˜ˡʽ˄ˈ V26 PE0_RX15_N PE0_TX15_N W28 15ˣ˘˃˲ˢ˨˧ʽ˄ˈ VCC3
3VDUAL R251
10K-LF
1
26,27,46 PE_WAKE* PE_WAKE* B22 PE_WAKE*/GPIO21 PE0_REFCLK_P Y24 PE0_REFCLK PE0_REFCLK 26
PE0_REFCLK_N Y23 PE0_REFCLK* 3VDUAL PE_RESET*
PE0_REFCLK* 26 PE_RESET* 26,27,46
R260
D2
B 26 PE0_PRSNTX16* PE0_PRSNTX16* AF29 PE0_PRSNTX16* B
1
10K-LF
Q50
D21 R259 G 2N7002/100mA-LF
V1P2 10K-LF Q51
D2
+1.2V
S
SOT23
1BFB5
5000MA
30 OHM/100MHz/3A/0603-LF
0603_R FB
2 +1.2V_PLL_PE_SS W22 +1.2V_PLL_PE_SS PE_RESET* AH29 K1
2N7002/100mA-LF
2
Y22 +1.2V_PLL_PE_SS A G
1
BC10 BC15 HTVDD_VLD R264 0-LF

1UF/16V-LF 0.1UF/16V/0402-LF HTVDD_VLD K2
S
PE_COMP BR21
0603_R
X5R
0402_R
X5R PE_CLK_COMP AJ30 1 2 BAT54A-LF
6.3V 16V
20% 10% 0603_R 1%
2.37K-1%-LF D-SOT23-K1AK2
2
30V
+1.2V V1P2 U22 +1.2V_PLL_PE +3.3V_PLL_PE_SS R22
V22 +1.2V_PLL_PE +3.3V_PLL_PE_SS T22 +3.3V_PLL +3.3V_PLL 18,22
1BFB9 30 OHM/100MHz/3A/0603-LF
2 +1.2V_PLL_PE
1
5000MA 0603_R FB
I107 BC12
1
BC16 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF
0402_R
X5R
0402_R 16V
X5R 10%
16V
2
10%
2
A A
Title
MCP68/65 PEX X16

Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U19B
BGA-692_R
MCP68
XXXX-XXXX-XXXX
SEC 3 OF 8
27 PE1_IN PE1_IN Y28 PE1_RX_P PE1_TX_P AA28 PE1_OUT PE1_OUT 27
27 PE1_IN* PE1_IN* Y27 PE1_RX_N PE1_TX_N AA27 PE1_OUT* PE1_OUT* 27
D
V0.1 add
27 PE2_IN PE2_IN AB29 PE2_RX_P PE2_TX_P AA30 PE2_OUT PE2_OUT 27
27 PE2_IN* PE2_IN* AB28 PE2_RX_N PE2_TX_N AA29 PE2_OUT* PE2_OUT* 27 D
46 PE3_IN PE3_IN AD27 PE3_RX_P PE3_TX_P AC29 PE3_OUT PE3_OUT V0.1
46 add
46 PE3_IN* PE3_IN* AD28 PE3_RX_N PE3_TX_N AC28 PE3_OUT* PE3_OUT* 46
3VDUAL
1 2 1 R261 2x10K-0402-LF AK29 PEA_CLKREQ*/GPIO51 PE1_REFCLK_P Y26 PE1_REFCLK PE1_REFCLK 27
R262 10K-0402-LF PE1_REFCLK_N Y25 PE1_REFCLK* PE1_REFCLK* 27
27 PE1_PRSNT* PE1_PRSNT* AG28 PE1_PRSNT* PE2_REFCLK_P AB23 PE2_REFCLK PE2_REFCLK 27
V0.1 add to PCIE Lan PE2_PRSNT* AG30 PE2_PRSNT* PE2_REFCLK_N AA23 PE2_REFCLK*
27 PE2_PRSNT* PE2_REFCLK* 27
PE3_PRSNT* PE3_PRSNT* AG29 PE3_PRSNT* PE3_REFCLK_P AB24 PE3_REFCLK V0.1 add
PE3_PRSNT* PE3_REFCLK 46
PE3_REFCLK_N AB25 PE3_REFCLK* PE3_REFCLK* 46
CHIPSET PLL POWER OPTION RGMII_RXD[3..0] RGMII_TXD[3..0]
33 RGMII_RXD[3..0] 0 ˥˚ˠ˜˜˲˥˫˗˃ 0 ˥˚ˠ˜˜˲˧˫˗˃
RGMII_TXD[3..0] 33
D26 RGMII_RXD0/MII_RXD0 RGMII_TXD0/MII_TXD0 A28 MII0
1 2
MCP61/65/68 +3.3V_DUAL 1 ˥˚ˠ˜˜˲˥˫˗˄
E26 RGMII_RXD1/MII_RXD1 RGMII_TXD1/MII_TXD1 B28 MII1 BR7 1 0402_R 5%
0-0402-LF
2 1 ˥˚ˠ˜˜˲˧˫˗˄
2 ˥˚ˠ˜˜˲˥˫˗˅ MII2 BR9 1 0402_R 0-0402-LF 2 ˥˚ˠ˜˜˲˧˫˗˅
B26 RGMII_RXD2/MII_RXD2 RGMII_TXD2/MII_TXD2 D28 5%
2
RESERVED +1.2V_DUAL 3 ˥˚ˠ˜˜˲˥˫˗ˆ
B27 RGMII_RXD3/MII_RXD3 RGMII_TXD3/MII_TXD3 E27 MII3 BR11 1 0402_R 5%
0-0402-LF
2 3 ˥˚ˠ˜˜˲˧˫˗ˆ
RGMIITXCLK BR12 0-0402-LF
33 RGMII_RXCLK RGMII_RXCLK A26 RGMII_RXC/MII_RXCLK RGMII_TXC/MII_TXCLK D27 0402_R
1 5%
2 RGMII_TXCLK RGMII_TXCLK 33
3VDUAL RGMII_RXCTL C26 RGMII_RXCTL/MII_RXDV RGMII_TXCTL/MII_TXEN E28 MIITXEN BR10 1 0402_R 5%
2 RGMII_TXCTL
33 RGMII_RXCTL 0-0402-LF RGMII_TXCTL 33
+3.3V_DUAL +1.2V_DUAL +3.3V_DUAL R211x10K-0402-LF BR14 0402_R 5%
2
0-0402-LF
2 1
BR2
33 MII_RX_ER D24 MII_RXER/GPIO36 RGMII/MII_MDC B25 RGMII_MDC RGMII_MDC 33
10K-0402-LF
5% 33 MII_COL E24 MII_COL/GPIO13/MI2C_DATA RGMII/MII_MDIO A25 RGMII_MDIO RGMII_MDIO 33
C V1P2_DUAL EMPTY F23 MII_CRS/GPIO14/MI2C_CLK 3VDUAL +3.3V_DUAL C
0402_R
33 MII_CRS
V0.1 RGMII/MII_PWRDWN*/GPIO37F24 RGMII_COMA* RGMII_COMA* 33
2
3VDUAL 1BFB1
1500MA 0603_R
x30OHM/3A/40mOHM-LF
FB
2 RGMII_INTR* RGMII_INTR* G24 RGMII/MII_INTR*/GPIO35 BR4
1
BUF25_1
BUF_25MHZ C24 1 2 RGMII_25MHZ RGMII_25MHZ 33
R389
2 +3.3V_PLL_MAC_DUAL M9 +3.3V_PLL_MAC_DUAL 0402_R 5% 1.47K-1%-LF
1500MA 0603_R FB 1%
3VDUAL 22-LF
+3.3V_DUAL MII_RESET*/GPIO12 C25 RGMII_RESET* RGMII_RESET* 23,33 0402_R
1
BC7 BC11 R387

1UF/16V-LF 0.1UF/16V/0402-LF
BR3 1 2 MII_COMP_3P3V B23 MII_COMP_3P3V MII_VREF C27 RGMII_MCPVREF
12
0603_R
X5R
0402_R
X5R 1 2 0402_R 1% MII_COMP_GND C23 MII_COMP_GND
1
6.3V 16V
0402_R 1%
49.9-0402-1%-LF BC1 BR5
20% 10%
49.9-0402-1%-LF 0.1UF/16V/0402-LF
1.47K-1%-LF
2
1%
HDMI_TXD0_P AC25 0402_R
X5R 0402_R
HDMI_TXD0_N AC24 1 2 V0.1 16V

10%
BR30 x22-LF
2
HDMI_TXD1_P AC26
V0.1
1
AE29 HDMI_DDC_CLK HDMI_TXD1_N AC27 1 2
BR26
1 2 TP27 TP_HDMI_DATA AE30 AB26 BR29 x22-LF
HDCP_ROM_SCLK HDMI_DDC_DATA HDMI_TXD2_P
0402_R 5%
HDMI_TXD2_N AB27
V0.1 MCP65 REF DSN to GND x0-0402-LF HDCP_ROM_SCLK_R AF28 HDCP_ROM_SCLK
HDCP_ROM_SDATA BR25
1 2 HDCP_ROM_SDATA_R AF30 HDCP_ROM_SDATA
+3.3V VCC3 0402_R 5%
HDMI_TXC0_P AE27
0-0402-LF +3.3V_HDMI AE26 +3.3V_HDMI HDMI_TXC0_N AE28
BR23
1 2 +3.3V_HDMI_PLL_HVDD AF27 +3.3V_HDMI_PLL_HVDD
B
0402_R 5% V0.1 MCP65 REF DSN NC B
1
CHIPSET OPTION x0-0402-LF BC29 BC23 HPLUG_DET3 AH30

BR24
1 2 x1UF/16V-LF x0.1UF-0402-LF
0402_R 5% 0603_R
X5R
0402_R
X5R HDMI_RSET AJ29 HDMI_RSET
2
MCP61/65 EMPTY x0-0402-LF 6.3V
20%
16V
10%
2
R295
DDC_CLK/GPIO17 B6 1K-0402-LF
MCP68 STUFF DDC_DATA/GPIO19 A6
1%
0402_R
V0.1 REF0 ohm to GND JTAG_TRST PULL DOWN FOR MCP65

BR15 10K-0402-LF
DAC_RED D30 DAC_RED JTAG_TCK M7 MCP68_TCK 1 2
TP14 BUG 249232 - CPUREFPLL NOT
1
DAC_GREEN D29 DAC_GREEN JTAG_TDI M5 TP_MCP68_TDI 0402_R 5%
DAC_BLUE C30 DAC_BLUE JTAG_TDO M6 TP_MCP68_TDO TP13

JTAG_TMS M8 TP_MCP68_TMS TP15 LOCKING WHEN SYSTEM IS WARM
2
JTAG_TRST* L9 MCP68_TRST* 1 2
PLACE NEAR MCP68 R382 R381 R380 BR16 10K-0402-LF
B30 DAC_HSYNC 0402_R 5%
0402_R 0402_R 0402_R
5% 5% 5%
DAC_VSYNC C29 DAC_VSYNC
TV_XTALIN D5 TP_TV_XTALIN
0-0402-LF0-0402-LF0-0402-LF TV_XTALOUT E5 TP_TV_XTALOUT
1 R379 2 DAC_RSET B29 DAC_RSET
R383 XTALIN
1
0402_R 5%
1 2DAC_VREF A29 DAC_VREF XTALIN K7
0-0402-LF 0402_R 5%
XTALOUT K8 XTALOUT
0-0402-LF Y4
XTALIN_RTC 25.000MHZ Y3
+3.3V VCC3 XTALIN_RTC K6 32.768KHZ 2HC49_R 1
XTALOUT_RTC K5 XTALOUT_RTC 1 2 I484
50PPM
18PF
1
VCC3 FB28 x30 OHM/100MHz-3A-0603 +3.3V_DAC C412 C413
A 11500MA 2 F28 +3.3V_DAC 4 3 A
1
1
0603_R FB C415 C414 18PF-LF 18PF-LF
1
18PF-LF 18PF-LF
+3.3V VCC3 CT82 R371 0402_R
C0G
0402_R
C0G
x4.7UF/0805Y/10V-LF I508 0402_R 0402_R 50V
5%
50V
5%
C0G C0G
2
50V 50V
2
0603_R
X5R 0-0402-LF 5% 5%
6.3V
2
R250 20%
2
x10K-0402-LF
5%
2
0402_R
1
HDCP_ROM_SDATA V0.1
HDCP_ROM_SCLK
2
R256
8K 10K-0402-LF Title
5%
0402_R
MCP68/65 PEX X1/MII

V0.1
1
Custom AN52
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U19C
BGA-692_R
MCP68
PCI_AD[31..0]
XXXX-XXXX-XXXX PCI_REQ*[4..0]
28,30 PCI_AD[31..0] 0 ˣ˖˜˲˔˗˃
PCI_REQ*[4..0] 28,31
D D14 PCI_AD0 SEC 4 OF 8 PCI_REQ0* G12 ˣ˖˜˲˥˘ˤʽ˃
0
1 ˣ˖˜˲˔˗˄ E14 PCI_AD1 PCI_REQ1* A10 1
ˣ˖˜˲˥˘ˤʽ˄
D
2 ˣ˖˜˲˔˗˅ A13 PCI_AD2 PCI_REQ2*/GPIO40/RS232_DSR*C11 ˣ˖˜˲˥˘ˤʽ˅
2
3 ˣ˖˜˲˔˗ˆ C14 PCI_AD3 PCI_REQ3*/GPIO38/RS232_CTS*H14 ˣ˖˜˲˥˘ˤʽˆ
3
4 ˣ˖˜˲˔˗ˇ A14 PCI_AD4 D13
PCI_REQ4*/GPIO52/RS232_SIN* ˣ˖˜˲˥˘ˤʽˇ
4
5 ˣ˖˜˲˔˗ˈ B14 PCI_AD5
6 ˣ˖˜˲˔˗ˉ C15 PCI_AD6
7 ˣ˖˜˲˔˗ˊ J16 PCI_AD7
8 ˣ˖˜˲˔˗ˋ G16 PCI_AD8 PCI_GNT0* A9 0
9 ˣ˖˜˲˔˗ˌ F16 PCI_AD9 PCI_GNT1* C10 1
PCI_GNT*1
10 ˣ˖˜˲˔˗˄˃ E16 PCI_AD10 B10
PCI_GNT2*/GPIO41/RS232_DTR* 2
11 ˣ˖˜˲˔˗˄˄ 3
PCI_GNT*2
B15 PCI_AD11 J14
PCI_GNT3*/GPIO39/RS232_RTS* PCI_GNT*3
PCI_GNT*3 28
12 ˣ˖˜˲˔˗˄˅ D16 PCI_AD12 C12
PCI_GNT4*/GPIO53/RS232_SOUT* PCI_GNT*4 4
13 ˣ˖˜˲˔˗˄ˆ
PCI_GNT*4 28
C16 PCI_AD13
14 ˣ˖˜˲˔˗˄ˇ D17 PCI_AD14
15 ˣ˖˜˲˔˗˄ˈ C17 PCI_AD15
16 ˣ˖˜˲˔˗˄ˉ J19 PCI_AD16 PCI_INTW* C22 PCI_INTW*
17 ˣ˖˜˲˔˗˄ˊ
PCI_INTW* 28,30,31
J20 PCI_AD17 PCI_INTX* D22 PCI_INTX* PCI_INTX* 28,30,31
18 ˣ˖˜˲˔˗˄ˋ H20 PCI_AD18 PCI_INTY* A22 PCI_INTY*
19 ˣ˖˜˲˔˗˄ˌ
PCI_INTY* 28,30,31
G20 PCI_AD19 PCI_INTZ* A21 PCI_INTZ* PCI_INTZ* 28,30,31
20 ˣ˖˜˲˔˗˅˃ F20 PCI_AD20
21 ˣ˖˜˲˔˗˅˄ E20 PCI_AD21
22 ˣ˖˜˲˔˗˅˅ B18 PCI_AD22
23 ˣ˖˜˲˔˗˅ˆ C19 PCI_AD23 PCI_CLK0 B13 PCI_CLK0 BRN3-2 2 7 22-8P4R-LF PCI_CLKSLOT1
C
PCI_CLKSLOT1 28 C
24 ˣ˖˜˲˔˗˅ˇ D20 PCI_AD24 PCI_CLK1 F14 BRN3-1 1 8 22-8P4R-LF PCI_CLKSLOT2
25 ˣ˖˜˲˔˗˅ˈ
PCI_CLKSLOT2 28
C20 PCI_AD25 PCI_CLK2 D12
26 ˣ˖˜˲˔˗˅ˉ D21 PCI_AD26 PCI_CLK3 E12 PCI_CLK3 BRN3-3 3 6 22-8P4R-LF PCI_CLKSLOT3 PCI_CLKSLOT3 30
27 ˣ˖˜˲˔˗˅ˊ C21 PCI_AD27 PCI_CLK4 H12 BRN3-4 4 5 22-8P4R-LF
28 ˣ˖˜˲˔˗˅ˋ B21 PCI_AD28
29 ˣ˖˜˲˔˗˅ˌ H22 PCI_AD29
30 ˣ˖˜˲˔˗ˆ˃ G22 PCI_AD30 PCI_CLKIN J12 PCI_CLKIN
31 ˣ˖˜˲˔˗ˆ˄ F22 PCI_AD31
28,30 PCI_C/BE*[3..0] PCI_C/BE*[3..0]

0 ˣ˖˜˲˖˂˕˘ʽ˃ H16 PCI_CBE0*
1 ˣ˖˜˲˖˂˕˘ʽ˄ B17 PCI_CBE1*
2 ˣ˖˜˲˖˂˕˘ʽ˅ A18 PCI_CBE2*
3 ˣ˖˜˲˖˂˕˘ʽˆ B19 PCI_CBE3*
28,30,31 PCI_FRAME* PCI_FRAME* C18 PCI_FRAME*

28,30,31 PCI_IRDY* PCI_IRDY* A17 PCI_IRDY* LPC_AD[3..0] LPC_AD[3..0] 32,40
PCI_TRDY* D18 PCI_TRDY* LPC_AD0 G10 LPCAD0 BRN1-4 4 5 22-8P4R-LF ˟ˣ˖˲˔˗˃ 0
28,30,31 PCI_TRDY*
PCI_STOP* F18 PCI_STOP* LPC_AD1 F10 LPCAD1 BRN1-3 3 6 22-8P4R-LF ˟ˣ˖˲˔˗˄ 1
28,30,31 PCI_STOP*
PCI_DEVSEL* E18 PCI_DEVSEL* LPC_AD2 D10 LPCAD2 BRN1-2 2 7 22-8P4R-LF ˟ˣ˖˲˔˗˅ 2 VCC3
28,30,31 PCI_DEVSEL*
PCI_PAR J18 PCI_PAR LPC_AD3 E10 LPCAD3 BRN1-1 1 8 22-8P4R-LF ˟ˣ˖˲˔˗ˆ 3
28,30 PCI_PAR
2
B PCI_PERR* G18 PCI_PERR*/GPIO43/RS232_DCD* +3.3V R221 B
28,30,31 PCI_PERR*
28,30,31 PCI_SERR* PCI_SERR* H18 PCI_SERR*
x10K-LF
28,30,31 PCI_PME* PCI_PME* E22 PCI_PME*/GPIO30 5%
0402_R V0.1 REF NC
C8
LPC_PWRDWN*/GPIO54/EXT_NMI* R392 LPCPWRDWN*
LPCFRAME*
TP9
LPC_FRAME* H10 1 2 LPC_FRAME* LPC_FRAME* 32,40
1
LPC_DRQ0*/GPIO50 C9 0402_R 5%
LPC_DRQ0* LPC_DRQ0* 32
TP_LPC_DRQ1* 22-LF
LPC_DRQ1*/GPIO15/FANRPM1B9 TP8
PCI_RST_SLOT1* RN33-1 1 8 22-8P4R-LF PCI_RESET0* C13 PCI_RESET0* LPC_SERIRQ J10 LPC_SERIRQ
28 PCI_RST_SLOT1* LPC_SERIRQ 32
2
PCI_RST_SLOT2* RN33-2 2 7 22-8P4R-LF PCI_RESET1* G14 PCI_RESET1* R223
28 PCI_RST_SLOT2*
10K-0402-LFSTRAP JMPR
5%
LPC_RST_SIO_TPM* RN33-4 4 5 22-8P4R-LF PCI_RESET2* B11 PCI_RESET2* 0402_R
32 LPC_RST_SIO_TPM* HDA_SDOUT
PCI_RST_IDE*_R RN33-3 3 6 22-8P4R-LF PCI_RESET3* F12 PCI_RESET3* LPC_CLK0 E8 LPC_CLK0 BRN2-3 3 6 22-8P4R-LF
LPC_CLK_SIO
LPC_FRAME
LPC_CLK_SIO 32
1
LPC_RST_FLASH* BRN2-2 7 2 22-8P4R-LF LPC_RESET* D9 LPC_RESET*
DEFAULT*
40 LPC_RST_FLASH*
LPC_CLK1 D8 BRN2-4 4 5 22-8P4R-LF LPC_CLK_FLASH LPC_CLK_FLASH 40
PCI_RST_SLOT3* BRN2-1 8 1 22-8P4R-LF 00 = LPC BIOS* 1-2
30 PCI_RST_SLOT3* I150 01 = PCI BIOS 2-3
10 = SPI BIOS 1-2
11 = RESERVED
5VDUAL V0.2
A A
1
3VDUAL R169
4.7K-LF
1
3VDUAL
PCI_RST_IDE* PCI_RST_IDE*
R197
D2
1
10K-LF
Q43
R194 G 2N7002/100mA-LF
x10K-LF
D2
Q41
PCI_RST_IDE*_R 2N7002/100mA-LF Title

2
G
R193 0-LF
MCP68/65 PCI
S

Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U19D
PLACE CAPS AT CONN BGA-692_R
MCP68
XXXX-XXXX-XXXX
1 1 C417 SEC 5 OF 8 IDE_PDD[15..0] IDE_PDD[15..0] 41
Default 2 SATA_A0_TX_P_C 2 1 SATA_A0_TX_P V2 SATA_A0_TX_P IDE_DATA_P0 AJ3 ˜˗˘˲ˣ˗˗˃ 0
D SATA_A0_TX_N_C 0603_R
C418
SATA_A0_TX_N
SATA1 3 X7R
0.01UF-0402-LF 2 1 V1 SATA_A0_TX_N IDE_DATA_P1 AJ2 ˜˗˘˲ˣ˗˗˄ 1
D
16V 0603_R
THR_SHRD_R 4 C419 10% X7R
0.01UF-0402-LF IDE_DATA_P2 AH3 ˜˗˘˲ˣ˗˗˅ 2
5 SATA_A0_RX_N_C 2 1
16V
10%
SATA_A0_RX_N W3 SATA_A0_RX_N IDE_DATA_P3 AH1 ˜˗˘˲ˣ˗˗ˆ 3
C420
6 SATA_A0_RX_P_C 0603_R
2 1 SATA_A0_RX_P W2 SATA_A0_RX_P IDE_DATA_P4 AG2 4
SATA X7R
0.01UF-0402-LF
16V 0603_R
˜˗˘˲ˣ˗˗ˇ
7 10% X7R IDE_DATA_P5 AF2 ˜˗˘˲ˣ˗˗ˈ 5

0.01UF-0402-LF
16V
I124 10% IDE_DATA_P6 AF4 ˜˗˘˲ˣ˗˗ˉ 6
IDE_DATA_P7 AE6 ˜˗˘˲ˣ˗˗ˊ 7
1 IDE_DATA_P8 AE5 ˜˗˘˲ˣ˗˗ˋ 8
1 C385
Default 2 SATA_A1_TX_P_C 2 1 SATA_A1_TX_P Y8 SATA_A1_TX_P IDE_DATA_P9 AF5 ˜˗˘˲ˣ˗˗ˌ 9
C386
SATA3 SATA_A1_TX_N_C 0603_R
SATA_A1_TX_N 10
V0.1 THR_SHRD_R
3 X7R
0.01UF-0402-LF
16V
2 1
0603_R
Y7 SATA_A1_TX_N IDE_DATA_P10 AF3 ˜˗˘˲ˣ˗˗˄˃
11
4 C381 10% X7R
0.01UF-0402-LF IDE_DATA_P11 AG1 ˜˗˘˲ˣ˗˗˄˄
5 SATA_A1_RX_N_C 2 1
16V
10%
SATA_A1_RX_N Y5 SATA_A1_RX_N IDE_DATA_P12 AG3 ˜˗˘˲ˣ˗˗˄˅ 12
C382
6 SATA_A1_RX_P_C 0603_R
2 1 SATA_A1_RX_P Y6 SATA_A1_RX_P IDE_DATA_P13 AH2 13
SATA X7R
0.01UF-0402-LF
16V 0603_R
˜˗˘˲ˣ˗˗˄ˆ
7 10% X7R IDE_DATA_P14 AJ1 ˜˗˘˲ˣ˗˗˄ˇ 14

0.01UF-0402-LF
16V
I129 10% IDE_DATA_P15 AK2 ˜˗˘˲ˣ˗˗˄ˈ 15
V0.1
1 1 C421 IDE_ADDR_P0 AG6 IDE_ADDR_P0 IDE_ADDR_P0 41
Default 2 SATA_B0_TX_P_C 2 1 SATA_B0_TX_P Y4 SATA_B0_TX_P IDE_ADDR_P1 AJ5 IDE_ADDR_P1
SATA_B0_TX_N_C 0603_R
C422
SATA_B0_TX_N IDE_ADDR_P1 41
SATA2 3 X7R 2 1 Y3 SATA_B0_TX_N IDE_ADDR_P2 AH6 IDE_ADDR_P2
0.01UF-0402-LF
16V 0603_R IDE_ADDR_P2 41
THR_SHRD_R 4 C423 10% X7R
0.01UF-0402-LF
5 SATA_B0_RX_N_C 2 1
16V
10%
SATA_B0_RX_N AA4 SATA_B0_RX_N IDE_CS1_P* AK6 IDE_CS1_P*
SATA_B0_RX_P_C 0603_R
C424
SATA_B0_RX_P IDE_CS1_P* 41
SATA 6 X7R
0.01UF-0402-LF
16V
2 1
0603_R
AA3 SATA_B0_RX_P IDE_CS3_P* AJ6 IDE_CS3_P* IDE_CS3_P* 41
7 10% X7R
0.01UF-0402-LF
16V
IDE_DACK_P* AG5 IDE_DACK_P* IDE_DACK_P* 41
C I134 10% IDE_IOW_P* AH4 IDE_IOW_P* C
IDE_IOW_P* 41
IDE_INTR_P AH5 IDE_INTR_P IDE_INTR_P 41
1 1 C383 IDE_DREQ_P AK3 IDE_DREQ_P R303 IDE_DREQ_P 41
Default 2 SATA_B1_TX_P_C 2 1 SATA_B1_TX_P AA2 SATA_B1_TX_P IDE_IOR_P* AJ4 IDE_IOR_PR*1 2 IDE_IOR_P*
SATA_B1_TX_N_C 0603_R
C384
SATA_B1_TX_N IDE_IOR_P* 41
SATA4 3 X7R 2 1 AA1 SATA_B1_TX_N IDE_RDY_P AK4 IDE_IORDY_P 0603_R 5%
0-0402-LFIDE_IORDY_P 41
0.01UF-0402-LF
16V 0603_R
THR_SHRD_R 4 10% X7R CABLE_DET_P/GPIO63 AF6 CBLE_DET_P
SATA_B1_RX_N_C
C387 0.01UF-0402-LF
16V
SATA_B1_RX_N CABLE_DET_P 41
5 2 1 C388 10% AB1 SATA_B1_RX_N
6 SATA_B1_RX_P_C 0603_R
2 1 SATA_B1_RX_P AB2 SATA_B1_RX_P VCC3 +3.3V
SATA X7R
0.01UF-0402-LF
16V 0603_R
7 10% X7R
0.01UF-0402-LF
2
16V
I139 10%
R310
121-1%-LF
1%
TP_AC3 AC3 RESERVED 0402_R
AC2 RESERVED
IDE_COMP_3P3 AD5 IDE_COMP_3P3V
TP_AD4 IDE_COMP_GND
21
AD4 RESERVED IDE_COMP_GND AD6
AD3 RESERVED
R305
121-1%-LF
1%
0402_R
TP_AE4 AE4 RESERVED

TP_AE3
1
B AE3 RESERVED B
SATA_LED*/GPIO57 A5 SATA_HDLED* SATA_HDLED* 36
AE1 RESERVED
AE2 RESERVED
EMPTY
BR20
SATA_TSTCLK_P AA6 SATA_TSTCLK_P 1 2
+1.2V V1P2 SATA_TSTCLK_N AB6 SATA_TSTCLK_N 0402 5%
X100-LF
2 Y9 +1.2V_PLL_SP_VDD
1500MA 0603_R FB
˨ˡˡ˔ˠ˘˗˲˅˅˲˖˔ˣ˲˜ˊ˄˲˔
SATA_TERMP AB5 SATA_TERMP
1
BC20 +1.2V V1P2
2
0.1UF/16V/0402-LF
0402_R +3.3V VCC3 U13 +1.2V_PLL_SP_SS BR19

X5R
16V +3.3V_PLL 18,19 2.49K-1%-LF
10% U12 +3.3V_PLL_SP_SS 1%
2
V12 +3.3V_PLL_LEG 0402_R
1BFB3
1500MA
30 OHM/100MHz/3A/0603-LF
0603_R FB
2 +3.3V_PLL M12 +3.3V_PLL_DISP
+1.2V V1P2
1
BC9 BC14 BC6 I95
1
1
1UF/16V-LF 0.1UF/16V/0402-LF
1BFB4
1500MA
x30OHM/3A/40mOHM-LF
0603_R FB
2 BC26
0.1UF/16V/0402-LF
0603_R 0.1UF/16V/0402-LF
0402_R 0402_R
X5R X5R X5R
EMPTY 6.3V
20%
16V
10%
16V
10%
0402_R
X5R
16V
2
10%
2
A A
+3.3V_PLL_CPU,+3.3V_PLL_PE_SS
CHIPSET PLL POWER OPTION
+3.3V_PLL_LEG,+3.3V_PLL_SP_SS
MCP61/65/68 +3.3V
+3.3V_PLL_DISP
RESERVED +1.2V
SHARE THE FERRITE BEAD Title
MCP68/65 SATA / IDE

Custom AN52 V0.1
8 7 6 5 4 3 2 1
+3.3V
VCC3
C408 U19E
2
2 1
0402_R BGA-692_R
R398 x10PF C0G
x10K-LF 50V
5%
MCP68 RN36A 1 4 15K-4P2R-0402-LF USB_4
5%
0402_R TP6 XXXX-XXXX-XXXX RN36B 2 3 15K-4P2R-0402-LF USB_4*
B7 GP_REFCLK SEC 6 OF 8 USB0_P M3 USB_0 RN35A 1 4 15K-4P2R-0402-LF USB_5
R397 2
TP_GP_REFCLK
USB_0 39
1 HDABCLK B4 HDA_BCLK USB0_N M4 USB_0* RN35B 2 3 15K-4P2R-0402-LF USB_5*
34 HDA_BITCLK C411
R178 R177 USB_0* 39
1
0402_R 5%
2 1
0402_R 50V 5%
1 21 2
22-LF x10PF C0G USB1_P N3 0402_R 5% 0402_R 5%
USB_1
R402 2 USB_1 39
2
15K-1%-LF 15K-1%-LF
34 HDA_SDOUT 1 HDASDOUT A3 HDA_SDATA_OUT0/GPIO45 USB1_N N4 R165 R164 USB_1* USB_1* 39
R399 34 HDA_SDIN_0 0402_R 5%
A2 HDA_SDATA_IN0/GPIO22 1 21 2 RN37A 1 4 15K-4P2R-0402-LF USB_6
HDA_SDIN_0
10K-0402-LF
VAGP_CHANGE 22-LF B1 HDA_SDATA_IN1/GPIO23/MGPIO0 USB2_P N1 0402_R 5% 0402_R 5%
USB_2 RN37B 2 3 15K-4P2R-0402-LF USB_6*
5%
15K-1%-LF 15K-1%-LF USB_2 39
0402_R
VLR2_CHANGE B2 HDA_SDATA_IN2/GPIO24 USB2_N N2 USB_2* RN38A 1 4 15K-4P2R-0402-LF USB_7
R163 R162 USB_2* 39
C426 1 21 2 RN38B 2 3 15K-4P2R-0402-LF USB_7*
STRAP JMPR
2 1
0402_R
V0.2 GP23&GP24 SWAP USB3_P P1 0402_R 5%
15K-1%-LF
0402_R 5%
15K-1%-LF
USB_3 USB_3 39
1
x10PF C0G
50V
USB3_N P2 R176 R175 USB_3* USB_3* 39
5% 1 21 2
HDA_SDOUT RN40A 15K-4P2R-0402-LF
LPC_FRAME R407 2 V0.2 USB4_P R2 0402_R 5%
15K-1%-LF
0402_R 5%
15K-1%-LF
USB_4 USB_4 40
RN40B
1 4
15K-4P2R-0402-LF
USB_8
1 HDARST* C3 HDA_RESET* USB4_N R3 USB_4* USB_4* 40 2 3 USB_8*
DEFAULT* 1 R405 2 0402_R 5% 22-LF HDASYNC B3 HDA_SYNC/GPIO44 RN39A 1 4 15K-4P2R-0402-LF USB_9
0402_R 5%
1 22
3VDUAL 1 USB5_P P3 USB_5 RN39B 2 3 15K-4P2R-0402-LF USB_9*
USB_5 40
1
22-LF C416 R431 x10K-LF R480 10K-0402-LF
x10PF
USB5_N P4 USB_5* USB_5* 40
00 = LPC BIOS* 1-2 VDDMEM_GPIO F2 GPIO_1
01 = PCI BIOS 1-2 43 VDDMEM_GPIO
0402_R VTT_P F1 GPIO_2/NMI* USB6_P T3 USB_6
10 = SPI BIOS 2-3
C0G
13 VTT_P USB_6 40
V0.1 add 50V
5% F6 GPIO_3/SMI* USB6_N T4 USB_6*
11 = RESERVED 36,40 ROM_EN USB_6* 40
VTT_N_G BRN4A 15K-4P2R-0402-LF
2
J8 GPIO_4/SCI_INTR* 1 4 USB_10
FP_AUDIO_PRESENCE* G3 GPIO_5/INIT* USB7_P U3 USB_7 BRN4B 2 3 15K-4P2R-0402-LF USB_10*
USB_7 40
+3.3V_DUAL +3.3V PCB_VID0 G5 GPIO_6/FERR*/SYS_FERR* USB7_N U4 USB_7* BRN5A 1 4 15K-4P2R-0402-LF USB_11
USB_7* 40
PCB_VID1 G6 GPIO_7/NFERR*/SYS_PERR* BRN5B 2 3 15K-4P2R-0402-LF USB_11*
USB8_P T6 USB_8 USB_8 41
3VDUAL VCC3 SPI_DI D3 GPIO_8/SPI_DI USB8_N T5 USB_8* USB_8* 41
25 SPI_DO SPI_DO D4 GPIO_9/SPI_DO
SPI_CS* E4 GPIO_10/SPI_CS USB9_P T8 USB_9 USB_9 41
2
SPI_CLK E3 GPIO_11/SPI_CLK USB9_N T7 USB_9* USB_9* 41

25 SPI_CLK
R411 R404
10K-0402-LF
x10K-0402-LF MCP65 STRAP USB10_P V5 USB_10
5% 5% USB_10 44
0402_R 0402_R USB10_N V4 USB_10* USB_10* 44
TP_H9 H9 RESERVED
3VDUAL USB11_P V7 USB_11 USB_11 44 CHIPSET USB_RBIAS_GND
3VDUAL
1
USB11_N V6 USB_11* USB_11* 44

2
34 HDA_RST* HDA_RST*
2
MCP61/65 1.1K
34 HDA_SYNC HDA_SYNC R426
2
x10K-0402-LF
R423
HDA_RST*
5%
x10K-0402-LF USB_OC0*/GPIO25 P7
MCP68 732
R406 0402_R
5%
USB_OC01* USB_OC01* 39
1* = RGMII 10K-0402-LF 0402_R USB_OC1*/GPIO26 P8 USB_OC23*
5% USB_OC23* 39
0 = MII 0402_R USB_OC2*/GPIO27 P9 USB_OC45*
13 VTT_N USB_OC45* 40
Q69
D1
USB_OC3*/GPIO28/MGPIO1P5 USB_OC67* USB_OC67* 40

+3.3V +3.3V_DUAL
HDA_SYNC
1
USB_OC4*/GPIO29 P6 USB_OC98* USB_OC89* 41

(SIO CLK) VTT_N_G
1
G 2 1 BR17
1* = 24MHZ R481 x0-0402-LF USB_RBIAS_GND T9 USB_RBIAS_GND 1 2
0 = 14.318MHZ V0.1 V0.2 SOT23 0603_R 1% V0.1 1.1K->1.0K
S
*DEFAULT x2N7002/100mA-LF 1.0K-1%-LF VCC3 3VDUAL

A20GATE/GPIO55 F5 A20GATE A20GATE 32
3VDUAL 2 1 INTRUDER* K2 INTRUDER* INTRUDER* 38
2
R482 0-0402-LF EXT_SMI*/GPIO32 F3 EXTSMI* RN30-4 4 5 2.7K-8P4R-LF

EXTSMI* 32
V0.1 1R416 x10K-LF
2 PCB_VID0 R483 RI*/GPIO33 H4 SER_RI* SER_RI* 32
RN30-3 3 6 2.7K-8P4R-LF
10K-0402-LF SPKR C7 SPEAKER RN30-2 2 7 2.7K-8P4R-LF
5% SPEAKER 34,36
R417 1K-LF 0402_R PWRBTN* G4 PWRBTN* RN30-1 1 8 2.7K-8P4R-LF
PWRBTN* 32
SIO_PME*/GPIO31 F4 IO_PME* IO_PME* 32
KBRDRSTIN*/GPIO56 A4 SIO_KBRST* SIO_KBRST* 32
3VDUAL
1
SMB_CLK0 C2 SMBMCLK RN29-4 4 5 0-8P4R-LF SMB_MEM_SCL SMB_MEM_SCL 13,14,15,16,35,43

1R418 x10K-LF
2 PCB_VID1 SMB_DATA0 C1 SMBMEMDATA RN29-3 3 6 0-8P4R-LF SMB_MEM_SDA SMB_MEM_SDA 13,14,15,16,35,43
RTC_RST* K4 RTC_RST* SMB_CLK1/MSMB_CLK D2 SMBSCL RN29-2 2 7 0-8P4R-LF SMB_SCL
36 RTC_RST* SMB_SCL 26,27,28,30,32
R419 1K-LF SMB_DATA1/MSMB_DATA E2 SMBSDA RN29-1 1 8 0-8P4R-LF SMB_SDA SMB_SDA 26,27,28,30,32
37 MEM_VLD MEM_VLD J3 MEM_VLD +3.3V_VBAT K3 +3.3V_VBAT VBATCCMOS
HTVDD_VLD H3 MCPVDD/HT_VLD BUF_SIO_CLK B5 BUF_SIO_CLK_R R390 1 2 22-LF
37 HTVDD_VLD BUF_SIO_CLK 32
HTVDD_EN J4 MCPVDD/HT_EN SUS_CLK/GPIO34 E1 SUS_CLK_R 0402_R 5%
43 HTVDD_EN
1
CPU_VLD R242 0-LF J1 CPU_VLD THERM*/GPIO59 C6 MCP_THERM* BC2
35,43 CPU_VLD MCP_THERM* 32 0.1UF/16V/0402-LF
0.1UF/16V-LF CPUVDD_EN J2 CPUVDD_EN RSTBTN* H5 FP_RESET* R375
35 CPUVDD_EN FP_RESET* 36 10K-0402-LF
SLP_S5* H8 SLP_S5* SLP_S5* 37,43 5%
0402_R
X5R
C286 SLP_S3* G8 SLP_S3* 0402_R
16V
10%
SLP_S3* 32,43
2
PWRGD_SB H6 PWRGD_SB PWRGD_SB 35,43
PS_PWRGD G2 MCP55_PWRGD MCP55_PWRGD 37,43
1
FANRPM0/GPIO60 E6
FANCTL0/GPIO61 D6 SPI_HOLD*
FANCTL1/GPIO62 C5 TP_SYSFAN_CNTL
TP11 23,36 ROM_EN
THERM_SIC/GPIO48 AH7 THERM_SIC OD 3VDUAL
SPI_CS* THERM_SIC 8
24 IN L8 PKG_TEST THERM_SID/GPIO49 AF8 THERM_SID OD
MCP68 SPI CLK STRAP THERM_SID 8
TESTMODE
F8 TEST_MODE_EN AE7
THERM_SID1/GPIO47/PWR_LED* TP_THERM_SID1 OD TP16 3VDUAL_SPI
2
SPI1
SPI_DO|SPI_CLK SPI_DI I189
24 OUT BR6 1 VCC3 GND 2
1K-0402-LF 3VDUAL 3VDUAL_SPI 3VDUAL_SPI +3.3V_DUAL SPI_CS*_R 3 4 SPI_CLK_R
00 = 31MHZ 5%
MCP STRAPS SPI_DI_R CS# CLK SPI_DO_R
0402_R 5 SO SI 6
01 = 42MHZ 3VDUAL_SPI +3.3V_DUAL 7 8
A
X HOLD#
2
*10 = 25MHZ
SOT23
D22 3VDUAL
2
1
11 = 1MHZ 3VDUAL +3.3V_DUAL C454
1
U21 0.1UF/16V/0402-LF R425 R428 R430

R422 xBAT54A-LF 10K-0402-LF 10K-0402-LF 10K-0402-LF V0.2 xSPI_HEADER2X4-LF
K1
K2
*DEFAULT x10K-0402-LF PM25LV04033SCE 5% 5% 5%
3VDUAL 5% SOIC_R
0402_R
X5R
16V
0402_R 0402_R 0402_R
V0.2
0402_R 10%
SPI_HOLD*
R468 x0-0402-LF
2
R470 x33-LF SPI_CS*_R

SPI
VCC3
V0.1
1
SPI_CS* LF 1 CS*(I) 8 23,36 ROM_EN
1
R471 x33-LF SPI_DI_R HOLD*(I) SPI_HOLD* R469 x0-0402-LF

1
SPI_DI LF 2 DO(O) 7 SPI_HOLD*

MCP61/65 SPI CLK STRAP R433 3 WP*(I) SCLK(I) 6 SPI_CLK_R R472 LF x33-LF
DI(I/O)
SPI_CLK
x4.7K-0402-LF 4 GND 5 SPI_DO_R R473 LF x33-LF
D
SPI_DO
2
SPI_DO|SPI_CLK
Q70 SERIAL FLASH SPI_DO
R427 SPI_CLK IN 24
00 = 500KHZ G 4MBIT I186 x10K-0402-LF 24
01 = 1.8MHZ 23,36 ROM_EN 5% IN
x2N7002/100mA-LF C436
2
0402_R
10 = 2.5MHZ
S
x1UF/16V-LF
*11 = 25MHZ
Title
1
*DEFAULT
MCP68/65 AUDIO / USB / MISC
Custom AN52 V0.1
8 7 6 5 4 3 2 1
U19G
BGA-692_R
P19 GND
MCP68 GND M15
V1P2_LDT +1.2V_HT V1P2 +1.2V H19 GND
XXXX-XXXX-XXXX GND AK14
U19F
AE11 GND SEC 8 OF 8 GND P15
BGA-692_R
D D7 GND GND W6
+1.2V V1P2 MCP68 G27 GND GND N19
XXXX-XXXX-XXXX D
AB7 GND GND AC8
1
AK27 +1.2V SEC 7 OF 8 +1.2V_HT W15 T15 GND GND N12
5000MA
AH27 +1.2V +1.2V_HT W16 0603_R
FB14 U2 GND GND N14
30 OHM/100MHz/3A/0603-LF
AJ27 +1.2V +1.2V_HT W17 FB
P13 GND GND P14
AG26 +1.2V AC9 GND GND M14
2
AG25 +1.2V +1.2V_PEA AK28 1P2V_PEA 1P2V_PEA 25 N25 GND GND M13
U18 +1.2V +1.2V_PEA AJ28 G26 GND GND U1
AE22 +1.2V +1.2V_PEA AH28 F17 GND GND R9
AE23 +1.2V +1.2V_PEA AG27 F15 GND GND N9
V19 +1.2V +1.2V_PEA AF26 F13 GND GND P12
V18 +1.2V +1.2V_PEA AE25 F11 GND GND D23
U19 +1.2V +1.2V_PEA AD24 F9 GND GND AK30
W19 +1.2V +1.2V_PEA AC23 D25 GND GND H7
W18 +1.2V H17 GND GND A30
V15 +1.2V D19 GND GND AB3
U16 +1.2V V1P2 +1.2V J17 GND GND K9
T14 +1.2V H13 GND GND F30
W14 +1.2V AH26 GND GND N8
AB21 +1.2V +1.2V_SP_D V13 AA9 GND GND F7
AC21 +1.2V +1.2V_SP_D W13 AE21 GND GND J21
1
U14 +1.2V +1.2V_SP_D V14 AE19 GND GND K1
5000MA
T18 +1.2V +1.2V_SP_D W12 0603_R
BFB7 AE17 GND GND AB30
C 30 OHM/100MHz/3A/0603-LF C
U15 +1.2V FB
AE15 GND GND V30
R15 +1.2V AE13 GND GND P30
2
V17 +1.2V AA8 GND GND K30
V16 +1.2V +1.2V_SP_A W9 1P2V_SP_A 1P2V_SP_A 25 AK22 GND GND H21
R17 +1.2V +1.2V_SP_A W8 AG19 GND GND AD26
T16 +1.2V +1.2V_SP_A V8 AK18 GND GND AA25
U17 +1.2V +1.2V_SP_A V9 AG15 GND GND W25
R19 +1.2V +1.2V_SP_A U9 C4 GND GND U25
E30 GND GND R25
D15 GND GND L25
D11 GND GND J25
V1P2_DUAL +1.2V_DUAL J6 GND GND W27
AB22 +1.2V_PED L6 GND GND N13
AE24 +1.2V_PED +1.2V_DUAL F26 N6 GND GND R27
AD22 +1.2V_PED +1.2V_DUAL F27 R6 GND GND L27
AA22 +1.2V_PED U6 GND GND W23
AC22 +1.2V_PED N22 GND GND U8
R13 GND GND J9
3VDUAL +3.3V_DUAL M19 GND GND AE9
AK1 GND GND AG7
+3.3V_DUAL L4 J23 GND GND F25
+3.3V_DUAL J22 R23 GND GND P18
B M18 GND GND F21 B
+3.3V VCC3 +3.3V_USB_DUAL L3 N18 GND GND F19
+3.3V_USB_DUAL L2 P16 GND GND F29
H15 +3.3V N15 GND GND AK5
J15 +3.3V C391 C398 V0.1 R18 GND GND R4
AC6 +3.3V T13 GND GND V3
AC5 +3.3V 0.1UF/16V-LF 0.1UF/16V-LF T17 GND GND W4
M17 GND GND AC4
I20 L23 GND GND C28
P17 GND GND T19
J11 GND GND AC13
R16 GND GND AK10
PLACE CAPS CLOSE TO 3.3V_USB_DUAL A1 GND GND AF1
ISSUES IN THE PAST J13 GND GND AG4
M16 GND GND R8
N16 GND GND A27
N17 GND GND H11
AG11 GND GND D1
N23 GND GND AC19
R14 GND GND AC17
T12 GND GND E29
R12 GND GND AJ7
AC7 GND GND AB4
A I21 A
Title
MCP68/65 PWR / GND

Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP68 DECOUPLING
PLACE ON BACK SIDE
D CENTER OF MCP68
D
V1P2 +1.2V
VCC3 +3.3V
V1P2_LDT +1.2V_HT
1
1
C234 CT71 BC35 BC32
1
x1UF 4.7UF/0805Y/10V-LF x0.1UF 0.1UF/16V/0402-LF C399 C400 C390 BC8
1
0.1UF/16V/0402-LFx0.1UF x0.1UF 0.1UF/16V/0402-LF BC18 C300
0402_R 0603_R 0402_R 0402_R
X5R X5R X5R X5R
6.3V 6.3V 16V 16V x0.1UF 0.1UF/16V/0402-LF
10% 10% 10% 10% 0402_R 0402_R 0402_R 0402_R
X5R X5R X5R X5R
16V 16V 16V 16V
2
2
0402_R 0402_R
10% 10% 10% 10% X5R X5R
16V 16V
2
10% 10%
2
V1P2 +1.2V
1
1
CT56 CT70 CT59 C255 CT58 C238 C274 BC33 C241 C236 BC31 C284 BC34
EMPTY x10UF/10V/0805-LF
10UF/10V/0805-LF x4.7UF/0805Y/10V-LF x1UF
4.7UF/0805Y/10V-LF
0.1UF/16V/0402-LF x0.1UF x0.1UF 1UF/16V-LF x1UF x0.1UF x0.1UF 0.1UF/16V/0402-LF
0805_R 0805_R 0805_R 0402_R 0603_R 0402_R 0402_R 0402_R 0402_R 0402_R 0402_R 0402_R 0402_R
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
6.3V 6.3V 6.3V 16V 6.3V 6.3V 16V 16V 6.3V 6.3V 16V 16V 16V
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
2
C C
24 1P2V_PEA 1P2V_PEA
1
1
CT77 C346 CT76 BC25 BC28 BC27 BC30
x10UF/10V/0805-LF 1UF/16V-LF 4.7UF/0805Y/10V-LF
x0.1UF-0402-LF x0.1UF-0402-LF x0.1UF-0402-LF x0.1UF-0402-LF
0805_R 0603_R 0603_R 0402_R 0402_R 0402_R 0402_R

X5R X5R X5R X5R X5R X5R X5R
6.3V 6.3V 6.3V 16V 16V 16V 16V
20% 20% 10% 10% 10% 10% 10%
2
2
3VDUAL +3.3V_DUAL V1P2_DUAL +1.2V_DUAL
24 1P2V_SP_A 1P2V_SP_A
1
1
BC17 BC13 C375 C377 C428 BC4 C302 BC3
0.1UF/16V/0402-LFx0.1UF 0.1UF/16V/0402-LFx0.1UF x0.1UF x0.1UF 0.1UF/16V/0402-LFx0.1UF
0402_R 0402_R 0402_R 0402_R 0402_R 0402_R 0402_R 0402_R

X5R X5R X5R X5R X5R X5R X5R X5R
16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10%
2
2
B B
A A
Title
MCP68/65 DECOUPLING/SPI
Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SLOT 7
PCIEXP1
+12V VCC12 CONN_R VCC12 +12V
PCI_EXPRESS_X16
Default
B1 +12V
RIGHT PRSNT1* A1 VCC3 +3.3V
D B2 +12V +12V A2
B3 +12V +12V A3 D
+3.3V B4 GND GND A4
23,27,28,30,32 SMB_SCL SMB_SCL B5 SMCLK TCK A5
VCC3 SMB_SDA B6 SMDAT TDI A6
23,27,28,30,32 SMB_SDA
+3.3V_DUAL B7 GND TDO A7 V0.1
3VDUAL B8 +3.3V TMS A8
PE_TRST* B9 TRST* +3.3V A9
B10 +3.3V_AUX +3.3V A10
19,27,46 PE_WAKE* PE_WAKE*
R287 B11 WAKE* PERST* A11 PE_RESET* PE_RESET* 19,27,46
1 2
0603_R 5%
B12 RSVD GND A12
10K-0402-LF
19 PE0_OUT[15..0] PE0_OUT[15..0] C307 B13 GND X1 CONNECTOR REFCLK+ A13 PE0_REFCLK PE0_REFCLK 19
19 PE0_OUT*[15..0] PE0_OUT*[15..0] 0 ˣ˘˃˲ˢ˨˧˃
C308 2 1 PE_TX0
0402_R
B14 PETP0 REFCLK- A14 PE0_REFCLK* PE0_REFCLK* 19
0 ˣ˘˃˲ˢ˨˧ʽ˃ 2 1 X5R PE_TX0* B15 PETN0 GND A15 PE0_IN[15..0]
0402_R
0.1UF/16V/0402-LF
16V
0 ˣ˘˃˲˜ˡ˃
PE0_IN[15..0] 19
X5R
0.1UF/16V/0402-LF
16V
10% B16 GND PERP0 A16 PE0_IN*[15..0] PE0_IN*[15..0] 19
10% B17 PRSNT2* PERN0 A17 0 ˣ˘˃˲˜ˡʽ˃
B18 GND GND A18
C309
1 ˣ˘˃˲ˢ˨˧˄
C310 2 1 PE_TX1
0402_R
B19 PETP1 RSVD A19
1 ˣ˘˃˲ˢ˨˧ʽ˄ 2 1 X5R PE_TX1*
0.1UF/16V/0402-LF B20 PETN1 X4 CONNECTOR GND A20
0402_R 16V
X5R 10% B21 GND PERP1 A21 1 ˣ˘˃˲˜ˡ˄
0.1UF/16V/0402-LF
16V
10% B22 GND PERN1 A22 1 ˣ˘˃˲˜ˡʽ˄
C311
2 ˣ˘˃˲ˢ˨˧˅
C312 2 1 PE_TX2
0402_R
B23 PETP2 GND A23
C 2 ˣ˘˃˲ˢ˨˧ʽ˅ 2 1 X5R PE_TX2* B24 PETN2 GND A24 C
0402_R
0.1UF/16V/0402-LF
16V
X5R
0.1UF/16V/0402-LF
16V
10%
C313
10% B25
B26
GND
GND
PERP2
PERN2
A25
A26
2 ˣ˘˃˲˜ˡ˅
2 ˣ˘˃˲˜ˡʽ˅ MATCH TX LANES 0-3, 12-15 <2.0"
3 ˣ˘˃˲ˢ˨˧ˆ
C314 2 1 PE_TX3
0402_R
B27 PETP3 GND A27
3 ˣ˘˃˲ˢ˨˧ʽˆ 2 1 X5R PE_TX3*
0.1UF/16V/0402-LF B28 PETN3 GND A28
0402_R 16V
X5R 10% B29 GND PERP3 A29 3 ˣ˘˃˲˜ˡˆ
0.1UF/16V/0402-LF
16V
10% B30
B31
RSVD
PRSNT2*
PERN3
GND
A30
A31
3 ˣ˘˃˲˜ˡʽˆ
PLACE CAPS NEAR PEX CONNECTOR
B32 GND RSVD A32
C315
4 ˣ˘˃˲ˢ˨˧ˇ
C316 2 1 PE_TX4
0402_R
B33 PETP4 RSVD A33
4 ˣ˘˃˲ˢ˨˧ʽˇ 2 1 X5R PE_TX4*
0402_R 16V
X5R 10% B35 GND PERP4 A35 4 ˣ˘˃˲˜ˡˇ
0.1UF/16V/0402-LF
16V
10%
C317 B36 GND PERN4 A36 4 ˣ˘˃˲˜ˡʽˇ VCC12 +12V
5 ˣ˘˃˲ˢ˨˧ˈ
C318 2 1 PE_TX5
0402_R
B37 PETP5 GND A37
5 ˣ˘˃˲ˢ˨˧ʽˈ 2 1 X5R PE_TX5*
0402_R 16V
X5R 10% B39 GND PERP5 A39 5 ˣ˘˃˲˜ˡˈ
0.1UF/16V/0402-LF
1
16V C334 C244 C245
10%
C319 B40 GND PERN5 A40 5 ˣ˘˃˲˜ˡʽˈ
V0.2 CE28
x0.1UF
680UF/MBZ/16V/DIP-LF x0.1UF x0.1UF
6 ˣ˘˃˲ˢ˨˧ˉ
C320 2 1 PE_TX6
0402_R
B41 PETP6 GND A41
6 ˣ˘˃˲ˢ˨˧ʽˉ 2 1 X5R PE_TX6*
0.1UF/16V/0402-LF B42 PETN6 GND A42 ECD-10-5
ALUM
0603_R
X7R
0603_R
X7R
0603_R
X7R
0402_R 16V 16V 50V 50V 50V
X5R 10% B43 GND PERP6 A43 6 ˣ˘˃˲˜ˡˉ 20% 10% 10% 10%
0.1UF/16V/0402-LF
16V
6 ˣ˘˃˲˜ˡʽˉ
2
10%
C321 B44 GND PERN6 A44
B
7 ˣ˘˃˲ˢ˨˧ˊ
C322 2 1 PE_TX7
0402_R
B45 PETP7 GND A45 B
7 ˣ˘˃˲ˢ˨˧ʽˊ 2 1 X5R PE_TX7*
0402_R 16V
VCC3 X5R
0.1UF/16V/0402-LF 10% B47 GND PERP7 A47 7 ˣ˘˃˲˜ˡˊ
R288 16V
7 ˣ˘˃˲˜ˡʽˊ
1 2 10% B48 PRSNT2* PERN7 A48
R0402 5%
B49 GND GND A49 VCC3 +3.3V
10K-0402-LF C323
8 ˣ˘˃˲ˢ˨˧ˋ
C324 2 1 PE_TX8
0402_R
B50 PETP8 RSVD A50
8 ˣ˘˃˲ˢ˨˧ʽˋ 2 1 X5R PE_TX8*
1
0402_R 16V CE29 C265 C285
X5R 10% B52 GND PERP8 A52 8 ˣ˘˃˲˜ˡˋ
0.1UF/16V/0402-LF
16V
8 ˣ˘˃˲˜ˡʽˋ 1000UF/YXG/6.3V/DIP-LF x0.1UF x0.1UF
10%
C325 B53 GND PERN8 A53
9 ˣ˘˃˲ˢ˨˧ˌ
C326 2 1 PE_TX9
0402_R
B54 PETP9 GND A54 RDL_R
ALUM
0603_R
X7R
0603_R
X7R
9 ˣ˘˃˲ˢ˨˧ʽˌ 2 1 X5R PE_TX9*
10V
20%
50V
10%
50V
10%
0402_R 16V
9 ˣ˘˃˲˜ˡˌ
2
X5R
0.1UF/16V/0402-LF
16V
10% B56 GND PERP9 A56
10% B57 GND PERN9 A57 9 ˣ˘˃˲˜ˡʽˌ
C327
10 ˣ˘˃˲ˢ˨˧˄˃
C328 2 1 PE_TX10
0402_R
B58 PETP10 GND A58
10 ˣ˘˃˲ˢ˨˧ʽ˄˃ 2 1 X5R PE_TX10*
0.1UF/16V/0402-LF B59 PETN10 GND A59
0402_R 16V
X5R 10% B60 GND PERP10 A60 10ˣ˘˃˲˜ˡ˄˃
0.1UF/16V/0402-LF
16V
10% B61 GND PERN10 A61 10ˣ˘˃˲˜ˡʽ˄˃
C329
11 ˣ˘˃˲ˢ˨˧˄˄
C330 2 1 PE_TX11
0402_R
B62 PETP11 GND A62
11 ˣ˘˃˲ˢ˨˧ʽ˄˄ 2 1 X5R PE_TX11*
0.1UF/16V/0402-LF B63 PETN11 GND A63
0402_R 16V
X5R 10% B64 GND PERP11 A64 11ˣ˘˃˲˜ˡ˄˄
0.1UF/16V/0402-LF
16V
10% B65 GND PERN11 A65 11ˣ˘˃˲˜ˡʽ˄˄
C331
12 ˣ˘˃˲ˢ˨˧˄˅
C332 2 1 PE_TX12
0402_R
B66 PETP12 GND A66
12 ˣ˘˃˲ˢ˨˧ʽ˄˅ 2 1 X5R PE_TX12*
0.1UF/16V/0402-LF B67 PETN12 GND A67
0402_R 16V
X5R 10% B68 GND PERP12 A68 12ˣ˘˃˲˜ˡ˄˅
A 0.1UF/16V/0402-LF
16V A
10% B69 GND PERN12 A69 12ˣ˘˃˲˜ˡʽ˄˅
C336
13 ˣ˘˃˲ˢ˨˧˄ˆ
C304 2 1 PE_TX13
0402_R
B70 PETP13 GND A70
13 ˣ˘˃˲ˢ˨˧ʽ˄ˆ 2 1 X5R PE_TX13*
0.1UF/16V/0402-LF B71 PETN13 GND A71
0402_R 16V
X5R 10% B72 GND PERP13 A72 13ˣ˘˃˲˜ˡ˄ˆ
0.1UF/16V/0402-LF
16V
10% B73 GND PERN13 A73 13ˣ˘˃˲˜ˡʽ˄ˆ
C337
14 ˣ˘˃˲ˢ˨˧˄ˇ
C305 2 1 PE_TX14
0402_R
B74 PETP14 GND A74
14 ˣ˘˃˲ˢ˨˧ʽ˄ˇ 2 1 X5R PE_TX14*
0.1UF/16V/0402-LF B75 PETN14 GND A75
0402_R 16V
X5R 10% B76 GND PERP14 A76 14ˣ˘˃˲˜ˡ˄ˇ
0.1UF/16V/0402-LF
16V
10% B77 GND PERN14 A77 14ˣ˘˃˲˜ˡʽ˄ˇ
C338
15 ˣ˘˃˲ˢ˨˧˄ˈ
C306 2 1 PE_TX15
0402_R
B78 PETP15 GND A78
15 ˣ˘˃˲ˢ˨˧ʽ˄ˈ 2 1 X5R PE_TX15*
0.1UF/16V/0402-LF B79 PETN15 GND A79
0402_R 16V
X5R 10% B80 GND PERP15 A80 15ˣ˘˃˲˜ˡ˄ˈ
0.1UF/16V/0402-LF
16V
PE0_PRSNTX16* 10% B81 PRSNT2* PERN15 A81 15ˣ˘˃˲˜ˡʽ˄ˈ
19 PE0_PRSNTX16*
B82 RSVD GND A82 Title
I11 PCI EXPRESS X16 CONNECTOR

Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SLOT 6
+3.3V_DUAL +3.3V +12V
PCIE2 VCC12 +12V

D CONN_R
3VDUAL 3VDUAL VCC3 VCC12 D
15U
2
PCI_EXPRESS_X1
R249
10K-0402-LF
5%
B1 +12V PRSNT1* A1
0603_R B2 +12V +12V A2
B3 +12V +12V A3 VCC3 +3.3V
B4 GND GND A4
1
23,26,28,30,32 SMB_SDA SMB_SDA B6
B7
SMDAT
GND
TDI
TDO
A6
A7 V0.1 PLACE CAPS NEAR PEX CONNECTORS
B8 +3.3V TMS A8
PE_TRST_1 B9 TRST* +3.3V A9 VCC12 +12V
B10 +3.3V_AUX +3.3V A10
19,26,46 PE_WAKE* PE_WAKE* B11 WAKE* PERST* A11 PE_RESET* PE_RESET* 19,26,46
1
C392 C335
B12 RSVD GND A12 0.1UF/16V/0402-LF X0.1UF-0402-LF
C266 B13 GND X1 CONNECTOR REFCLK+ A13 PE1_REFCLK PE1_REFCLK 20
PE1_OUT 2 1 PE1_TX0 B14 PETP0 REFCLK- A14 PE1_REFCLK*
0603_R 0603_R
20 PE1_OUT 0402_R
C267
PE1_TX0*
PE1_REFCLK* 20 X7R
50V
X7R
50V
20 PE1_OUT* PE1_OUT* 16V

X5R 2 1
0402_R
B15 PETN0 GND A15 10% 10%
0.1UF/16V/0402-LF
2
10%
16V
X5R B16 GND PERP0 A16 PE1_IN PE1_IN 20
0.1UF/16V/0402-LF
20 PE1_PRSNT* PE1_PRSNT* 10% B17 PRSNT2* PERN0 A17 PE1_IN* PE1_IN* 20
B18 GND GND A18
C C
2
I156
VCC3 R248 VCC3 +3.3V
R247 10K-0402-LF
1 2 5%
R0402 5% 0603_R
10K-0402-LF
1
C294 C243
0.1UF/16V/0402-LF X0.1UF-0402-LF
1
0603_R 0603_R
X7R X7R
50V 50V
10% 10%
2
3VDUAL +3.3V_DUAL
SLOT 7
+3.3V_DUAL +3.3V +12V
1
PCIE1
1
VCC12 +12V CE31 C376
3VDUAL 3VDUAL VCC3 VCC12 CONN_R X0.1UF-0402-LF

15U 1000UF/YXG/6.3V/DIP-LF 0603_R
X7R
2
PCI_EXPRESS_X1 2 50V
10%
B B
2
R267
10K-0402-LF
5%
B1 +12V PRSNT1* A1
0603_R B2 +12V +12V A2
B3 +12V +12V A3 VCC3 +3.3V
B4 GND GND A4
1

23,26,28,30,32 SMB_SDA SMB_SDA B6 SMDAT TDI A6
B7 GND TDO A7 V0.1
B8 +3.3V TMS A8
PE_TRST_2 B9 TRST* +3.3V A9
B10 +3.3V_AUX +3.3V A10
19,26,46 PE_WAKE* PE_WAKE* B11 WAKE* PERST* A11 PE_RESET* PE_RESET* 19,26,46
B12 RSVD GND A12
B13 GND X1 CONNECTOR REFCLK+ A13 PE2_REFCLK PE2_REFCLK 20
C247 PE2_TX0
20 PE2_OUT PE2_OUT2 1 B14 PETP0 REFCLK- A14 PE2_REFCLK* PE2_REFCLK* 20
0402_R C248 PE2_TX0*
20 PE2_OUT* PE2_OUT* 16V
X5R 2 1
0402_R
B15 PETN0 GND A15
0.1UF/16V/0402-LF
10% X5R
16V
B16 GND PERP0 A16 PE2_IN PE2_IN 20
0.1UF/16V/0402-LF
20 PE2_PRSNT* PE2_PRSNT* 10% B17 PRSNT2* PERN0 A17 PE2_IN* PE2_IN* 20
B18 GND GND A18
2
I156
VCC3 R201
R188 10K-0402-LF
A 1 2 5% A
R0402 5% 0603_R
10K-0402-LF
1
V0.1 add
Title
PCI EXPRESS X1 CONNECTOR

Custom AN52 V0.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SLOT 5 SLOT 4 (FURTHEST FROM CPU)
PCI1 PCI2
I135 +3.3V_DUAL
I136
PCI124 3VDUAL PCI124 3VDUAL +3.3V_DUAL
D 21,30 PCI_AD[31..0] PCI_AD[31..0] V2.2 21,30 PCI_AD[31..0] PCI_AD[31..0] V2.2
0 5V 32BIT 0 5V 32BIT
ˣ˖˜˲˔˗˃ A58 AD0 3.3VAUX A14 ˣ˖˜˲˔˗˃ A58 AD0 3.3VAUX A14
1 1
ˣ˖˜˲˔˗˄
B58 AD1 TDO B4 ˣ˖˜˲˔˗˄
B58 AD1 TDO B4
2 2
ˣ˖˜˲˔˗˅ A57 AD2 PRSNT1* B9 ˣ˖˜˲˔˗˅ A57 AD2 PRSNT1* B9
3 3
ˣ˖˜˲˔˗ˆ
B56 AD3 PRSNT2* B11 ˣ˖˜˲˔˗ˆ
B56 AD3 PRSNT2* B11
4 4
ˣ˖˜˲˔˗ˇ
A55 AD4 RSVD1 A9 ˣ˖˜˲˔˗ˇ
A55 AD4 RSVD1 A9
5 5
ˣ˖˜˲˔˗ˈ B55 AD5 RSVD2 B10 ˣ˖˜˲˔˗ˈ B55 AD5 RSVD2 B10
6 6
ˣ˖˜˲˔˗ˉ
A54 AD6 RSVD3 A11 ˣ˖˜˲˔˗ˉ
A54 AD6 RSVD3 A11
7 7
ˣ˖˜˲˔˗ˊ B53 AD7 RSVD5 B14 ˣ˖˜˲˔˗ˊ B53 AD7 RSVD5 B14
8 8
ˣ˖˜˲˔˗ˋ
B52 AD8 TCK B2 ˣ˖˜˲˔˗ˋ
B52 AD8 TCK B2
9 9
ˣ˖˜˲˔˗ˌ
A49 AD9 TRST* A1 ˣ˖˜˲˔˗ˌ
A49 AD9 TRST* A1
10 10
ˣ˖˜˲˔˗˄˃ B48 AD10 TMS A3 ˣ˖˜˲˔˗˄˃ B48 AD10 TMS A3
11 11
ˣ˖˜˲˔˗˄˄
A47 AD11 TDI A4 ˣ˖˜˲˔˗˄˄
A47 AD11 TDI A4
12 12
ˣ˖˜˲˔˗˄˅ B47 AD12
ˣ˖˜˲˔˗˄˅ B47 AD12
13 +12V 13 +12V
ˣ˖˜˲˔˗˄ˆ
A46 AD13
ˣ˖˜˲˔˗˄ˆ
A46 AD13
14 -12V 14 -12V
ˣ˖˜˲˔˗˄ˇ
B45 AD14
ˣ˖˜˲˔˗˄ˇ
B45 AD14
15 VCC12 15 VCC12
ˣ˖˜˲˔˗˄ˈ A44 AD15
ˣ˖˜˲˔˗˄ˈ A44 AD15
16 -12V 16 -12V
ˣ˖˜˲˔˗˄ˉ
A32 AD16
ˣ˖˜˲˔˗˄ˉ
A32 AD16
17 17
ˣ˖˜˲˔˗˄ˊ B32 AD17 +12V A2 ˣ˖˜˲˔˗˄ˊ B32 AD17 +12V A2
18 18
ˣ˖˜˲˔˗˄ˋ
A31 AD18 -12V B1 ˣ˖˜˲˔˗˄ˋ
A31 AD18 -12V B1
19 19
ˣ˖˜˲˔˗˄ˌ
B30 AD19
ˣ˖˜˲˔˗˄ˌ
B30 AD19
20 20
ˣ˖˜˲˔˗˅˃ A29 AD20 +5V B5 ˣ˖˜˲˔˗˅˃ A29 AD20 +5V B5
21 21
ˣ˖˜˲˔˗˅˄
B29 AD21 +5V B6 ˣ˖˜˲˔˗˅˄
B29 AD21 +5V B6
22 22
ˣ˖˜˲˔˗˅˅ A28 AD22 +5V A5 ˣ˖˜˲˔˗˅˅ A28 AD22 +5V A5
C 23 23
ˣ˖˜˲˔˗˅ˆ
B27 AD23 +5V A8 ˣ˖˜˲˔˗˅ˆ
B27 AD23 +5V A8
24 24
ˣ˖˜˲˔˗˅ˇ
A25 AD24 +5V A10 ˣ˖˜˲˔˗˅ˇ
A25 AD24 +5V A10
25 25
ˣ˖˜˲˔˗˅ˈ B24 AD25 +5V B61 ˣ˖˜˲˔˗˅ˈ B24 AD25 +5V B61
26 26
ˣ˖˜˲˔˗˅ˉ
A23 AD26 +5V A16 ˣ˖˜˲˔˗˅ˉ
A23 AD26 +5V A16
27 27
ˣ˖˜˲˔˗˅ˊ B23 AD27 +5V B62 ˣ˖˜˲˔˗˅ˊ B23 AD27 +5V B62
28 28
ˣ˖˜˲˔˗˅ˋ
A22 AD28 +5V A59 ˣ˖˜˲˔˗˅ˋ
A22 AD28 +5V A59
29 29
ˣ˖˜˲˔˗˅ˌ
B21 AD29 +5V B59 ˣ˖˜˲˔˗˅ˌ
B21 AD29 +5V B59
30 VCC5 +5V 30 VCC5 +5V
ˣ˖˜˲˔˗ˆ˃ A20 AD30 +5V A61 ˣ˖˜˲˔˗ˆ˃ A20 AD30 +5V A61
31 31
ˣ˖˜˲˔˗ˆ˄
B20 AD31 +5V B19 ˣ˖˜˲˔˗ˆ˄
B20 AD31 +5V B19
26 25
ˣ˖˜˲˔˗˅ˉ A26 IDSEL +5V A62 ˣ˖˜˲˔˗˅ˈ A26 IDSEL +5V A62
21,30 PCI_C/BE*[3..0] PCI_C/BE*[3..0] 21,30 PCI_C/BE*[3..0] PCI_C/BE*[3..0]
0 0
ˣ˖˜˲˖˂˕˘ʽ˃
A52 CBE0* +3.3V A21 ˣ˖˜˲˖˂˕˘ʽ˃
A52 CBE0* +3.3V A21
1 1
ˣ˖˜˲˖˂˕˘ʽ˄ B44 CBE1* +3.3V A27 ˣ˖˜˲˖˂˕˘ʽ˄ B44 CBE1* +3.3V A27
2 2
ˣ˖˜˲˖˂˕˘ʽ˅
B33 CBE2* +3.3V A33 ˣ˖˜˲˖˂˕˘ʽ˅
B33 CBE2* +3.3V A33
3 3
ˣ˖˜˲˖˂˕˘ʽˆ B26 CBE3* +3.3V A39 ˣ˖˜˲˖˂˕˘ʽˆ B26 CBE3* +3.3V A39
+3.3V A45 +3.3V A45
21,30,31 PCI_INTY* PCI_INTY* A6 INTA* +3.3V B43 21,30,31 PCI_INTX* PCI_INTX* A6 INTA* +3.3V B43
21,30,31 PCI_INTZ* PCI_INTZ* B7 INTB* +3.3V B41 21,30,31 PCI_INTY* PCI_INTY* B7 INTB* +3.3V B41
21,30,31 PCI_INTW* PCI_INTW* A7 INTC* +3.3V B36 21,30,31 PCI_INTZ* PCI_INTZ* A7 INTC* +3.3V B36
21,30,31 PCI_INTX* PCI_INTX* B8 INTD* +3.3V B31 21,30,31 PCI_INTW* PCI_INTW* B8 INTD* +3.3V B31
PCI_REQ*[4..3] B25 VCC3 +3.3V PCI_REQ*[4..3] B25 VCC3 +3.3V
21,31 PCI_REQ*[4..3] 4 +3.3V 21,31 PCI_REQ*[4..3] 3 +3.3V
21 PCI_GNT*[4..3] PCI_GNT*[4..3] ˣ˖˜˲˥˘ˤʽˇ
B18 REQ* +3.3V B54 21 PCI_GNT*[4..3] PCI_GNT*[4..3] ˣ˖˜˲˥˘ˤʽˆ
B18 REQ* +3.3V B54
4 3
B ˣ˖˜˲˚ˡ˧ʽˇ A17 GNT* +3.3V A53 ˣ˖˜˲˚ˡ˧ʽˆ A17 GNT* +3.3V A53
21,30,31 PCI_PME* PCI_PME* A19 PME* 21,30,31 PCI_PME* PCI_PME* A19 PME*
21,30,31 PCI_FRAME* PCI_FRAME* A34 FRAME* GND A12 21,30,31 PCI_FRAME* PCI_FRAME* A34 FRAME* GND A12
21,30,31 PCI_TRDY* PCI_TRDY* A36 TRDY* GND A13 21,30,31 PCI_TRDY* PCI_TRDY* A36 TRDY* GND A13
21,30,31 PCI_STOP* PCI_STOP* A38 STOP* GND A18 21,30,31 PCI_STOP* PCI_STOP* A38 STOP* GND A18
21,30,31 PCI_IRDY* PCI_IRDY* B35 IRDY* GND A24 21,30,31 PCI_IRDY* PCI_IRDY* B35 IRDY* GND A24
21,30,31 PCI_DEVSEL* PCI_DEVSEL* B37 DEVSEL* GND A30 21,30,31 PCI_DEVSEL* PCI_DEVSEL* B37 DEVSEL* GND A30
30,31 PCI_LOCK* PCI_LOCK* B39 LOCK* GND A35 30,31 PCI_LOCK* PCI_LOCK* B39 LOCK* GND A35
21,30,31 PCI_PERR* PCI_PERR* B40 PERR* GND A37 21,30,31 PCI_PERR* PCI_PERR* B40 PERR* GND A37
21,30,31 PCI_SERR* PCI_SERR* B42 SERR* GND A42 21,30,31 PCI_SERR* PCI_SERR* B42 SERR* GND A42
21,30 PCI_PAR PCI_PAR A43 PAR GND A48 21,30 PCI_PAR PCI_PAR A43 PAR GND A48
23,26,27,30,32 SMB_SDA SMB_SDA A41 SBO* GND A56 23,26,27,30,32 SMB_SDA SMB_SDA A41 SBO* GND A56
21 PCI_RST_SLOT1* PCI_RST_SLOT1* A15 RESET* GND B3 21 PCI_RST_SLOT2* PCI_RST_SLOT2* A15 RESET* GND B3
23,26,27,30,32 SMB_SCL SMB_SCL A40 SDONE GND B12 23,26,27,30,32 SMB_SCL SMB_SCL A40 SDONE GND B12
GND B13 GND B13
30,31 PCI_REQ64A* PCI_REQ64A* A60 REQ64* GND B15 31 PCI_REQ64B* PCI_REQ64B* A60 REQ64* GND B15
30,31 PCI_ACK64* PCI_ACK64* B60 ACK64* GND B17 30,31 PCI_ACK64* PCI_ACK64* B60 ACK64* GND B17
21 PCI_CLKSLOT1 PCI_CLKSLOT1 B16 CLOCK GND B22 21 PCI_CLKSLOT2 PCI_CLKSLOT2 B16 CLOCK GND B22
GND B28 GND B28
KEY<A50> GND B34 KEY<A50> GND B34
KEY<A51> GND B38 KEY<A51> GND B38
KEY<B50> GND B46 KEY<B50> GND B46
KEY<B51> GND B49 KEY<B51> GND B49
A GND B57 GND B57
CONN_R CONN_R
Title
PCI CONNECTOR 1-2

Custom AN52 V0.1
VCC3 +3.3V
PCI_SERR* RN31D 5 4 10K-8P4R-LF

21,28,30 PCI_SERR*
PCI3
I135 +3.3V_DUAL
PCI124 3VDUAL PCI_DEVSEL* RN27A 8 1 10K-8P4R-LF
21,28,30 PCI_DEVSEL*
21,28 PCI_AD[31..0] PCI_AD[31..0] V2.2
0 ˣ˖˜˲˔˗˃ A58 AD0 5V 32BIT 3.3VAUX A14
1 ˣ˖˜˲˔˗˄
B58 AD1 TDO B4
2 RN27C
ˣ˖˜˲˔˗˅ A57 AD2 PRSNT1* B9 21,28,30 PCI_IRDY* PCI_IRDY* 6 3 10K-8P4R-LF
3 ˣ˖˜˲˔˗ˆ
B56 AD3 PRSNT2* B11
4 ˣ˖˜˲˔˗ˇ
A55 AD4 RSVD1 A9
5 ˣ˖˜˲˔˗ˈ B55 AD5 RSVD2 B10
6 RN31B 10K-8P4R-LF
ˣ˖˜˲˔˗ˉ
A54 AD6 RSVD3 A11 28,30 PCI_LOCK* PCI_LOCK* 7 2
7 ˣ˖˜˲˔˗ˊ B53 AD7 RSVD5 B14
8 ˣ˖˜˲˔˗ˋ
B52 AD8 TCK B2
9 ˣ˖˜˲˔˗ˌ
A49 AD9 TRST* A1
10 RN31C 10K-8P4R-LF
ˣ˖˜˲˔˗˄˃ B48 AD10 TMS A3 21,28,30 PCI_PERR* PCI_PERR* 6 3
11 ˣ˖˜˲˔˗˄˄
A47 AD11 TDI A4
12 ˣ˖˜˲˔˗˄˅ B47 AD12
13 +12V
ˣ˖˜˲˔˗˄ˆ
A46 AD13
14 -12V
ˣ˖˜˲˔˗˄ˇ
B45 AD14
15 VCC12
ˣ˖˜˲˔˗˄ˈ A44 AD15
16 -12V RN27D 10K-8P4R-LF
ˣ˖˜˲˔˗˄ˉ
A32 AD16 21,28,30 PCI_FRAME* PCI_FRAME* 5 4
17 ˣ˖˜˲˔˗˄ˊ B32 AD17 +12V A2
18 ˣ˖˜˲˔˗˄ˋ
A31 AD18 -12V B1
19 ˣ˖˜˲˔˗˄ˌ
B30 AD19
20 RN27B 10K-8P4R-LF
ˣ˖˜˲˔˗˅˃ A29 AD20 +5V B5 21,28,30 PCI_TRDY* PCI_TRDY* 7 2
21 ˣ˖˜˲˔˗˅˄
B29 AD21 +5V B6
22 ˣ˖˜˲˔˗˅˅ A28 AD22 +5V A5
23 ˣ˖˜˲˔˗˅ˆ
B27 AD23 +5V A8
24 RN31A 10K-8P4R-LF
ˣ˖˜˲˔˗˅ˇ
A25 AD24 +5V A10 21,28,30 PCI_STOP* PCI_STOP* 8 1
25 ˣ˖˜˲˔˗˅ˈ B24 AD25 +5V B61
26 ˣ˖˜˲˔˗˅ˉ
A23 AD26 +5V A16
27 ˣ˖˜˲˔˗˅ˊ B23 AD27 +5V B62
28 RN32A 10K-8P4R-LF
ˣ˖˜˲˔˗˅ˋ
A22 AD28 +5V A59 28,30 PCI_ACK64* PCI_ACK64* 8 1
29 ˣ˖˜˲˔˗˅ˌ
B21 AD29 +5V B59
30 VCC5 +5V
ˣ˖˜˲˔˗ˆ˃ A20 AD30 +5V A61
31 ˣ˖˜˲˔˗ˆ˄
B20 AD31 +5V B19
23
PCI_AD23 A26 A62 PCI_REQ64A* RN32B 7 2 10K-8P4R-LF
IDSEL +5V 28,30 PCI_REQ64A*
21,28 PCI_C/BE*[3..0] PCI_C/BE*[3..0]
0 ˣ˖˜˲˖˂˕˘ʽ˃
A52 CBE0* +3.3V A21
1 ˣ˖˜˲˖˂˕˘ʽ˄ B44 CBE1* +3.3V A27
2 V0.1 add RN32C 10K-8P4R-LF
ˣ˖˜˲˖˂˕˘ʽ˅
B33 CBE2* +3.3V A33 28 PCI_REQ64B* PCI_REQ64B* 6 3
3 ˣ˖˜˲˖˂˕˘ʽˆ B26 CBE3* +3.3V A39
+3.3V A45
21,28,31 PCI_INTZ* PCI_INTZ* A6 INTA* +3.3V B43
21,28,31 PCI_INTW* PCI_INTW* B7 INTB* +3.3V B41
PCI_INTX* A7 B36 3VDUAL
21,28,31 PCI_INTX* INTC* +3.3V
21,28,31 PCI_INTY* PCI_INTY* B8 INTD* +3.3V B31
PCI_REQ*[4..0] 1 B25 VCC3 +3.3V
21,28,31 PCI_REQ*[4..0] +3.3V R394
21,28 PCI_GNT*[4..0] PCI_GNT*[4..0] PCI_REQ*1 B18 REQ* +3.3V B54 21,28,30 PCI_PME* PCI_PME* 1 2
1
PCI_GNT*1 A17 GNT* +3.3V A53 R0402 5%
10K-0402-LF
21,28,31 PCI_PME* PCI_PME* A19 PME*
21,28,31 PCI_FRAME* PCI_FRAME* A34 FRAME* GND A12
PCI_TRDY* A36 A13 VCC3 +3.3V
21,28,31 PCI_TRDY* TRDY* GND
21,28,31 PCI_STOP* PCI_STOP* A38 STOP* GND A18
21,28,31 PCI_IRDY* PCI_IRDY* B35 IRDY* GND A24
21,28,31 PCI_DEVSEL* PCI_DEVSEL* B37 DEVSEL* GND A30 21,28 PCI_REQ*[4..0] PCI_REQ*[4..0] BR13
PCI_LOCK* B39 A35 0ˣ˖˜˲˥˘ˤʽ˃ 1 2
28,31 PCI_LOCK* LOCK* GND
21,28,31 PCI_PERR* PCI_PERR* B40 PERR* GND A37 0402_R 5%
8.25K-1%-LF
21,28,31 PCI_SERR* PCI_SERR* B42 SERR* GND A42
21,28 PCI_PAR PCI_PAR A43 PAR GND A48 R401
SMB_SDA A41 A56 1ˣ˖˜˲˥˘ˤʽ˄ 1 2
23,26,27,28,32 SMB_SDA SBO* GND
21 PCI_RST_SLOT3* PCI_RST_SLOT3* A15 RESET* GND B3 0402_R 5%
8.25K-1%-LF
23,26,27,28,32 SMB_SCL SMB_SCL A40 SDONE GND B12
GND B13 BR1
PCI_REQ64A* A60 B15 2ˣ˖˜˲˥˘ˤʽ˅ 1 2
28,31 PCI_REQ64A* REQ64* GND
28,31 PCI_ACK64* PCI_ACK64* B60 ACK64* GND B17 0402_R 5%
PCI_CLKSLOT3 8.25K-1%-LF
21 PCI_CLKSLOT3 B16 CLOCK GND B22
GND B28 R415
B34 3 ˣ˖˜˲˥˘ˤʽˆ 1 2
KEY<A50> GND
KEY<A51> GND B38 0402_R 5%
8.25K-1%-LF
KEY<B50> GND B46
KEY<B51> GND B49 R391
B57 4ˣ˖˜˲˥˘ˤʽˇ 1 2
GND
0402_R 5%
CONN_R 8.25K-1%-LF
RN34A
21,28,30 PCI_INTW* PCI_INTW* 8 1

10K-8P4R-LF
RN34D
21,28,30 PCI_INTX* PCI_INTX* 5 4

10K-8P4R-LF
RN34B
3VDUAL VCC12 VCC5 -12V VCC3 PCI_INTY* 7 2
21,28,30 PCI_INTY*
10K-8P4R-LF
1
RN34C
C434 C433 C431 C439 C432 PCI_INTZ* 6 3
21,28,30 PCI_INTZ*
1UF/16V-LF 1UF/16V-LF 1UF/16V-LF 1UF/16V-LF 1UF/16V-LF 10K-8P4R-LF
C0603 C0603 C0603 C0603 C0603
16V 16V 16V 16V 16V
2
10% 10% 10% 10% 10%

X5R X5R X5R X5R X5R
Title
PCI TERMINATION/DECOUPLING
Custom AN52 V0.1
8 7 6 5 4 3 2 1
FB11
U14 1 2 30 OHM/100MHz/3A/0603-LF V2P5_DUAL_LAN
QFN64_R FB12
1
C256 C260 C257 C258 CT64
AVDD 21 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 4.7UF/0805Y/10V-LF 1 2 30 OHM/100MHz/3A/0603-LF V1P8_DUAL_LAN
20 RGMII_TXD[3..0] RGMII_TXD[3..0] 88E1116/88E3018 AVDD 22
3 ˥˚ˠ˜˜˲˧˫˗ˆ 62 TXD3 AVDD 27 0402_R 0402_R 0402_R
X5R
0402_R 0603_R
2 ˥˚ˠ˜˜˲˧˫˗˅ Gbit LAN PHY X5R

10V
X5R
10V 10V
X5R
10V
X5R
6.3V
D 61 TXD2 NC 28 2 1 10% 10% 10% 10% 10%
1 ˥˚ˠ˜˜˲˧˫˗˄ R484 x0-0402-LF 0.1UF/16V/0402-LF 0.01UF-0402-LF
2
59 TXD1 AVDD 29 D
0 ˥˚ˠ˜˜˲˧˫˗˃ 58 TXD0
AVDDC 34
20 RGMII_TXCTL RGMII_TXCTL 63 TX_CTRL AVDDC 37
20 RGMII_TXCLK RGMII_TXCLK 60 TX_CLK
AVDDR 14
PLACE NEAR PHY
1
C261 C264 C269 C263 C268 CT65
20 RGMII_RXD[3..0] RGMII_RXD[3..0] AVDDR 15 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 0.01UF-0402-LF 4.7UF/0805Y/10V-LF
RN26-4
3 ˥˚ˠ˜˜˲˥˫˗ˆ 4 5 0-8P4R-LF RGMIIRXD3_R 55 RXD3 3VDUAL
3VDUAL +3.3V_DUAL RN26-3
2 ˥˚ˠ˜˜˲˥˫˗˅ 3 6 0-8P4R-LF RGMIIRXD2_R 54 RXD2 AVDDX 16 X:3018 0402_R
X5R
0402_R
X5R
0402_R
X5R
0402_R
X5R
0402_R
X5R
0603_R
X5R
RN26-2
1 ˥˚ˠ˜˜˲˥˫˗˄ 2 7 0-8P4R-LF RGMIIRXD1_R 51 RXD1 R224 x0-LF O:1116 10V
10%
10V
10%
10V
10%
10V
10%
10V
10%
6.3V
10%
2
RN26-1
0 ˥˚ˠ˜˜˲˥˫˗˃ 0-8P4R-LF R485 x0-LF 0.1UF/16V/0402-LF 0.01UF-0402-LF
2
1 8 RGMIIRXD0_R 50 RXD0 DVDD 5 LAN_DVDD
V0.1 1.5K -> 4.7K R243 0402_R
DVDD 13
1
4.7K-LF R253 CT67 C270 C289 C278
5% 20 RGMII_RXCTL RGMII_RXCTL 1 20-0402-LFRGMII_RXCTL_R 49 RX_CTRL DVDD 40 4.7UF/0805Y/10V-LF 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
0402_R
20 RGMII_RXCLK RGMII_RXCLK 1 2 RGMII_RXCLK_R 53 RX_CLK DVDD 47
R254 0-0402-LF 0603_R 0402_R 0402_R
X5R X5R X5R
0402_R 6.3V 0.1UF/16V/0402-LF 10V 10V
VDDO 7 10% 10% 10%
3VDUAL
1
2
20 RGMII_MDIO RGMII_MDIO 45 MDIO VDDO 46 +3.3V_DUAL
20 RGMII_MDC RGMII_MDC 48 MDC

VDDOR 52
x25.000MHZ
Y2
TP_RGMIITCK
42 TCK VDDOR 56
2HC49_R 1 TP_RGMIITDI
43 TDI
1
50PPM
C287 C288 C290 C246
I126 18PF
˨ˡˡ˔ˠ˘˗˲ˇ˃˲˖˔ˣ˲˜˄˅ˊ˲˔ ˨ˡˡ˔ˠ˘˗˲ˇ˃˲˖˔ˣ˲˜˄˄ˌ˲˔ TP_RGMIITDO
44 TDO DIS_REG1.2V12
1
C272 C275 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF

R232 TP_RGMIITMS
41 TMS CTRL1.8V 17 TP_CTRL1.8V
C x18PF x18PF TP1 0402_R 0402_R C

1 2 11
RGMIITRST
TRST* X5R
10V
0402_R
X5R X5R
10V
0402_R
X5R
KEEP STUBS <250 MILS C0G
EMPTY
0603_R 0603_R
C0G
0402_R 5% 10%
10V
10% 10%
10V
10%
50V 50V 4.7K-0402-LF 0.1UF/16V/0402-LF
2
5% 5%
TP2 TP_TSTPT 32 TSTPT
Close to PHY
2
R231
RGMII_25MHZ 1 2 LAN_XTAL1 38 XTAL_IN
20 RGMII_25MHZ
0603_R 5%
MDI0+ 31 GBIT_MDI0+
0-0402-LF LAN_XTAL2 MDI0+ 39
39 XTAL_OUT MDI0- 30 GBIT_MDI0-
MDI0- 39
RGMII_RESET* 10 RESET* MDI1+ 26 GBIT_MDI1+
20,23 RGMII_RESET* MDI1+ 39
MDI1- 25 GBIT_MDI1-
MDI1- 39
2
RGMII_VREF 57 VREF
R233 MDI2+ 24 GBIT_MDI2+
4.7K-0402-LF MDI2+ 39
MDI2- 23 GBIT_MDI2-
5% MDI2- 39
0402_R
3VDUAL +3.3V_DUAL 4 COMA* MDI3+ 20 GBIT_MDI3+

CONFIG3 3
MDI3+ 39
CONFIG3 MDI3- 19 GBIT_MDI3-
MDI3- 39
2
R164-> 2K : 3018 4.87K :1116

1
2 CONFIG2 R225
2
RGMII_RSET
R255 1 CONFIG1 RSET 33 1 2
1K-1%-LF R218 R216 R214 R212
1%
64 CONFIG0 0402_R 1%
2.0K-1%-LF x49.9-0402-1%-LF x49.9-0402-1%-LF 49.9-0402-1%-LF 49.9-0402-1%-LF

0402_R NC 18 1 2
2
1% 1% 1% 1%
R210 0-0402-LF 0402_R 0402_R 0402_R 0402_R
2
B 65 GND_PAD R195 R196 R206 R207 B
12
HSDAC+ 36 TP_HSDAC+ 0-0402-LF 0-0402-LF R219 R217 R215 R213

1
5% 5% 5% 5%
C292 GND:3018 0-0402-LF 0-0402-LF x49.9-0402-1%-LF x49.9-0402-1%-LF 49.9-0402-1%-LF 49.9-0402-1%-LF
1
R263
0.1UF/16V/0402-LF HSDAC- 35 TP_HSDAC- 0402_R 0402_R 0402_R 0402_R
1% 1% 1% 1%
1K-1%-LF
1%
X :1116 0402_R 0402_R 0402_R 0402_R
0402_R
0402_R X5R
10V
1
10% LED0 6
2
1
LED1 8 ˨ˡˡ˔ˠ˘˗˲ˇ˃˲˖˔ˣ˲˜ˈˈ˲˔ ˨ˡˡ˔ˠ˘˗˲ˇ˃˲˖˔ˣ˲˜ˈˆ˲˔ ˨ˡˡ˔ˠ˘˗˲ˇ˃˲˖˔ˣ˲˜ˈ˄˲˔ ˨ˡˡ˔ˠ˘˗˲ˇ˃˲˖˔ˣ˲˜ˇˇ˲˔
1
Reserved for E3018 MII C250 C242 C249 C259
1
LED2 9 x0.01UF-0402-LF x0.01UF-0402-LF 0.01UF-0402-LF 0.01UF-0402-LF
3VDUAL +3.3V_DUAL I147 0402_R 0402_R 0402_R 0402_R

X5R X5R X5R X5R
10V 10V 10V 10V
10% 10% 10% 10%
2
LAN_LED0
2
R237 LAN_LED1
10K-0402-LF
5%
0402_R
2
2
EMPTY EMPTY
R241 R239 R187 R246 R245 PLACE RC NETWORKS
x0-0402-LF 0-0402-LFx0-0402-LF x0-0402-LF CLOSE TO PHY
1
RGMII_COMA* x0-0402-LF
20 RGMII_COMA* 5% 5% 5% 5% 5%
0402_R 0402_R 0402_R 0402_R 0402_R
MII_RX_ER 20
MII_CRS 20
MII_COL 20
1
3VDUAL
LINK_1000 39
A
3VDUAL A
LINK_100 39
LAN_LED2 39
For E3018 MII to copper, R?
+3.3V_DUAL R2571 2 RGMII_INTR*
mount and R176 don't. 0402_R 5%
For E1116 and E3016, R176 x0-0402-LF
3018 HW DEFALT CONFIG mount and R178 don't.
CONFIG 0-1 PHY ADDRESS = 00001 Pin17 CTRL18/25ΚFloat ->18/25 regulator isn't used
CONFIG 2 ENABLE AUTO-CROSSOVER If 1116 BIOS need PROGRAM LED TO MODE 3

Pin12 DIS_REG12->GNDΚdisable VDDOΚenable
Title
CONFIG 3 COPPER MII
COMA MUST BE PROGRAMMED BEFORE RESET 10/100 LAN PHY 88E3018
Custom AN52 V0.1
8 7 6 5 4 3 2 1
5 4 3 2 1
VDD33_LAN1
VDD33_LAN1
3VDUAL VDD33_LAN1 Place near U12 VDD33 Pins

FB7
1 2
R474 R475
1
30 OHM/100MHz/3A/0603-LFCT54 CT52 CT53 4.7K-LF 4.7K-LF
C199 C203 C213 C209
10UF/10V/0805-LF 10UF/10V/0805-LF 0.1UF/16V-LF 0.1UF/16V-LF
E
SOT23 SOT23
10UF/10V/0805-LF 0.1UF/16V-LF 0.1UF/16V-LF
LAN1_CTRL18 Q29 LAN1_CTRL12 Q30
2
B B
R476 0-LF AVDD18_LAN1 VDD18_LAN1 R477 0-LF BCP69/1A/20V-LF VDD12_LAN1
D BCP69/1A/20V-LF D
C
V0.2 R144 0-0805-LF
1
CT51 V0.2 CT50
C218 C217 C186 C187 C195 C198 C202 C207 C212
10UF/10V/0805-LF 0.1UF/16V-LF 10UF/10V/0805-LF
0.1UF/16V-LF 0.1UF/16V-LF 0.1UF/16V-LF 0.1UF/16V-LF
0.1UF/16V-LF 0.1UF/16V-LF 0.1UF/16V-LF 0.1UF/16V-LF
2
Place near U12 VDD15 Pins
VCC3 VCC3 U11

USB1B
17 LAN1_TRD0_P L2
MDIP[0] TRD1+ (B)
1
VDD12_LAN1 47 18 LAN1_TRD0_N L3
C205 VMAIN_AVAL MDIN[0] TRD1- (B)
2 20 LAN1_TRD1_P L4
0.1UF/16V-LF VDD(1) MDIP[1] LAN1_TRD1_N TRD2+ (B)
7 VDD(2) MDIN[1] 21 L5 TRD2- (B)
2
13 VDD(3)
3VDUAL AVDD33_LAN1 33 26 LAN1_TRD2_P L6
FB5 VDD(4) MDIP[2] LAN1_TRD2_N TRD3+ (B)
39 VDD(5) MDIN[2] 27 L7 TRD3- (B)
1 2 44 VDD(6)
48 30 LAN1_TRD3_P L8
VDD(7) MDIP[3] TRD4+ (B)
1
30 OHM/100MHz/3A/0603-LF VDD33_LAN1 58 31 LAN1_TRD3_N L9

C200 VDD(8) MDIN[3] TRD4- (B)
2
2
2
2
2
2
2
2
1 VDDO_TTL(1) H1 H1
0.1UF/16V-LF 40 R125 R126 R123 R124 R121 R122 R119 R120 H2
C AVDD33_LAN1 VDDO_TTL(2) H2 C
2
45 VDDO_TTL(3) H7 H7 H2 H8
61 VDDO_TTL(4) H8 H8
59 LAN1_ACT# 49.9-1%-LF 49.9-1%-LF 49.9-1%-LF 49.9-1%-LF L11 L2
LED_LNK/ACTn L1
8 60 LAN1_LINK100# 49.9-1%-LF 49.9-1%-LF 49.9-1%-LF 49.9-1%-LF LAN1_ACT# R141 150-1%-LF L11 L12
VDDO_TTL_MAIN LED_LINK10/100n LED1- L3
VDD18_LAN1 R138 150-1%-LF L4
11
1
11
1
11
1
11
1
12 VAUX_AVLBL LED_LINKn 63 VDD33_LAN1 L12 LED1+ L5
62 LAN1_LINK1000# L6
LED_LINK1000n L7
19 C182 C181 C180 C177 V0.2 LAN1_LINK100# R128 0-LF L14 L8
AVDDL(1) LED2- L9
22 0.1UF/16V-LF 0.1UF/16V-LF 0.1UF/16V-LF 0.1UF/16V-LF LAN1_LINK1000# R131 0-LF L13 L13
AVDDL(2) LED2+
1
23 L14 L10
C194 AVDDL(3) R139 0-LF
2
28 AVDDL(4) VDD18_LAN1 L1 TRDCT_VDD H1 H7
0603 C185 L10 TRDCT_CAP
1
1UF/16V-LF 0.1UF/16V-LF 32 C208
AVDDL(5)
1
LAN1_CTRL18 C206 0.01UF-0402-LF
2
51 AVDDL(6) CTRL18 4
USBGND
52 3 LAN1_CTRL12 0402_R C191 RJ45/USB/Gb-LF
AVDDL(7) CTRL12 x0.1UF/16V-LF
X5R
10V COU22P-RJ45XLED
57 AVDDL(8) NC R130 4.87K-1%-LF
10%
0.01UF-0402-LF
2
64 VDD25 RSET 16
2
24 HSDACP
25 HSDACN
3VDUAL
V0.2 R136 1K-1%-LF
29 TSTPT NC VDD33_LAN1
38 GBE_SCL V0.2
VPD_CLK GBE_SDA
VPD_DATA 41
R134 15K-1%-LF 10 LOM_DISABLEn
20 PE3_REFCLK PE3_REFCLK 55 LAN1_LINK100# R478 220-LF
REFCLKP LAN1_LINK1000# R479 220-LF
20 PE3_REFCLK* PE3_REFCLK* 56 REFCLKN
SPI_CS 36
37 3VDUAL
B SPI_CLK B
20 PE3_IN PE3_IN 1 2 49 TX_P Output SPI_DI 35
20 PE3_IN* PE3_IN* C3421 20.1UF/16V/0402-LF 50 TX_N SPI_DO 34
C341 0.1UF/16V/0402-LF
1
C211 0.1UF/16V/0402-LF C227 V0.1 Does AN52 Use??
V0.2 20 PE3_OUT* PE3_OUT* 2 1 PE3_TX0*
PE3_TX0
53 RX_N Intput 0.1UF/16V-LF R156 R155 R154
20 PE3_OUT PE3_OUT 2 1 54 RX_P
C210 0.1UF/16V/0402-LF x4.7K 4.7K-LF 4.7K-LF
2
19,26,27 PE_RESET* PE_RESET* 5 U13
PERSTn SOP8
SWITCH_VCC 11 1 A0 (I) VCC (P) 8
3VDUAL 9 2 7
SWITCH_VAUX A1 (I) WP (B) GBE_SCL
6 WAKEn 3 A3 (I) SCLK (O) 6
4 5 GBE_SDA
GND (P) SDATA (B)
2
R137 43 AT24C08-LF 8Kb

SMDATA SOP8-1_27 R145
10K-0402-LF 42
5% SMCLK
0603_R 0-LF
65 EPAD XTALO 14
R133 10M-LF
1
19,26,27 PE_WAKE* PE_WAKE* 46 TESTMODE XTALI 15

1 2
88E8056-LF Y1 25.000MHZ
150PPM 2
HC49_R
18PF I484
1
C192 C197
27PF/NPO/50V-LF 27PF/NPO/50V-LF
0402_R 0402_R
C0G C0G
50V 50V
5% 5%
A A
2
CK_PE_LAN1_P
CK_PE_LAN1_N
PCIE_OB_RST#
HSO_P3 Title
LAN1_PME# HSO_N3
HSI_P3
GbE PCIE LAN 88E8056
HSI_N3
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
VCC5A NORMAL VOLTAGE = 4.7V (2%) GND GND_AUDIO priority of first priority of first close
VCC5 VCC5A VCC3 FB1 AUDIO1B AUDIO1A
U22 close to PIN25,38 to PIN1,9
FB29 L0603 1 5 FB31
VIN VOUT
pin 47
x30OHM/3A/40mOHM/0805 R434 30 OHM/100MHz/3A/0603-LFCT103 C427 C396 CT102 CT92 C404 C410
LF
C437 3 3.01K-1%-LFL0603 0805 0603x1UF 06031UF/16V-LF 0805 0805 0603 06030.1UF/16V/0402-LF
50 mils gap
EN
1%
VCC5SB 06031UF/16V-LF Y5V
10UF/10V/0805-LF Y5V Y5V
10UF/10V/0805-LF x0.1UF Y5V
Y5V 16V 16V 10V 16V
L0603 16V
pin 12 ALC88X CODEC GND_EMI_AUDIO
FB30 2 4 4.7UF/0805Y/10V-LF
GND ADJ
D 30 OHM/100MHz/3A/0603-LF RT9179/1%/300mA-LF GND D
R429 C435 V0.1 Replace EC53 with C749 ,C756 100UF ->10UF
LF
For RT9167 R1:NC; R2:NC; C1:0.1uF 0603x0.1UF GND_AUDIO For PCB Layout copper
1%
For RT9179 R1:3.01K_1%; R2:1K_1%; C1:NC 1K-1%-LF V1.0 RT9167ሽ୲૞ՂΙRT9179լ‫ױ‬Ղ area and placement
RT9179ૉՂሽ୲ΔᄎࠌSNRΕTHNDЀ
23 HDA_RST* HDA_RST* ᧢ᜊ FRONT_OUT_L
+ +
23 HDA_SYNC HDA_SYNC ALC880-LF,REV:H CE36 100UF/25V/DIP-LF FB11
23 HDA_SDOUT HDA_SDOUT FRONT_OUT_R
HDA_SDIN_0
3139-00-0021 CE35 100UF/25V/DIP-LF
23 HDA_SDIN_0
06030603060306030805080508050805
ALC882M-LF,REV:B1 LINE_IN_L
R396 LF 10-LF CT85 10UF/10V/0805-LF
23 HDA_BITCLK HDA_BITCLK
3139-00-0020 LINE_IN_R FRONT PANEL AUDIO VCC3
C406 FP_OUT_L CE34 100UF/25V/DIP-LF CT88 10UF/10V/0805-LF D14
ALC885M-LF,REV:B2
+ +
0603x22PF 25V MIC1_L K2 R386 LF 4.7K-0402-LF
V0.1 NPO FP_OUT_R CE33 100UF/25V/DIP-LF U20 3139-00-00XX CT86 10UF/10V/0805-LF VREF_MIC2 A
50V 25V 11 35 MIC1_R K1 R377 LF 4.7K-0402-LF R467
LF
ACZ_RST# (I) FRONT_OUT_L (B)
060306030603
CD_L C389 1UF/16V-LF 10 36 CT89 10UF/10V/0805-LF FP-AUDIO1
Y5V 16V ACZ_SYNC (I) FRONT_OUT_R (B) CT95 CENTER_OUT
1UF/16V-LF
SOT23
BAT54A-LF 4.7K-0402-LF
close to MCP55P CD_REF C395 1UF/16V-LF
5 ACZ_SDOUT (I) LINE_IN_L (B) 23
16V Y5V FP_AUDIO_PRESENCE*
8 ACZ_SDIN (O) LINE_IN_R (B) 24 23 FP_AUDIO_PRESENCE* 4 AVCC
Y5V 16V 6 21 CT96 LFE_OUT
1UF/16V-LF D-SOT23-K1AK2 R466 0-0402-LF
CD_R C394 1UF/16V-LF ACZ_BIT_CLK (I) MIC1_L (B) 16V Y5V MIC2_L RN28-1 8 30V
14 FP_OUT_L (B) MIC1_R (B) 22 1 75-8P4R-LF 1 MIC2_L
Y5V 16V 15 43 CT94 REARSURR_OUT_L
1UF/16V-LF MIC2_R RN28-2 7 2 75-8P4R-LF 3
FP_OUT_R (B) CENTER_OUT (O) MIC2_R 1 2
MIC2_L CT90 06030603 1UF/16V-LF 18 44 16V Y5V
16V Y5V CD_L (I) LFE_OUT (O) CT93 REARSURR_OUT_R
1UF/16V-LF FP_OUT_R RN28-3 6
19 CD_REF (I) REARSURR_OUT_L (B) 39 3 75-8P4R-LF 5 FRO_R
MIC2_R CT87 1UF/16V-LF 20 41 16V Y5V JD_MIC2 6
16V Y5V CD_R (I) REARSURR_OUT_R (B) SENSE_B MIC2_JD
16 MIC2_L (B) SENSE_B (I) 34
SENSE_A 17 33 EXT_VOL_CTRL R400 LF 10K-0402-LF FP_OUT_L RN28-4 5 4 75-8P4R-LF 9 9 10
MIC2_R (B) DCVOL (I) VCC5A FRO_L
13 40 JDREF R412 LF 1% 20K-1%-LF JD_LINEIN2 10
SENSE_A (I) NC/JDREF LINE2_JD
06030603
C SURR_OUT_LCT97 1UF/16V-LF 37 48 C
16V Y5V VREF_LINE1_R (O) SPDIFO (O) SPDIFI R370 R372 R374 R376 SENSE_B
45 47 7
LF
LF
LF
LF
SURR_L (O) SPDIFI/EAPD (B) F_IO_SEN
0805
SURR_OUT_RCT98 1UF/16V-LF 46 27 CT91 4.7UF/0805Y/10V-LF X22K X22K X22K X22K 2
16V Y5V SURR_R (O) VREF (O) Y5V 10V VREF_MIC1_L C425 AGND
12 PC_BEEP (I) VREF_MIC1_L (O) 28 V0.1 for Vista
0603
23,36 SPEAKER SPEAKER R395 LF 10K-0402-LF PC_BEEP C397 1UF/16V-LF 2 29 06030.1UF/16V/0402-LF

GPIO0 (B) VREF_LINE1_L (O)
0603
Y5V 16V 3 30 C403 1UF/16V-LF Y5V JD_LINEIN2 R442 0603-1% 39.2K-1%-LF HDR-5*2-GREEN-LF
C401 GPIO1 (B) VREF_MIC2 (O) Y5V 16V 16V COH2X5P-2_54-CP8
4 GND1 (P) VREF_LINE2 (O) 31
R393
06030.1UF/16V/0402-LF 7 32 VREF_MIC2 V 0.1 40.2K to 39.2K
GND2 (P) VREF_MIC1_R (O)
LF
Y5V 1K-0402-LF 1 JD_MIC2 R459 LF 1% 20K-1%-LF

16V VCC3_1 (P) VREF_MIC1_R
VCC3_2 (P) 9
CT99 26 25
08054.7UF/0805Y/10V-LF 42 AGND1 (P) VCC5A_1 (P) C405 C407 C402 C409
AGND2 (P) VCC5A_2 (P) 38
Y5V 06031UF/16V-LF
06031UF/16V-LF 06031UF/16V-LF
06031UF/16V-LF
10V ALC883-LF Y5V Y5V Y5V Y5V
LQFP48-0_5 16V 16V 16V 16V
VCC5A VCC3
CD1
1 CD_L JD_FRONT R356 0603-1% 5.11K-1%-LF SENSE_A
1 L(O)
2 CD_REF VREF Decouple Caps
GND1(P) JD_LINEIN1 R354 1% 10K-1%-LF
GND2(P) 3 LF
4 CD_R 1) Place close to codec as possible

4 R(O) JD_MIC1 R361 LF 1% 20K-1%-LF as you can.
HDR-4*1-BLACK-LF
COB1X4P-2_54-CD JD_REARSURR R362 0603-1% 39.2K-1%-LF 2) Signal trace routed through or
V0.1 for Vista beneath is forbidden.
JD_SURR R366 0603-1% 5.11K-1%-LF SENSE_B
B B
R385 LF 2.2K-LFVREF_MIC1_L JD_CENTER R364 LF 1% 10K-1%-LF V0.1 for Vista
Close to IC V 0.1 R329 40.2K to 39.2K
R384 LF 2.2K-LFVREF_MIC1_R
R317 R343 4.99K to 5.11K
GND_AUDIO GND_EMI_AUDIO AUDIO1B

GND_AUDIO GND_EMI_AUDIO
AUDIO1A
MIC1_L FB19 150OHM/400MA/150mOHM-LF C1 SURR_OUT_L FB21 150OHM/400MA/150mOHM-LF F1 FB1
L0603 MIC_REF (B) L0603 RSR_L (I)
C2 NC5 F2 NC5
JD_MIC1 C3 JD_SURR F3 GND_AUDIO FB15 GND_EMI_AUDIO
MIC1_R FB20 150OHM/400MA/150mOHM-LF NC6 SURR_OUT_R FB25 150OHM/400MA/150mOHM-LF NC6
C4 MIC_IN (I) BLUE F4 RSR_R (I) ORANGE
L0603 4 L0603 1
C359 C356 HOLE4 C370 C361 HOLE1 150OHM/400MA/150mOHM-LF
GREEN BLACK L0603
R321 R318 0603 0603 R340 R326 0603 0603
LF
LF
LF
LF
X22K X7R
X1000PF/X7R/16V-LF X7R X22K X22K X7R X7R
X22K PINK GRAY
16V 16V
X1000PF/X7R/16V-LF 16V
1000PF/X7R/16V-LF 16V
1000PF/X7R/16V-LF 7 GND
8 GND Don't stuff this bead.
LINE_IN_L FB16 150OHM/400MA/150mOHM-LF A1 CENTER_OUT FB23 150OHM/400MA/150mOHM-LF D1
Or it will degrade audio quality.
L0603 LINEIN_L (B) C1 L0603 SR_L (I) F1
A2 NC3 A1 B1 D2 NC3 D1 E1
JD_LINEIN1 A3 C2 JD_CENTER D3 F2
NC4 A2 B2 NC4 D2 E2
LINE_IN_R FB17 150OHM/400MA/150mOHM-LF A4 C0 LFE_OUT FB26 150OHM/400MA/150mOHM-LF D4 F0
L0603 LINEIN_R (B) A3 B3 L0603 SR_R (I) D3 E3
5 C3 2 F3
HOLE5 A4 B4 HOLE2 D4 E4
C350 C347 C4 C371 C365 F4
R311 R308 06031000PF/X7R/16V-LF
06031000PF/X7R/16V-LF R343 R332 0603 0603
LF
LF
LF
LF
X22K X22K X7R X7R X22K X22K X7R

1000PF/X7R/16V-LF X7R
16V 16V 16V 16V
1000PF/X7R/16V-LF
A1,B1,C1 D1,E1,F1
A A2,B2,C2 D2,E2,F2 A
FRONT_OUT_L R421
LF FB27 150OHM/400MA/150mOHM-LF B1 REARSURR_OUT_L FB22 150OHM/400MA/150mOHM-LF
E1 CENTER (I)
L0603 FRONT_L (I) A3,B3,C3 L0603 D3,E3,F3
0-LF B2 E2 NC1
NC1 A4,B4,C4 D4,E4,F4
JD_FRONT B3 JD_REARSURR E3 NC2
NC2 C0 F0
FRONT_OUT_R R420
LF FB18 150OHM/400MA/150mOHM-LF B4 REARSURR_OUT_R FB24 150OHM/400MA/150mOHM-LF E4 BASS (I)
0-LF L0603 FRONT_R (I) L0603
6 HOLE6 3 HOLE3
C354 C373 C0 C368 C364 F0 GND
06031000PF/X7R/16V-LF
06031000PF/X7R/16V-LF GND R335 R329 0603 06031000PF/X7R/16V-LF Title
LF
LF
R314 R351 X7R X7R X22K X22K X7R

1000PF/X7R/16V-LF X7R PHONE JACK-2X3-LF
AUDIO ALC662
LF
LF
X22K X22K 16V 16V PHONE JACK-2X3-LF 16V 16V CON26P-PHONEX6_P8

CON26P-PHONEX6_P8 Size Document Number Rev
A3 AN52 V0.2
5 4 3 2 1
5 4 3 2 1
+3.3V_DUAL
3VDUAL
Temperature Sensing (2.048V)
PWRBTN* R279 4.7K-0402-LF U15
23 PWRBTN*
102 65 HM_VREF=2.048V
"CPU Back / PWM use"
103 64 HM_VREF R205 2 1
HM_VREF
t
VCC3 QFP128 10K-1%-LF RT1 10K-1%THRM_0603-LF
0603
VCC3 128 39 VPWMTIN
C37 0.1UF/X7R/16V-LF
LPC_FRAME* R271 x4.7K-0402-LF 1 38 LPT VCC5 1
21,40 LPC_FRAME*
R199 LF 4.7K-0402-LF 128 47 "system use"
R269 4.7K-0402-LF VID0/GPSA1/GP10 (BD) STB# (OD) C239 R203
D 21 LPC_DRQ0* LPC_DRQ0* 127 VID1/GPSB1/GP11 (BD) AFD# (OD) 46 2 1 D
t
126 45 R272 LF 10K-0402-LF 1UF/16V-LF 10K-1%-LF RT2 10K-1%THRM_0603-LF
VID2/GPX1/GP12 (BD) ERR# (I)
0603
LPC_SERIRQ R270 4.7K-0402-LF 125 44 VSYSTIN
21 LPC_SERIRQ VID3/GPX2/GP13 (BD) INIT# (OD) IOAGND 8
124 43 C240 0.1UF/X7R/16V-LF
VID4/GPY2/GP14 (BD) SLIN# (OD)
1
2
123 VID5/GPY1/GP15 (BD) PD0 (B) 42
122 41 CT63 "CPU use"
VID6/GPSB2 (I)/GP16(BD) PD1 (B) 4.7UF/0805Y/10V-LF R204
121 VID7/GPSA2 (I)/GP17(BD) PD2 (B) 40 CPU_THERMDA 8
SIO THERM OUTPUT USED FOR EXT_SMI* 39 15K-1%-LF
GAME & MIDI &GPIO PD3 (B) VCPUTIN C196
2
PD4 (B) 38
VCC3 37 2200PF/X7R/16V-LF
PD5 (B)
BR8 PD6 (B) 36 8 IOAGND CPU_THERMDC 8
1 2 MCP_THERM* MCP_THERM* 23 PD7 (B) 35
R0402 5%
38 FANPWM_CPU1 FANPWM_CPU1 120 34
10K-0402-LF R2441 1K-0402-LF FANAUX2R1 CPUFANOUT1/MSO/GP20 (BD) ACK# (I) V0.1
38 FAN4_AUX2 2 119 CPUFANIN1/MSI/GP21 (BD) BUSY (I) 33
38 FANPWM_SYS R0402 5%
116 SYSFANOUT (O) PE (I) 32
38 FANPWM_CPU0 FANPWM_CPU0 115 31
CPUFANOUT0 (O) SLCT (I)
7 AUXFANOUT
RN23-1 8 1 1K-8P4R-LF SYSFANIOR 113 COM1
38 FAN3_SYS SYSFANIN (B)
RN23-2 7 2 1K-8P4R-LF CPUFANIOR 112 57
38 FAN1_CPU CPUFANIN0 GP60/RIA#
RN23-3 6 3 1K-8P4R-LF AUXFANIOR 111 56
38 FAN2_AUX1
RN23-4 5 4 1K-8P4R-LF 58
AUXFANIN0
AUXFANIN1/SO
GP61/DCDA#
GP62/SOUTA/PENKB 54 SIO_SOUTA Voltage Sensing (2.048V)
GP63/SINA 53
VCC3 52 DTRA RN25-1 8 1 10K-8P4R-LF VCCP_R
GP64/DTRA#(PENROM) VCCP
VCC3 51 RTSA
GP65/RTSA#(HEFRAS) RN25-2 7
GP66/DSRA# 50 VDDMEM 2 10K-8P4R-LF V_DDR
HW Monitor 49 RN25-3 6 3 10K-8P4R-LF
GP67/CTSA# 8 IOAGND
Q48 Q49 VSYSTIN 104 VCC3
K
BAT54C-LF BAT54C-LF VCPUTIN SYSTIN/VTIN1 (I) RN25-4 5

103 CPUTIN/VTIN2 (I) VTTMEM V1P2_LDT 4 10K-8P4R-LF V_VTT
VPWMTIN 102 COM2
C AUXTIN0/VTIN3 (I) R240 4.7K-0402-LF R226 10K-1%-LF V_PCIE C
85 LF
A1
A2
A1
A2
GP40/RIB# V1P2
HM_VREF HM_VREF 101 84
SYSFANIOR VCCP_R VREF (P) GP41/DCDB# FAN_SET2 20K-1% V_VCC NC
100 CPUVCORE (I) GP42/IRTX/SOUTB 83 VCC5
CPUFANIOR V_DDR 99 82 W83627DHG ref. 10K-1%
VIN0 (I) GP43/IRRX/SINB 8 IOAGND
AUXFANIOR V_VTT 98 81 is connect to IOAGNG
FANAUX2R1 V_PCIE VIN1 (I) GP44/DTRB# R229 20K-1%-LF +12VIN
97 VIN2 (I) GP45/RTSB# 80 not GND VCC12
3VDUAL +12VIN 96 79 R230 3.01K-1%-LF
VIN3 (I) GP46/DSRB# 8 IOAGND
GP47/CTSB# 78
1
MEM_VID0 R312
MEM_VID0
10K-0402-LF
Strap Pin
VCC3
2
43 SIO_PWRGD_SB 75 GP51/RSRMRST# (B) RSTOUT0# (O) 94

PIN92(GP30)Ε91(GP31)Ε69(GP36) 92 93 R266 LF 4.7K-0402-LF
8 PROCHOT_EN* GP30(BD) RSTOUT1# (O)
64(GP37)Ε87(GP35) are OD & Vstandby 91 90 R276 LF X0-0402-LF
GP31(BD) RSTOUT2#/SCL/GP32 SMB_SCL 23,26,27,28,30
& Reset not change 69 89 R277 LF X0-0402-LF R265 LF x1K
GP36 RSTOUT3#/SDA/GP33 SMB_SDA 23,26,27,28,30 36 WDTORST*
64 GP37 RSTOUT4#/GP34 88
87 GP35
VCC5SB
3VDUAL
R171
GP50 VIDLEVELΚHigh GTL LEVEL
1
VBATCCMOS 2 1 10M-LF
K
R227 110 VCC3

D10 10K-0402-LF SID
36 W_BEEP 118 BEEP/SI (OD) SIC 109
R202 1 10K-0402-LF
36 WDTORST* 77 WDTO#/GP50(EN_VRM10) PECI 108 2
LL4148/300MA-LF 38 CASEOPEN* 76 107 FAN_SET2 R238 LF 1K-0402-LF
R228 0-0402-LF CASEOPEN# (I) VTT R192 1 10K-0402-LF V1P2_LDT
23 EXTSMI*
LF 5 OVT#/HM_SMI# PECISB 106 2 Pin83 SOUTB
A
R252 33-LF
2
35,36 SIO_PSON*
LF 72 PSON#/GP53
B B
PWRBTN* 67 FAN_SET R200 LF 1K-0402-LF
23 PWRBTN* PSOUT#/GP57
36 SIO_PSIN* SIO_PSIN* 68 PSIN#/GP56 SCE#/GP22 19
R258 LF x0-0402-LF 71 2 Pin117 PLED/FANSETΚHigh PWMOUT100%
SUSLED PWROK/GP54 SCK/GP23
36 SUSLED 70 SUSLED/GP55
3VDUAL R440
23,43 SLP_S3* 73 GP52/SUSB#
1 2 KB 3VDUAL
LPC 63 SIO_KBDATA
GP26/KDAT SIO_KBDATA 40
2
x10K-0402-LF LPC_RST_SIO_TPM* 30 62 SIO_KBCLK
21 LPC_RST_SIO_TPM* LRESET# (I) GP27/KCLK SIO_KBCLK 40
21,40 LPC_FRAME* LPC_FRAME* 29 LFRAME# (I) R373
10K-0402-LF
21,40 LPC_AD0 27 LAD0 (B) KBRST (O) 60 SIO_KBRST* SIO_KBRST* 23 5%
21,40 LPC_AD1 26 LAD1 (B) GA20M (O) 59 A20GATE A20GATE 23 R0402
3VDUAL 25
R234 21,40 LPC_AD2 LAD2 (B) MS SER_RI*
21,40 LPC_AD3 24 LAD3 (B) SER_RI* 23
1
1 2 21 LPC_DRQ0* LPC_DRQ0* 22 LDRQ# (O) GP24/MDAT 66 SIO_MSDATA SIO_MSDATA 40
21 65 TJP!DPNྤ໦ᙌ‫פ‬౨<joqvuլᏁQVMM!IJHI
21 LPC_CLK_SIO LPC_CLK_SIO SIO_MSCLK SIO_MSCLK 40
10K-0402-LF PCICLK (I) GP25/MCLK VCC3
21 LPC_SERIRQ LPC_SERIRQ 23 SERIRQ (B)
23 IO_PME* 86 PME# (OD)
BUF_SIO_CLK 18 117 FAN_SET SIO_SOUTA R275 10K-0402-LF
23 BUF_SIO_CLK CLKIN_48/24 (I) PLED/FAN_SET SIO_SOUTA Hi Enable KBC
SIO_SST R198
Default 48MHz SST 114 1
R0402 5%
2
FDC AVCC 10K-0402-LF C282 0.1UF/16V/0402-LF DTRA R274 <᥆ࢤ3> 1K-0402-LF

AVCC 95
0603
VCC3 1 IOAGND Low Disable SPI V0.2
40 SIO_FD_DENSEL DRVDEN0 (OD) AGND 105 RTSA R273 1K-0402-LF
40 SIO_FD_INDEX* 3 INDEX# (I)
4 Low BASE ADDRESS 2EH
AVCC FB13 150OHM/400MA/150mOHM-LF
40 SIO_FDD_MTR0* MOA# (OD) VBAT (P) 74 VBATCCMOS <᥆ࢤ3>
40 SIO_FDD_DS0* 6 DSA# (OD)
L0603 <᥆ࢤ3>
40 SIO_FDD_DIR* 8 DIR# (OD) 3VSB (P) 61 3VDUAL Straping
C271 C273 9 SUSLED need to be pull low
40 SIO_FDD_STEP* STEP# (OD)
0603 0603X2200PF 10 C298
A
0.1UF/16V/0402-LF
40 SIO_FDD_WDATA* WD# (OD) VCC3_1 (P) 12
http://laptop-motherboard-schematic.blogspot.com/ VCC3
06030.1UF/16V/0402-LF if High may be enter test mode A
40 SIO_FDD_WGATE* 11 WE# (OD) VCC3_2 (P) 28
IOAGND FB10 150OHM/400MA/150mOHM-LF 13 C276 C291 C297
8 IOAGND L0603 40 SIO_FDD_TRK0* TRAK0# (I) VCC3_3 (P) 48 0603 0603 0603
+3.3V_DUAL
40 SIO_FDD_WRTPRT* 14 WP# (I)

15 20 0.1UF/16V/0402-LF 0.1UF/16V/0402-LF
40 SIO_FDD_RDATA* RDATA# (I) VSS_1 (P)
16 55 0.1UF/16V/0402-LF
40 SIO_FDD_HDSEL* HEAD# (OD) VSS_2 (P)
17 close to Pin12 Pin28 Pin 48
40 SIO_FDD_DSKCHG* DSKCHG# (I)
W83627DHG-LF Title
PQFP128-0_5-A
SIO-W83627DHG
A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
VCC12A
ATX12V1
1
GND VCC12A v0.2
5
+12V 1.2UH/10A/2.2mOHM-LF VIN
VCC3 2
GND L2
RP1 6
+12V
1 2
VREG_VID0 1 5 3
GND
R1 C
VREG_VID1 2 R2 7
+12V C31 + CE7
VREG_VID2 3 R3 C 10 3VDUAL 4
GND + +
1200UF/16V/LR/DIP-LF 1200uF
VREG_VID3 4 8
+12V 1UF/16V-LF CE12 CE2 v0.2
VREG_VID4 R4 1200UF/16V/LR/DIP-LF 1200UF/16V/LR/DIP-LF
6 R5 COP2X4P-ATXS
VREG_VID5 7 I178
R6 R28
8
LF
R7 4.7K-0402-LF VIN
9
D
D R8 Q4 D
Near PWM
D
1K-10P8R-LF Q5 G
5VDUAL v0.2 BOM C43
W83303D_PSOUT* G 2N7002/100mA-LF CT10 Y5V>X5R 0.1UF/16V/0402-LF
D
S
2N7002/100mA-LF <Type1> Q2 1206 0603
D
S
<Type2> G PWRGD_PS 36,43 Q14 10UF/X5R/16V/1206-LF
R46 R57 FET-TO252
G
LF
2N7002/100mA-LF 2.2-0805-LF
Sense point
DS
10-LF <Type1> TO252 VCCP
S
20_RT8801_VDD <Type2>
Q1 06N03/25V/35A/5.7m-LF
<Type1>
3VDUAL G CPUVDD_EN 23 <Type2>
L3 0.6UH/38A/Square-LF
C33 1 2
06030.1UF/16V/0402-LF VCC12A 2N7002/100mA-LF U4 VCC12A 0.80mOHM
D
+ CE5
S
16V <Type1> RT9605BPQ-LF Q15 Q16
X7R FET-TO252 FET-TO252
<Type2> PVCC1 22 15_PVCC1 R44 LF G G v0.2 1500UF/MBZ/6.3V-LF
R14 D2 10-LF R53 + CE6
LF
A
4.7K-0402-LF U2 R2 5VDUAL LL4148/300MA-LF TO252 TO252 2.2-0805-LF 1500UF/MBZ/6.3V-LF
SDO80
LF
S
26 9.09K-1%-LF 06N03/25V/35A/5.7m-LF
<Type1> 06N03/25V/35A/5.7m-LF
<Type1> v0.2
VDD
1%
SLOTOCC 1 R22 0603 C32 <Type2> <Type2>
SLOT_OCC
K
23,43 CPU_VLD 14 10-LF 215_BOOT1 1UF/16V-LF C41
LF
PGOOD BOOT1
1
23,43 PWRGD_SB 4 12 RT8801_DVDEN 16V 06034700PF-LF
RST# DVD C14 Y5V XTR5
20_RT9605_5V 8 0.1UF/16V/0402-LF Low Side MOSFET: xTRACE10
R45 R15 5V Y5V 0603 IPD09N03LA -> IPD06N03LA
LF
0-LF 1K-1%-LF 16V R52
13,14,15,16,23,43 SMB_MEM_SDA 2 DATA 0603 30_UG1 VIN 2200uF/MBZ/6.3V
2
13,14,15,16,23,43 SMB_MEM_SCL 3 CLK UG1 1 0-0805-LF
GND C11
VREG_VID5 1UF/16V-LF 30_PHASE1
PWM4
37 VREG_VID5 32 VID5 PHASE1 24
VREG_VID4 27 v0.2 BOM
37 VREG_VID4 VID4
37 VREG_VID3 VREG_VID3 28 25 23 30_LG1 CT19 Y5V>X5R C60
VREG_VID2 VID3 PWM4 PWM3 LG1 1206 0603
37 VREG_VID2 29 VID2 PWM3 24 7 PWMIN3
C 5VDUAL 37 VREG_VID1 VREG_VID1 30 23 PWM2 5 VCC12A 10UF/X5R/16V/1206-LF 0.1UF/16V/0402-LF I reference point C
D
VREG_VID0 VID1 PWM2 PWM1 PWMIN2 Q18
37 VREG_VID0 31 VID0 PWM1 22 4 PWMIN1 FET-TO252
PVCC2 21 15_PVCC2 R48 LF 10-LF R71 G
21 RCSP1 D4 2.2-0805-LF Sense point
A
R23 ADSEL 5
4.7K-0402-LF CSP1 RCSP2 LL4148/300MA-LF
5VDUAL
LF 20 near RT8801<0.5inch, TO252
SDO80
LF
AD_SEL CSP2
S
R3 R25 LF x4.7K-0402-LF 19 RCSP3 C34 06N03/25V/35A/5.7m-LF
<Type1> L5 0.6UH/38A/Square-LF
220K-LF CSP3 RCSP4
far away the MOSFEET
Hi:0X5E Low:0x5C CSP4 18 0603 <Type2> 1 2
K
VOSS 11
LF
R35 LF 680-LF 16 15_BOOT2 0.80mOHM
D
VOSS BOOT2 1UF/16V-LF
RT 15 RT
R21 0-LF R31 LF 680-LF v0.2 BOM
16V
Q20 Q19 v0.2 + CE9
SS 13 R26 680-LF C30 G FET-TO252 G FET-TO252 R61 1500UF/MBZ/6.3V-LF
SS
LF 1K > 680 ohm Y5V
ICOUT 7 0.1UF/16V/0402-LF 2.2-0805-LF + CE11
LF
R16 R13 C3 IC_out CSN Richtek: 680 ~ 1K Y5V 0603 1500UF/MBZ/6.3V-LF

16 TO252 TO252
CSN
LF
16V v0.2
S
x68K 40.2K-1%-LF 06030.1UF/16V/0402-LF R = L/(DCRxC) 06N03/25V/35A/5.7m-LF
<Type1> 06N03/25V/35A/5.7m-LF
<Type1>
1%
16V C9 = 0.6uH/(0.8mohm x 1uF) = 750 ohm <Type2> <Type2>

C54
1
v0.2 v0.2 BOM X7R 06030.1UF/16V/0402-LF 10 17 30_UG2 06034700PF-LF
16V SGND UG2 XTR4 XTR3
BOM 20K > 30.1K
X7R 19 30_PHASE2 xTRACE10
300KHz ->230KHz->200KHz ADJ R39 xNC PHASE2 xTRACE10
ADJ 17 LF
V0.2 30.1K-1%->40.2K-1% FB 8 33 20 30_LG2 VIN

FB GND2 LG2
0603
C25 + CE13 + CE15
2
GND1 6
0603
LF FBCOMP C4 2200PF/X7R/16V-LF
9 COMP 1UF/16V-LF VCC12A R58 0-0805-LF 1500UF/MBZ/6.3V-LF
1500UF/MBZ/6.3V-LF
R18 7.5K-1%-LF 50V X7R v0.2 BOM
RT8801B-LF R32 LF xNC 15 15_PVCC3 R30 LF 10-LF CT32 Y5V>X5R C79
D
PVCC3
0603
COMP D3 Q22 1206 0603
A
0603
C7 33PF/NPO/50V-LF C8 C15 LL4148/300MA-LF R84 G FET-TO252 10UF/X5R/16V/1206-LF 0.1UF/16V/0402-LF
SDO80
VCCP 0603xNC 1UF/16V-LF 2.2-0805-LF v0.2
V0.1 0603 C27 TO252 Sense point
0603
S
C6 680PF/X7R/16V-LF
R10 LF 100-1%-LF R24 R27 LF xNC 9 15_BOOT3 06N03/25V/35A/5.7m-LF
<Type1>
LF
50V X7R 51.1-1%-LF BOOT3 1UF/16V-LF L6 0.6UH/38A/Square-LF

16V <Type2>
0603
C10 C13 1 2
R19 LF 1K-0402-LF R7 0-0805-LF CPU_CORE_FB 8 1UF/16V-LF 0.1UF/16V/0402-LF Y5V 0.80mOHM
D
NTC
Y5V 0603 Q23 Q24 v0.2

1
16V FET-TO252 FET-TO252 R82

B 20mils G G B
C1 3 2.2-0805-LF
R20 NC 30_UG3
6 10 TO252 TO252
LF
GND1 UG3
1
v0.2
S
0.1UF/X7R/16V-LF R41 12 06N03/25V/35A/5.7m-LF
<Type1> 06N03/25V/35A/5.7m-LF
<Type1>
LF
xNC V0.1 v0.2 100-1%-LF GND2 30_PHASE3 XTR2

2
13 GND3 PHASE3 11 <Type2> <Type2>

UL8 Pro: 470-LF -> 100 ohm/1% 18 C76 xTRACE10
10K-1%THRM_0603-LF -> 10K ohm GND4 30_LG3 06034700PF-LF
25 14
Please near Pin17 of RT8801, GND5 LG3
then Load-Line will be better. 1 XTR1 R73 0-0805-LF
2
2
xTRACE10
8 CPU_CORE_FB* R11 LF 402K-1%-LF

VCCP 20_CSP1
20mils R17 v0.2 BOM
1
R12 20_CSP2
LF
LF
C5 V0.2 1.47K-1%->402-1%
1%
R47 100-1%-LF 121K-1%-LF 20_CSP3

LF
0.1UF/X7R/16V-LF
100-1%-LF 20_VCCPCSP
2
near RT8801< 0.5inchΔ Trace width:30mil-->UGATE[3..1]

V0.1 VCCP
VCCP far away the MOSFEET. Trace width:30mil-->LGATE[3..1]
Trace width:30mil(reference GND)
1
(Solider side)-->PHASE[3..1] CT15 CT7 CT13
D
10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF
1
Q8
2
W83303D_PSOUT* G FDD8878/14m/40A-LF CT8 CT11 CT12
S
10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF
2
A A
Title
PWM RT8801 & RT9605

Custom AN52 V0.1
5 4 3 2 1
5 4 3 2 1
VCC5SB
88E3018 LAN PHY 2.5V @ 500mA MAX V1P2 CORE
VCC5SB D13 VCC5 VCC5 5VDUAL U17 RC1117ST/SOT223-LF V2P5_DUAL_LAN V1P8_DUAL_LAN
3V_DUAL 5VSBA BAT54C-LF VCC5SB SOT223 VCC3 1.2V @ 10A MAX
A1 I IN(I) OUT(O) O
ADJ(I)
1
1 K VCC5SB CT104 VAGP: V1P2_DUAL
1
3VDUAL CE8 C204 A2 C301 CT73 10UF/10V/0805-LF 0.8V-1.05V (8 Step)*1.5
D
2
3VDUAL Q31 CT83 CT81 1 0805 R268 CT72 C295 3VDUAL Q55 C343 V0.2
1000UF/YXG/6.3V/DIP-LF FDD8878/14m/40A-LF CE32 0.1UF/16V-LF 0805 0.1UF/16V-LF 2N7002/100mA-LF
+ +
1
1%
G
2 0.1UF/16V-LF 3VSB_DRV 1000UF/YXG/6.3V/DIP-LF 4.7UF/0805Y/10V-LF R1
124-1%-LF AGP_DRV 0.1UF/16V-LF R286
G G
4.7UF/0805Y/10V-LF V1P2_REF
2
0-0805-LF
D S
S
2 1 3VSB_SEN
1 2 100uF->1000uF 3VDUAL R408 R291
R304 0-LF 10UF/10V/0805-LF x10K-LF AGP_SEN 1 12 1 V1P2_REF
1
1
D 1 1 VCC3 Q32 R306 10UF/10V/0805-LF C299 R278 1K-1%-LF R486 x0-0805-LF D
CE25 CE38 FDD8878/14m/40A-LF x10K-1% CT75 C303
CT55 G VCC_DRV Close to W83303D x0.1UF R2 R414 R292 R290
D 2
1%
1000UF/YXG/6.3V/DIP-LF C231 5VSBA 124-1%-LF x10K-LF x2K-1% 2.0K-1%-LF C333
2
LR1_DRV
LR1_SEN
1000UF/YXG/6.3V/DIP-LF
2 2 0.1UF/16V-LF Q68 1UF/16V-LF 0.1UF/16V-LF
S
D
VCC3 2 2
10UF/10V/0805-LF x2N7002/100mA-LF Q53 10UF/10V/0805-LF
2
VLR2_CHANGE G
1
R413 x0-LF G x2N7002/100mA-LF
S
C344 V0.2 GP23&GP24 SWAP R487
R296 R297 0.1UF/16V-LF Close to W83303D
S
5V_DUAL VCC5SB 2 1
different with 0-LF 0-LF
2
HT
2
W83304CG ref. circuit LR1_DRV 0402_R
LR1_DRV_R
LR1_SEN_R
5VDUAL R299 x0-LF 5%
LR1_DRV
R488 x0-0402-LF
AGP_DRV
AGP_SEN
1.2V@900mA MAX
LR2_DRV
LR2_SEN
x10K-0402-LF
S
5%
5VDUAL C45 G 5VSB_DRV R300 0402_R LR1 ,LR2 ,LR4: 3VDUAL
0.1UF/16V-LF
0-LF 0.8V-1.05V (8 Step)
Q13 VCC3
FDD8878/14m/40A-LF 3VSB_DRV VLDT:
1
D D
3VSB_SEN LR1_SEN 1.2V-1.5V (7 Step) R283

1 1 37 VCC_DRV VCC_DRV R301 x0-LF 1K-LF V1P2_LDT
CE37 CE3 C22 VCC5 Q12 V0.1 LΚDisable
FDD8878/14m/40A-LF Q25 C129
36
35
34
33
32
31
30
29
28
27
26
25
D
E
SOT23
0.1UF/16V-LF G VCC_DRV 5VSB_DRV U18 APM3055L/12A/TO252-LF 0.1UF/16V-LF
2 2 HTVDD_EN R284 4.7K-LF
B PMBS3906-LF
3VSB_SEN
VAGP_SEN
5V/3V_DRV
VLDT_SEN
3VSB_DRV
VAGP_DRV
LR1_DRV
LR1_SEN
LR2_DRV
LR2_SEN
5VSB
VLDT_DRV
23 HTVDD_EN Q54
S
C46 C349 G
1000UF/YXG/6.3V/DIP-LF 0.1UF/16V-LF 200mA V1P2_LDT
C
1000UF/YXG/6.3V/DIP-LF x0.1UF/16V-LF 40V
S
R302
V0.2 NC LR1_SEN TR-SOT23
2 1
1
C VCC5 1K-1%-LF 1 1 C
+ SC1 CE16 CE17 C126 C345 C339 R294
37 5VSB_DRV GND 24 V0.2
2 1 38 C1(I) VDDIO_DRV 23 VDDIO_DRV R293
3VDUAL C352 0.1UF/16V-LF 39 22 NC 2.0K-1%-LF x120UF/2V-LF 1000UF/YXG/6.3V/DIP-LF 1UF/16V-LF x470-LF
9VSB 40 C2(I) 5VUSB_DRV LR3_DRV 1000UF/YXG/6.3V/DIP-LF
2 2 0.1UF/16V-LF
different with ANM2 R323 1K-LF CHR_PMP H/LR3_DRV 21
LR3_SEN VDDIO Type select: 2 0.1UF/16V-LF
5VSBA 41 5VSB H/LR3_SEN 20
42 GND VDDIO_SEN 19 VDDIO_SEN 1: PWM Mode
23,35 PWRGD_SB 2 R322 0-LF RSMRST* 43 RSMRST#(OD) W83304CG-LF LR4_DRV 18 LR4_DRV 0: Linear Mode
44 17 LR4_SEN
R330 x0-0402-LF NC LUVDET#(I) LR4_SEN PWM_MODE R331 4.7K-LF VCC5SB 3VDUAL
1 2 45 MISC_EN(OD) PWM_MODE(I) 16
C357 35,36 PWRGD_PS 46 15 R334 100K-LF V1P2_DUAL
x1UF/16V-LF SLP_S3* PWR_OK(I) ISET(AI.AO) 3VDUAL
47 14 1 2
ALL_PWR_OK(OD)
PS_ON_OUT#(OD)
23,32 SLP_S3* S3#(I) SS(AI/AO)
32 SIO_PWRGD_SB R315 x0-LF 23,37 SLP_S5* SLP_S5* 48 13 C367 0.22UF/16V-LF
VCORE_EN(OD)
S5#(I) A0(I)
1
1 LR1 ,LR2 ,LR4: Q58 C369
I2C_DATA(I/O)
VCORE_GD(I)
D
PS_ON_IN#(I)
2.5VDDA(AO)
from SIO 3VDUAL A0 0.8V-1.05V (8 Step) APM3055L/12A/TO252-LF To W83320S & SB
DDRDET#(I)
2
I2C_CLK(I)
R333 4.7K-LF C358C355 R338 3VDUAL R409 0.1UF/16V-LF
FAULT#(I)
VCC5SB
VCC5SB R327 4.7K-LF LUVET# R337 4.7K-LF x4.7K-LF x10K-LF LR2_DRV G V1P2_DUAL
1
VCC3
GND
0.1UF/16V-LF
S
LUVDET# R339 LR2_SEN 1 12 1
R328 0.1UF/16V-LF 4.7K-LF R410 R289 1K-1%-LF 1
1
D 2
1: ENABLE LUV FUNCTION
0: DISABLE LUV FUNCTION x4.7K-LF x10K-LF R298 CT84 CE30
10
11
12
V0.2 GP23&GP24 SWAP Q67 R285 C378
1
2
3
4
5
6
7
8
9
2.0K-1%-LF
3VDUAL 2 1 v0.2 A0 C360 0.1UF/16V-LF 1000UF/YXG/6.3V/DIP-LF
R346 4.7K-LF x2N7002/100mA-LF 2.0K-1%-LF 1UF/16V-LF 10UF/10V/0805-LF
2
2
1: address = 0x5E VAGP_CHANGE G
D
R403 x0-LF 2 2
MCP55_PWRGD 1 2 0: address = 0x5C
R345 0-LF R344 10K-LF Q52
S
V0.2 After EVT Change
VCC3
2
R489
1
0-0402-LF
G 2N7002/100mA-LF CORE 1.2V AUX
1.2VDUAL @ 850mA MAX
S
VDDIO 3VDUAL 0402_R
B VCC3 5% B
(when DDRDET#=1 ,PWM Mode=1) R490
DDRDET# 10K-0402-LF
VCC5SB 1.8/2V - 2.5/2V (11 Step)
DDRII VREF
1
1 5%
R357 4.7K-LF C372 0402_R
DDRDET# 2.25-3V(0.125V/Step) Q57 C340

For HT OVP
D
1: 1.8V FOR DDR2 13,14,15,16,23,35 SMB_MEM_SCL SMB_MEM_SCL 0.1UF/16V-LF R360 2N7002/100mA-LF V1P2_LDT
SMB_MEM_SDA 0.1UF/16V-LF VDDMEM_REF
1
0: 2.5V FOR DDR1 13,14,15,16,23,35 SMB_MEM_SDA 4.7K-LF
VDDIO_DRV 1.46V LR3
2
G
VCC5SB 1 (when DDRDET#=1 ,PWM Mode=1)
1
R347 4.7K-LF VDDIO_SEN
S
2 1R317 C353
2
2 0.8V-1.1V (11 Step)*1.5

R358 4.7K-LF 1 2 2 R313
OVPEN* OVPEN* R348 4.7K-LF R349 4.7K-LF 1K-1%-LF C351 CT79 CT78
1
V0.1 3VDUAL R319 150-1%-LF

0.1UF/16V-LF 5VSBA
Q47 C374 R320 1K-1%-LF0.1UF/16V-LF 10UF/10V/0805-LF LR3_SEN
2
C 35,36 SIO_PSON*
1
1
form PWM PWRGD PMBS3904-LF x0.1UF/16V-LF 1.1K-1%-LF 10UF/10V/0805-LF 2
2
1
CPU_VLD 1 10K-LF 1 R316 C348 OVPEN*
23,35 CPU_VLD 2 B W83303D_PSOUT* OVPEN*
R235R0603 x330-LF 3VDUAL R336 1 VCCP R369
2
5%
D
D
E 2.24V 10K-LF Q64
For VCCP OVP
1
35,36 HTVDD_EN R359 x0 Q59 178-1%-LF

CPU_THERMTRIP_W* 2N7002/100mA-LF 0.1UF/16V-LF 2N7002/100mA-LF
2
G 1 G
1
R352 Q60 C363 1
D2
D2
1
S
S
10K-LF V0.2 R325 Q56
3VDUAL 2 1 3VDUAL 2N7002/100mA-LF R367
R236 10K-LF G 2N7002/100mA-LF 178-1%-LF
0.1UF/16V-LF 5VSBA LR3_DRV 1 2 G 0-LF
32 VDDMEM_GPIO
1
R353 0-LF LR4_SEN R307 0-LF

2
1
CPU_THERMTRIP_W* 2
S
S
from MCP665 GPIO
1
R190 R324 C362 OVPEN* 2
OVPEN*
D
10K-LF R365
D
Q46 3VDUAL 10K-LF Q65 R309
A G 2N7002/100mA-LF 0.1UF/16V-LF
100-1%-LF x7.15K-1%-LF A
Q45 2N7002/100mA-LF
2
2
C 1 2 G
S
PMBS3904-LF
D2
R208 1
R189 10K-LF Q62
S
8,18 CPU_THERMTRIP* 1 2 B CPU_THERMTRIP_MCP65*
from CPU R0603 5% to MCP655 (3VDUAL) 2N7002/100mA-LF R368
D
1
220-LF C262 E LR4_DRV 1 2 G 0-LF

Q42 R342 0-LF
S
G 2N7002/100mA-LF LR1 ,LR2 ,LR4:
x0.22UF/16V-LF 2 Title
0.8V-1.05V (8 Step)
W83304CG
S
2
v0.2 R350
x7.15K-1%-LF Size Document Number Rev
A3 AN52 0.2
5 4 3 2 1
5 4 3 2 1
MCP65 V1P2 CORE

1.2V@ 10AMP (1.2V- 1.6V)
MCP65 Core
V0.2 Q36 V1P2
D VCC5 VCC5 06N03/25V/35A/5.7m-LF D
S
DRVLO2 R160 GATE_L2 G
2
1 0-0805-LF
R143
C214 I_lim = (72uA * RISEN)/RDSON L14
= (72uA*10K)/14mohm = 51.43A
D
4.7-0805-LF 0.1UF/16V-LF PH2 1 2
U12 V0.2
1
2 R152 3.3UH/25A/6.3mOHM/Square-LF CT69 CT68 CT66 CT57 1 1
1
1
1 14 ISEN2 1 2.0K-1%-LF 2 ISEN2R C279 C283 C281 C280
C216 LDRV ISEN R179
2 13
S
VDDA2 VDD PGND DRVHI2 R191 GATE_H2 2.2-0805-LF 0.1UF/X7R/16V-LF CE27 CE26
3 VDDA HDRV 12 G
1UF/16V-LF BOOTCORE2 0-0805-LF 1500UF/MBZ/6.3V-LF
2 2 0.1UF/16V/0402-LF
0.1UF/16V/0402-LF
0.1UF/16V/0402-LF
2
4 PWROK BOOT 11
1
Q37
2
5 GND ISET 10
2 REFINCORE2 C225 06N03/25V/35A/5.7m-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF 1500UF/MBZ/6.3V-LF
6 SS REFIN 9
D
VCC5 7 8 FB2 0.22UF/16V-LF 10UF/X5R/6.3V/0805-LF 10UF/X5R/6.3V/0805-LF
R142 COMP FB C233
C221 W83320G-LF VCC5 1000PF/X7R/16V-LF VCC3 VCC5
2
1 2 D7
COMP21 2 R147 100K-LF 1 A1 1.2uH/6A/4mOHM-LF
10K-LF K L13 1 2
3026
2
1 2200PF/X7R/16V-LF
1 2 A2 1
32 V1P2_VLD C220 x0.022UF/16V-LF
2
CE23 4mOHM 1
C215 R151 BAT54C 0805 CT61 CE24
39.2K-1%-LF CT60 1500UF/MBZ/6.3V-LF 0805 1000UF/YXG/6.3V/DIP-LF
0.1UF/16V-LF 4.7UF/0805Y/10V-LF 2 6.3V,10*12.5mm 4.7UF/0805Y/10V-LF
2
2
1
1 2 V1P2_REF 43
Freq.=200KHz*(1.19V/Rset)/24uA R150 4.7K-LF
1
1
C
1.Rset=49.9K -> 200KHz C
2.Rset=39.2K -> 252.98KHz
R157 C229
C224 x390K-LF 0.1UF/16V-LF
1UF/16V-LF
2
2 2
R146 1R148 21C228 2

x20K-1%-LF x10K-LF x1UF/16V-LF
2 1
1 R149 10K-1%-LF
V0.2
DDRII MEMVDD DDRII VTT

5VDUAL
Q11 7AMP @ 1/2MEMVDD
22AMP @1.8V
S
5VDUAL DRVLO1 R54 GATE_L1 G 06N03/25V/35A/5.7m-LF

2
1 0-0805-LF
R85 VDDMEM
C110 I_lim = (72uA * RISEN)/RDSON L4 VDDMEM VDDMEM 3VDUAL VDDMEM
B = (72uA*10K)/14mohm = 51.43A B
D
4.7-0805-LF 0.1UF/16V-LF PH1 1 2 3VDUAL

1000uF/6.3V
U6 V0.2
1
2 R76 3.3UH/25A/6.3mOHM/Square-LF 1 1 C72
1
0603
1 14 ISEN1 1 2.0K-1%-LF 2 ISEN1R SC2 + CT31 CT33 C148 R100
C111 LDRV ISEN R51 C61 0603 1K-1%-LF
2 13 C159 0.1UF/16V-LF
S
VDD PGND U10
1
VDDA1 3 12 DRVHI1 R29 GATE_H1
G 2.2-0805-LF CE10 CE14 0.1UF/16V/0402-LF C169
1UF/16V-LF VDDA HDRV BOOTCORE1 0-0805-LF 0.1UF/X7R/16V-LF 2 2 0.1UF/16V-LF 06030.1UF/16V-LF
2
4 11 8
VIN
PWROK BOOT VREF2
1
Q9 x120UF/2V-LF
2
5 GND ISET 10 VCTRL 6
2 REFINCORE1 C77 06N03/25V/35A/5.7m-LF 1500UF/MBZ/6.3V-LF 83310_VREF1
6 SS REFIN 9 3 VREF1
D
5VDUAL 7 8 FB1 0.22UF/16V-LF C39 10UF/X5R/6.3V/0805-LF 1500UF/MBZ/6.3V-LF VTTMEM

R86 COMP FB 1000PF/X7R/16V-LF 10UF/X5R/6.3V/0805-LF VTTMEM
C92 W83320G-LF 5VDUAL 5VDUAL
2
1 2 D5 5 4
BOOT_SEL VOUT
1 COMP1 1 2 R83 100K-LF 1 A1 1.2uH/6A/4mOHM-LF C147 R99 1
10K-LF K 5VDUAL_IN1 L1 1 2 0603 1K-1%-LF 7 CE20
3026
GND
GND
ENABLE
2
C108 2200PF/X7R/16V-LF
1 2 2 A2 0.1UF/16V-LF 1000UF/YXG/6.3V/DIP-LF
C109 x0.022UF/16V-LF CT5 CT4 1 4mOHM 1
0.1UF/16V-LF R77 BAT54C 0805 0805 CE1 CE4 W83310DG-LF2 1000uF/MBZ/10V
39.2K-1%-LF 4.7UF/0805Y/10V-LF 1500UF/MBZ/6.3V-LF
2
9
2 4.7UF/0805Y/10V-LF 1500UF/MBZ/6.3V-LF
2 2
Freq.=200KHz*(1.19V/Rset)/24uA
1
1.Rset=49.9K -> 200KHz

2.Rset=39.2K -> 252.98KHz 1 2 1 VDDMEM_REF
R72 4.7K-LF
MEM VTT Power module 8*11
1
C78 C73
R74 0.1UF/X7R/16V-LF
x390K-LF
2
1UF/16V-LF
2
2
A A
R78
x4.99K-1%-LF 1R80 21C74 2
x10K-LF x1UF/16V-LF
1
2 1
R79 4.99K-1%-LF
Title
NB CORE & DDRII Power

A3 0.2
AN52
5 4 3 2 1
3VDUAL D18
32 WDTORST* K A
2
VCC5SB R174
15K-1%-LF xLL4148/300MA-LF 3VDUAL
2
5%
R0603
VCC5A NORMAL VOLTAGE = 4.7V (2%)
2
R182
10K-0402-LF MEM_VLD 3VDUAL V1P8DUAL_BUFFER
5% MEM_VLD 23 R341
VCC5SB U5
D1
R0402 Q38 x10K-LF
5%
2N7002 FB1 L0603
R0603 V0.2 1 VIN VOUT 5
2
V0.2 MEM_VLD_5V* G C366 30 OHM/100MHz/3A/0603-LF
VDDMEM Q40 MCP55_PWRGD_R
1
C FET-SOT23 R355 MCP55_PWRGD 23,43
x0.1UF/16V-LF x10K-LF R388 x0-LF C36 R38
D1
R183 MEM_VLD_RC
MMBT3904 3 EN
LF
5%
S
1 2 B R0603 06031UF/16V-LF R1 121-1%-LF
1
1%
R0603 5% 4.7K-LF Q61 C393 Y5V
1
CT62 TR-SOT23 E 16V
MCP55_PWRGD_5V*G 2 4
R491 x4.7UF x2N7002/100mA-LF GND ADJ
D1
S
15K-1%-LF C0805
?
0.1UF/16V-LF RT9179/1%/300mA-LF
10V
10% Q63 R40 C28
R363
2MCP_PWRGD_RC G R2 0603x0.1UF
2
43 VCC_DRV 1
x2N7002/100mA-LF VOUT=1.175x(1+R1/R2) 221-1%-LF
2
R0603 5%
S
Q39 x10K-LFCT80
D
x4.7UF/0805Y/10V-LF
2N7002
SLP_S5* G C0805
23,43 SLP_S5* ?
16V
10%
FET-SOT23 EMPTY
2
S
D
Q66
R378
1 2 G x2N7002/100mA-LF
32 V1P2_VLD
S
x10K-LF 2 1
C379 x0.47UF/16V-LF
3VDUAL SBIOS PROGRAMMING STEPS

V1P8DUAL_BUFFER
2
1. READ VID INPUT ON SIO

R168 2. SET SIO VID TO THE READ VALUE
VCC5SB 10K-0402-LF V0.2 C18 3. SET SIO VID TO OUTPUT STATE
5%
R0402 CT105 4. SET "CPU_VID_OVERRIDE" GPIO HIGH
2
V0.1 6.2k ->4.7k 0805 5. SET NEW SIO VID OUTPUT VALUE
R161 0.1UF/16V-LF
0.47uF ->1uF 10K-0402-LF HTVDD_VLD 4.7UF/0805Y/10V-LF
D 1
5% HTVDD_VLD 23
V0.2 R0402 Q34 R170 0-LF
2
2N7002
14
G C380 U1A 74LVC07A-LF
HTVDD_VLD 23 SOP14-1_27
V1P2_LDT x0.1UF/16V-LF CPU_VID[5..0] VREG_VID[5..0]
1
Q35 C FET-SOT23 8 CPU_VID[5..0] VREG_VID[5..0] 35

MMBT3904 0 1
˖ˣ˨˲˩˜˗˃ 2 0 ˩˥˘˚˲˩˜˗˃
S
from CPU to PWM

1
HT_VLD_RC B
1
R167 4.7K-0402-LF
TR-SOT23
E
R492 0603 C235
7
15K-1%-LF
x1UF/16V-LF
1 1
2
U1B SOP14-1_27
3
˖ˣ˨˲˩˜˗˄
4 ˩˥˘˚˲˩˜˗˄
Reserved for AM2+ CPU_NB CORE

10AMP @1.2V 2
U1C SOP14-1_27
2 ˩˥˘˚˲˩˜˗˅
5
˖ˣ˨˲˩˜˗˅ 6
VCC5 VCC5
DRVLO3
v0.2
NBVDD
I_lim = (72uA * RISEN)/RDSON PH3 U1D SOP14-1_27

= (72uA*4.7K)/15mohm = 3 9
˖ˣ˨˲˩˜˗ˆ 8 3 ˩˥˘˚˲˩˜˗ˆ
22.56A
ISEN3 ISEN3R
VDDA3 DRVHI3 GATE_H3

BOOTCORE3
U1E SOP14-1_27
REFINCORE3 4 11
˖ˣ˨˲˩˜˗ˇ 10 4 ˩˥˘˚˲˩˜˗ˇ
VCC5 FB3
VCC5 VCC3
COMP3
VCC3_IN3
U1F SOP14-1_27
5 13
˖ˣ˨˲˩˜˗ˈ
12 5 ˩˥˘˚˲˩˜˗ˈ
I609
6.3V,10*12.5mm
V1P2_DUAL
v0.2
Title
PWR SEQ /VID /For AM2+

A3 AN52 V0.1
5 4 3 2 1
5VDUAL_USB
5VDUAL
F2
2 1
1.6A/9V/POLYSWITCH-LF
VCCUSB1
USB1A FP-USB Header
D D
U1 VCC1 (P)
USB_OC01* R110 USB1VCC
23 USB_OC01* 1 2 U5 VCC2 (P)
1
1K-0402-LF C178 5VDUAL_FP_USB
U4 GND1 (P)
x470PF U8 5VDUAL 1 R447
2 USB_OC89*
1K-0402-LF
GND2 (P) USB_OC89* 23
2
R111
2.2K-LF CE18 F5 R458
1000UF/YXG/6.3V/DIP-LF 2.2K-LF
2
2 1
1
H3 C450 C445
H3 1.6A/9V/POLYSWITCH-LF C444 x470PF
1
H4 H4
H5 x1000PF 0.1UF/16V/0402-LF
H5 C451
1
H6 H6
2
H4 H6 0.1UF/16V/0402-LF
L11
USB_0 1 2 USB_0P_C U7 FP-USB3
23 USB_0 USB0+ (B) U4 U8
USBV1 1 2 USBV1
U3 U7 VREG_USBn VREG_USBn+1
USB_0* 4 3 USB_0N_C U6 USB_8* 3 4 USB_9*
23 USB_0* USB0- (B) U2 U6 23 USB_8* USBPnN USBPn+1N USB_9* 23
USB_8 5 6 USB_9
L-S4P-2012
U1 U5 23 USB_8 USBPnP USBPn+1P USB_9 23
xChoke-USB U3 USBG1 7 8
USB1+ (B) GNDn GNDn+1
L12 9 NO PIN9 USB_OC 10
U2 H3 H5
USB_1 USB_1P_C USB1- (B) USB2P_HEADER5X2-LF
23 USB_1 1 2
C C
USB_1* 4 3 USB_1N_C RJ45/USB/Gb-LF
23 USB_1* COU22P-RJ45XLED
xChoke-USB FB4
USBGND
L-S4P-2012
1 2
30 OHM/100MHz/3A/0603-LF
USBGND
V0.2 UBB P&N SWAP
USB2 RJ45/USB-10/100-LF
L14 LAN1_1000- 1R186 22-LF
2
ORANGE LINK_1000 33
LAN1_100- 1R185 22-LF
2 LINK_100 33
L13 V1P8_DUAL_LAN
CG7 CG1 GLEDP14 GREEN
L10
USB2VCC U5 L10 FB8 x30 OHM/100MHz-3A-0603 V2P5_DUAL_LAN
USB_2* VCCP0 CG5 CG3 GLEDN13 GND DATA LOSS SOLUTION
23 USB_2* 1 2 U6 USBP0N
B U7 L9 MDI3- B
USBP0P VCCP0 VCCP1 GND TRD3- MDI3- 33
USB_2 4 3 U8 L8 MDI3+
23 USB_2 GNDP0 TRD3- TRD3+ C254 MDI3+ 33
1 2
L-S4P-2012 USBP0N USBP1N 6.8PF/NPO/50V-LF
xChoke-USB TRD3+ L7 MDI2-
TRD2- TRD2- MDI2- 33
L6 MDI2+
L9 USBP0P USBP1P TRD2+ TRD2+ C253 MDI2+ 33
USB2VCC U1 1 2
USB_3* VCCP1 TRD1- 6.8PF/NPO/50V-LF
MDI1-
23 USB_3* 1 2 U2 USBP1N TRD1- L5 MDI1- 33
U3 GNDP0 GNDP1 TRD1+ L4 MDI1+
USBP1P TRD0- TRD1+ C252 MDI1+ 33
USB_3 4 3 U4 1 2
23 USB_3 GNDP1 TRD0+ 6.8PF/NPO/50V-LF
L3 MDI0-
VCT TRD0- MDI0- 33
L2 MDI0+
xChoke-USB OLEDP12 TRD0+ C251 MDI0+ 33
5VDUAL_USB 1 2
L-S4P-2012 CG6 CG4 6.8PF/NPO/50V-LF
VCT L1 V2P5_DUAL_LAN
5VDUAL CG8 CG2 OLEDN11 FB9 30 OHM/100MHz/3A/0603-LF
F3 V1P8_DUAL_LAN
L12
2 1 VCCUSB2 R184 3VDUAL
YELLOW 220-LF
CG1
CG2
CG3
CG4
CG5
CG6
CG7
CG8
1.6A/9V/POLYSWITCH-LF L11 LAN_LED2 33
USB_OC23* 1K-0402-LF
1 R153 2
H1
H2
H3
H4
H5
H6
H7
23 USB_OC23* H8
R181 C237
2
0-0402-LF 0603x0.1UF
1
R159 CE22 C219 FB6 B5

2.2K-LF x470PF USB2GND 1 2
A 1000UF/YXG/6.3V/DIP-LF A
30 OHM/100MHz/3A/0603-LF
2
1
Title
LAN trace : 50:5:7:5:50 Dual LAN + USB CONN
B AN52 V0.1
5 4 3 2 1
5 4 3 2 1
10K-8P4R-LF
5 10K-8P4R-LF
6 10K-8P4R-LF
7 10K-8P4R-LF
VCC3
8
FP-USB Header
FLASH ROM 5VDUAL_FP_USB
4
3
2
1
RN24-4
RN24-3
RN24-2
RN24-1
D D
LPC_AD[3..0] 5VDUAL
21,32 LPC_AD[3..0]
LPC_AD0
LPC_AD1 R443 1K-0402-LF
1 2 USB_OC45* USB_OC45* 23
2
LPC_AD2
LPC_AD3 F4 R439
2.2K-LF
2 1
1
C453 C443
1.6A/9V/POLYSWITCH-LF C440 x470PF
VCC3 x1000PF 0.1UF/16V/0402-LF
U16 SST49LF004B C449
1
LPC_AD[3..0]
2
21,32 LPC_AD[3..0] 4MB FLASH
2
0.1UF/16V/0402-LF
LPC_AD0 13 LAD0 NC 1
LPC_AD1 14 LAD1 NC 22 R222 FP-USB1
LPC_AD2 15 LAD2 NC 26 4.7K-0402-LF USBV3 1 2 USBV3
LPC_AD3 USB_4* VREG_USBn VREG_USBn+1 USB_5*
17 LAD3 NC 27 23 USB_4* 3 USBPnN USBPn+1N 4 USB_5* 23
USB_4 5 6 USB_5
23 USB_4 USBPnP USBPn+1P USB_5 23
LPC_FRAME* 24 FLASH4MBIT_INIT USBG0
1
21,32 LPC_FRAME* 23 FRAME* INIT* 7 GNDn GNDn+1 8
9 NO PIN9 USB_OC 10
LPC_CLK_FLASH 31 18
21 LPC_CLK_FLASH LCLK RES
RES 19 VCC3 USB2P_HEADER5X2-LF
LPC_RST_FLASH* 2 20
21 LPC_RST_FLASH* RESET* RES
RES 21
VCC3 1R220 4.7K-0402-LF

2 FWH_WP* 7 WP* VDD 25 5VDUAL
VDD 32 5VDUAL_FP_USB
FWH_TBL* 8 1 R444
2 USB_OC67*
1K-0402-LF
3VDUAL TBL* USB_OC67* 23
1
2
GPI0 6
C R209 C277 F6 R438 C
29 MODE GPI1 5
4.7K-0402-LF 0.1UF/16V/0402-LF 2.2K-LF
28 4 2 1
D
GND GPI2
1
16 GND GPI3 3 C442 C447
Q44 1.6A/9V/POLYSWITCH-LF C441 x470PF
2
GPI4 30
23,36 ROM_EN G x1000PF 0.1UF/16V/0402-LF
2N7002/100mA-LF C448
2
1
S
2
ID0 12
ID1 11 0.1UF/16V/0402-LF
ID2 10
ID3 9 FP-USB2
USBV4 1 2 USBV4
PLCC32_4M_Socket_Black-LF USB_7* VREG_USBn VREG_USBn+1 USB_6*
23 USB_7* 3 USBPnN USBPn+1N 4 USB_6* 23
USB_7 5 6 USB_6
23 USB_7 USBPnP USBPn+1P USB_6 23
USBG2 7 8
GNDn GNDn+1
9 NO PIN9 USB_OC 10
USB2P_HEADER5X2-LF
2.7K-8P4R-LF
2.7K-8P4R-LF
2.7K-8P4R-LF
2.7K-8P4R-LF
5VDUAL_USB
5VDUAL
FB2 1812
PS/2 KM
1 2
30 OHM/100MHz/3A/0603-LF F1 1.6A/9V/POLYSWITCH-LF C2
L0603 FUSE1812 06030.1UF/16V/0402-LF
Y5V
6V
7
8
6
5
B 16V B
KM1
2
1
3
4
4 VCC1 (P)
5VPS2 10 VCC2 (P)
RN2-2
RN2-1
RN2-3
RN2-4
32 SIO_KBDATA
RN1-1 1 8 22-8P4R-LF SIOKBDATA
SIOKBCLK
1
5
KDAT (B)
KCLK (B)
FLOPPY CONNECTOR
2 NC1
6 NC2 VCC5
RN1-2 2 7 22-8P4R-LF R115 x1K
32 SIO_KBCLK
SIOMSDATA 7 5 4
SIOMSCLK MDAT (B) RN17-4 6
11 MCLK (B) 3 x1K
8 RN17-3 7 2 x1K VCC5
NC3 RN17-2 8
12 NC4 1 x1K
RN1-3 3 6 22-8P4R-LF RN17-1 x1K
32 SIO_MSDATA
3 FDC1
GND1 (P) 16 14
9 GND2 (P) 32 SIO_FD_DENSEL 2 DR0 (I) 2 1 GND1 (P) 1
11 9 5 3 4 NC1 GND2 (P) 3
RN1-4 4 5 22-8P4R-LF 13 6
32 SIO_MSCLK H1 7 1 DR1 (I)
47PF-8P4C-LF
47PF-8P4C-LF
47PF-8P4C-LF
47PF-8P4C-LF
14 H2 8 2 32 SIO_FD_INDEX* 8 INDEX# (O) GND4 (P) 7

15 H3 12 10 6 413 32 SIO_FDD_MTR0* 10 MORA# (I) GND5 (P) 9
16 H4 12 DSB# (I) GND6 (P) 11
8
CN8P4C
CN8P4C
CN8P4C CN8P4C
V0.2 footprint ->RN8P4R 17 H5 17 15 32 SIO_FDD_DS0* 14 DSA# (I) GND7 (P) 13
16 MORB# (I) GND8 (P) 15
A
KB/MS-LF 32 SIO_FDD_DIR* 18 17 A
CON2X6P-DIN DIR# (I) GND9 (P)
1
32 SIO_FDD_STEP* 20 STEP# (I) GND10 (P) 19

32 SIO_FDD_WDATA* 22 WD# (I) GND11 (P) 21
32 SIO_FDD_WGATE* 24 WE# (I) GND12 (P) 23
32 SIO_FDD_TRK0* 26 TRK0# (O) GND13 (P) 25
CN1-1
CN1-2
CN1-3
CN1-4
32 SIO_FDD_WRTPRT* 28 WP# (O) GND14 (P) 27

32 SIO_FDD_RDATA* 30 RD# (O) NC2 29
32 SIO_FDD_HDSEL* 32 HEAD# (I) GND15 (P) 31
34 33 Title
32 SIO_FDD_DSKCHG* DSKCH# (O) 34 33 NC3
Header-BOX-17X2P-LF K/M+FLASH+FDC+FP-USB
COB2X17P-2_54 Size Document Number Rev
A3 AN52 V0.1
5 4 3 2 1
IDE_PDD[15..0]
22 IDE_PDD[15..0]
IDE1 IDE1
COB2X20P-2_54-CP20
IDE_HDR
R158
7 7 8
1 2 ˜˗˘˲ˣ˗˗ˊ ˜˗˘˲ˣ˗˗ˊ
3 DD7 DD8 4 ˜˗˘˲ˣ˗˗ˋ
6 9
R0402 5% ˜˗˘˲ˣ˗˗ˉ 5 DD6 DD9 6 ˜˗˘˲ˣ˗˗ˌ
VCC3 VCC3 10K-0402-LF 5 10

˜˗˘˲ˣ˗˗ˈ 7 DD5 DD10 8 ˜˗˘˲ˣ˗˗˄˃
EMPTY 4 11
˜˗˘˲ˣ˗˗ˇ 9 DD4 DD11 10 ˜˗˘˲ˣ˗˗˄˄
3 12
R127
˜˗˘˲ˣ˗˗ˆ 11 DD3 DD12 12 ˜˗˘˲ˣ˗˗˄˅
2 13
R135 1 2 ˜˗˘˲ˣ˗˗˅
13 DD2 DD13 14 ˜˗˘˲ˣ˗˗˄ˆ
1 14
1 2 R0603 5% ˜˗˘˲ˣ˗˗˄ 15 DD1 DD14 16 ˜˗˘˲ˣ˗˗˄ˇ
x10K 0 15
R0402 5% ˜˗˘˲ˣ˗˗˃ 17 DD0 DD15 18 ˜˗˘˲ˣ˗˗˄ˈ
21 PCI_RST_IDE*
PCI_RST_IDE* 4.7K-0402-LF 1 RESET*
CSEL 28
IDE_DREQ_P 21 DMARQ
22 IDE_DREQ_P IDE_IOW_P*
22 IDE_IOW_P* 23 DIOW*
22 IDE_IOR_P*
IDE_IOR_P* 25 DIOR* PDIAG* 34 CABLE_DET_P
CABLE_DET_P 22
IDE_IORDY_P 27 IORDY DA2 36
22 IDE_IORDY_P IDE_DACK_P*
22 IDE_DACK_P* 29 DMACK* CS1* 38
2
IDE_INTR_P 31 INTRQ
22 IDE_INTR_P IDE_ADDR_P1
22 IDE_ADDR_P1 33 DA1 GND 2 R280
22 IDE_ADDR_P0
IDE_ADDR_P0 35 DA0 GND 19 15K-1%-LF
5%
22 IDE_CS1_P*
IDE_CS1_P* 37 CS0* GND 22 R0603
IDE_HDLED_P* 39 DASP* GND 24

36 IDE_HDLED_P*
GND 26
1
R140 R132 GND 30
1 2 1 2 32 NC GND 40
R0402 5% R0402 5%
4.7K-0402-LF 10K-0402-LF I267

5.6k ohm -> 4.7k ohm
22 IDE_CS3_P*
IDE_CS3_P*
22 IDE_ADDR_P2
IDE_ADDR_P2
VCC3
VCC3 W83627EHF AN02:
avoid EOS
VCC5
2
VCC5 VCC12 R464

R6 4.7K-0402-LF
2.2K-LF 4
CPU FAN
K
1
3 FAN2_AUX1 32
R5 D1 2
2.2K-LF LL4148/300MA-LF CPU Change & Clear CMOS: High
B1
1
CPUFAN1
Q3
1 2 3 4 AUXFAN1 AUX FAN1
A
R8 FAN-WAFER3X1-BROWN-LF
2
32 FANPWM_CPU0 E C 4 Control
PMBS3904-LF 220-LF TO SIO CASE OPEN* VBATCCMOS
3 SENSE
VCC3 VCC3 32 CASEOPEN* CASEOPEN* 2
R9 x0 VCC12 2 R172 0-0402-LF
W83627EHF (AN05): +12V
Pin115/116 could select output type by Register:
OD => stuff 0 ohm 1 23 INTRUDER* INTRUDER* R166
R4 GND VCC12 R441 R173 x0-0402-LF 10M-LF
Push-pull => stuff NPN,pull-high
D
4.7K-0402-LF 4.7K-0402-LF TO MCP51
Register default:OD (for H ver.)
FAN-WAFER4X1-Black-LF 1
4
COB1X4P-2_54-FANS 3 Q33 G CPU_GND
32 FAN1_CPU FAN4_AUX2 32 R180 CPU_GND 8
2 VBATCCMOS 2N7002/100mA-LF
FROM CPU GND PIN
S
1 2 1 1
VCC12
AUXFAN2 AUX FAN2 10M-LF
FAN-WAFER3X1-BROWN-LF C232
0.1UF/16V/0402-LF
2
R101
4.02K-1%-LF
VCC12
E
B Q26 VCC3
32 FANPWM_CPU1 C133
06030.1UF/16V/0402-LF 2SB1202/3A_TO252-LF
C
NC Y5V
32 FANPWM_SYS 16V R1
R102 4.7K-0402-LF
R105 R106 1K-1%-LF
8
x10K 10K-0402-LF 4
3 + 3 FAN3_SYS 32
1 2
2 - 1
U8A
LM358DR-LF SYSFAN1
FAN-WAFER3X1-Black-LF
4
1UF/16V-LF
R107
C153
0603
16V SYS FAN1
Y5V
R103 10K-1%-LF
4.02K-1%-LF CT2 CT1 V0.2 10UF/X5R->4.7UF
1206 1206
4.7UF/16V/1206-LF x10UF/16V/1206
Title
IDE 1/2 & FP-USB

A3 AN52 V0.1
5 4 3 2 1
SMB_SDA
SMB_SDA 26,27,28,30,32
SMB_SCL
SMB_SCL 26,27,28,30,32
3VDUAL ATXPWR1
3VDUAL VCC5SB VCC3 -12V VCC5 VCC12 VCC5SB VCC5SB
VCC5SB
2
K K 3.3V 1
3.3V
R65 13
x22K
5% -12V 2
3.3V
R0603 14
KA KA R64 GND
GND
3
2
2.2K-LF 15 <BOM>
D12 ATX_PS_ON*
1
16PS_ON* 5V
4 R88
C
10K-LF
D 5%
D
BAV99-LF D11 B GND
5
GND R0603
A BAV99-LF A Q21 17
PMBS3904-LF GND 5V
6
R66
1
18
1K-0402-LF 7
GND
GND
VCC5SB
Prevent ESD issue 19
8
PWR_OK
1 2 PWRGD_PS
1 NC PWRGD_PS 35,43
32,35 SIO_PSON* 20 R87 0-LF
5V 9
5VSB
R60 21
1
4.7K-0402-LF 5V 10
12V C112
X470PF
W83303D_PSOUT* 22
2 KN9-SLI issue:
5V 11
12V
(issue): LOW power supply supportability.
23 (Sol): Add loading to 5VSB
2
GND 12
3.3V
W83627DHF/ P01(Pin70): 24 VCC5SB

Test mode: pull-high
5V_dual
COP2X12P-ATXS
SUSLED 32
5VDUAL ATX_PWR_24 R93 R91
I272 x220-0805-no 220-0805-LF
R455 R456
x10K 2.2K-LF
IDE_HDLED_P* K2 R457
41 IDE_HDLED_P* 2
A VCC5 2.2K-LF
SATA_HDLED* K1 3VDUAL
22 SATA_HDLED* 1
C D19 5VDUAL 3VDUAL C
B
BAT54A-LF
1
R465
PMBS3904-LF
E C SUSLED1 147ohm
D
3VDUAL 220-LF ->330ohm R454 R451

Q72
Q75 220-LF 10K-LF
23,40 ROM_EN G 2N7002/100mA-LF FPIO1
W83627DHG Low active
R453
S
HDDLEDV SUSLEDV
2
1 HDD_LED+ 1 2 SP_LED+ 2
1K-0402-LF HDDLED* 3 4
REST_SW HDD_LED- SP_LED- FP_PWRSW
5 RESET SW- PWR_ON+ 6 1 2 SIO_PSIN* 32
23 FP_RESET* 1 2 FP_RESET*R 7 8 FP_PWRSW_N R450 220-LF R452 22-LF
R449 22-LF RESET SW+ PWR_ON-
9 NC
5VDUAL VCC5
C446 R460 68-0805-LF 13
D
D17 R462 68-0805-LF SPEAKER+5V PWRLEDV R446 Q71
15 SPEAKER GND1 PWR LED+ 16
K A 0.1UF/16V/0402-LF 17 150-1%-LF
32 WDTORST*
K
SPEAKER GND2
19 SPEAKER DRIVER19 PWR LED- 20 G 1 2 ROM_EN
D20 20 2N7002/100mA-LF
R445 22-LF
S
xLL4148/300MA-LF LL4148/300MA-LF
10*2PIN-LF CH2X10P-CUT5P
A
BUZZER
5VDUAL V0.1
B B
SPKR4 BUZZER
10K-0402-LF
BEEP pin (OD) state after system reset R463
W83627DHG=low
W83627EHF = high
C
W83627HF = Low
32 W_BEEP B Q73
PMBS3904-LF C452
220-LF R461
E
0.1UF/16V/0402-LF
SPEAKER STRAPS VCC3
ROM Table Select 2 1
C
R437 1K-0402-LF
SPEAKER R436 SPKR2 B Q74
0= USER 23,34 SPEAKER PMBS3904-LF
1= SAFE(Default) Buzzer Driver from chipset 2.2K-LF
1 2 C438
E
R435 x1K
0.1UF/16V/0402-LF
3VDUAL VBATCCMOS
5VDUAL VCC5
VBATCCMOS
D15
1
BAT54C-LF CCMOS1 CT100 CT101 C429 C430 R448 R114

+ + 0.1UF/16V/0402-LF0.1UF/16V/0402-LF
A
Battery-HOLDER-LF A2 2
HEADER3X1-Black-LF A
K VBATS 1 10UF/10V/0805-LF 10UF/10V/0805-LFX5R
C0402 C0402
X5R 220-LF 220-LF
6.3V 6.3V
1 2BATT_PWR_R A1 2 10% 10%
BATT_PWR 1
3
2
BAT1 R424 1K-0402-LF

A
D16
BATTERY=VBAT BAT54C-LF R432 LED2 LED1
A1 1 100-1%-LF
GND
K LED_RED-LF LED-Green-LF Title
23 RTC_RST*
A2 2
CMOS CLEAR JUMPER PWR CON/F-PNL/VBAT/SPKR

K

A3 AN52 V0.1
5 4 3 2 1
5 4 3 2 1
Other BOM (NO Foot-Print)

RED੡᧩‫׬ق‬ᆃࠫ೴
USB-PWR/FP-PWR JUMPER PS2-PWR JUMPER CCMOS JUMPER 1Cm
CCMOS1(1-2)1
PCIEx1
PCI
PCI
PCIEXP
D D
FP-PWR3(2-3)
4Cm 4.5Cm
JUMPER-2PIN-Black-LF
G-CARD
v0.2 BOM
FP-AUDIO JUMPER
(for AC97 only)
BIOS BIOS LABEL 14.318MHz XTAL WIRE M/B
(ref. the same (no ref.) (ref. the same
(NO-REF)LABEL1 Y4
with BIOS Socket) with X'TAL(32.768KHZ))
U16 LABEL
PhoenixBIOS
FP-AUDIO1(5-6) FP-AUDIO1(9-10) D686 BIOS
4MB PHOENIX 1998
FLASH JUMP_WIRE-LF
BIOS_LABEL1
LPC_FLASH-LF
(ref. the same
with Battery Socket)
BAT1 CPU RETENTION
C C
FIRMWARE
(no ref.) (no ref.) (no ref.) CUPON PSU & Derivatives CPU, DDR, NB, SB Platform
(single)
(NO-REF)FILE1 (NO-REF)FILE2 (NO-REF)CPU_RET1
VCC5
CUPON4
AC2005 FIRMWARE1 1 VBATCCMOS +3.3V_VBAT VCC5 +5V +1.8V_SUS VDDMEM
BIOS Firmware 1394 Firmware NC CUPON3 2
Data File Data File M2_Retention-LF
xHeader-2X1P
BIOS_FIRMWARE1 1394_FIRMWARE1 3V_BATTERY-LF
CUPON3 +1.2V_DUAL +0.9V_SUS VTTMEM
1 V1P2_DUAL VCC12 +12V
NC CUPON4 2
xHeader-2X1P
PWM Heat-Sink SB Heat-Sink +1.2V V1P2 VCC12A +12V_ATXP -12V -12V
CUPON
(differential)
N1
PWM_HSINK1 V2P5_DUAL_LAN +1.8V_DUAL V1P8_DUAL_LAN VCC3 +3.3V 5VDUAL +5V_DUAL
CUPON2
B B
1
NC CUPON1 2
NC CUPON1N 3 3VDUAL +3.3V_DUAL
v0.2 +1.2V_HT V1P2_LDT +V_CPU VCCP
Silent_OTES_HEATPIPE xHeader-3X1P
1
BOM
HSINK-61_4X40_2
CUPON1
1 +2.5V V2P5_VDDA
NC CUPON2 2 VCC5SB +5V_STBY
Heat_Sink/37.5*37.5*11mm-LF NC CUPON2N 3
3050-0051-88 3050-0052-30
HSINK-61_4X21_2 HSINK-61_4X21_2 xHeader-3X1P
49.4*21.2*25mm 49*39.2*35mm
(ex.KN8 PWM) (ex.F-AN9-32X v0.1 PWM)
9
RL2 RL1 RL5 RL4 RL3 RL6 RL7 RL19 RL12 RL25 M10
1 5
2 6 1 7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 7 2 4
4 8
M11 M12 M4
xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xM8_3X4G M7
xM8_3X4G 9 9 9
RL18 RL8 RL23 RL20 RL14 RL10 RL13 RL16 M3 M6 1 1 1
1 5 1 5 v0.2
A 2 6 2 6 A
1 1 1 1 1 1 1 1 3 1 7 3 1 7 xM8_3X4G xM8_3X4G xM8_3X4G
1 1 1 1 1 1 1 1
4 8 4 8
xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xM8_3X4G xM8_3X4G
v0.2
RL21 RL11 RL17 RL9 RL22 RL15 RL26 RL24 M1 V0.1 M8 M9 M2 M5
1 5 1 5 1 5 1 5 1 5
2 6 2 6 2 6 2 6 2 6 Title
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3
4
1 7
8
3
4
1 7
8
3
4
1 7
8
3
4
1 7
8
3
4
1 7
8 MOUNTING HOLES
xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xMarkin-R xM8_3X4G xM8_3X4G xM8_3X4G xM8_3X4G xM8_3X4G USBGND A3 AN52 V0.1
GND_AUDIO Date: Thursday, March 08, 2007 Sheet 42 of 42
5 4 3 2 1

ABIT AN52 [NFORCE MCP68] SOCKETAM2 V.0.1

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ABIT AN52 [NFORCE MCP68] SOCKETAM2 V.0.1

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8 7 6 5 4 3 2 1

6 PCI DEVICE TABLE / VID TABLE

47 MCP68 CORE-AUX-HT-VREGS COVER

DDRII SDRAM CONN 2

ATA 133 HDMI

INTEGRATED SATA CONTROLLERS (X2) X12 USB2 BACK PANEL CONN

FRONT PANEL HDR

USB2 PORTS 6-7

AM2 SOCKET 940

PE_RESET* HT MCP RST* HT_MCP_RST*

HT MCP PWRGD HT_MCP_PWRGD

PS ON SLP_S3* SLP S3* PCI RST0* PCIRST_SLOT1*

AM2 SOCKET 940

LPC_CLK0 PCI SLOT 1

32.0 KHZ RTC_XTAL

S5# MEMVLD MCP55_PWRGD HT_VLD 11

S5# 5VDRV LR1_DRV

POWER SEQ MAP

VCC12 VCC12 PCI/3 FAN/4 PCIEx16/1 PCIEx1/2

(3.38A) W83320 V1P2 MCP65S

(0.23A) W83304CG V1P2_DUAL MCP65S

V0.1 220PF ->2200PF

18 HTCPU_UP[15..0] HTCPU_UP[15..0] HTCPU_DWN[15..0] HTCPU_DWN[15..0] 18

18 HTCPU_UP*[15..0] HTCPU_UP*[15..0] HTCPU_DWN*[15..0] HTCPU_DWN*[15..0] 18

Layout add Text 2 ˛˧˖ˣ˨˲˨ˣʽ˅ L2 HT_RXD<2>* HT_TXD<2>* AE1 ˛˧˖ˣ˨˲˗˪ˡʽ˅ 2

HTCPU_UPCLK0 N3 HT_RXCLK<0> HT_TXCLK<0> AD1 HTCPU_DWNCLK0

HTCPU_UPCNTL0 U1 HT_RXCTL<0> HT_TXCTL<0> W2 HTCPU_DWNCNTL0

C PLACE WITHIN 1 INCH

CPU_TMS AL9 TMS TEST29 C11 FBCLKOUT

TP_CPU_TEST16 E7 AH8 TP_CPU_TEST23

TP_CPU_TEST14 C5 AL8 CPU_TEST21 1 8

B E5 TEST7 TEST28 J10 B

RN22-2 2 7 330-8P4R-LF AE25 RSVD RSVD G4

R50 R49 I235

14 ˠ˘ˠ˲˕˲˗˔˧˔˄ˇ MB_DATA<14> MB0_CLK<1>

2ˠ˘ˠ˲˕˲˔˗˗˅U29 MB_ADD<2> MB_CKE<1> M31 MEM_B1_CKE

AJ11 E12 MEM_VTT_SENSE

V0.1 39.2-1%ohm ->40.2-1%ohm

AC17 VSS VSS L7 B5 VDD VDD U10

AH18 VSS VSS P14 K7 VDD VDD AA22

D18 VSS VSS V2 AB24 VDDIO VDDIO P28

VSS VSS VDDIO

F24 W17 P26

F26 VSS VSS W19

H16 VSS VSS Y20

D VDDMEM V1P2 V1P2_LDT VTTMEM D

VTT_P VTT_N VTT_VREF

DIMM 1 CLOSEST DIMM TO CPU

DIMM 2 CHANNEL "B" UPPER 64 BITS

DIMM 3 CHANNEL "A" LOWER 64 BITS

DIMM 4 CHANNEL "B" UPPER 64 BITS

7 HTCPU_DWN*[15..0] HTCPU_DWN*[15..0] HTCPU_UP*[15..0] HTCPU_UP*[15..0] 7

11 ˛˧˖ˣ˨˲˗˪ˡʽ˄˄AD12 HT_MCP_RXD11_N HT_MCP_TXD11_N AF20 11

12 ˛˧˖ˣ˨˲˗˪ˡʽ˄˅AC11 HT_MCP_RXD12_N HT_MCP_TXD12_N AE18 12

13 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˆ AB12 HT_MCP_RXD13_N HT_MCP_TXD13_N AG18 13

14 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˇAG14 HT_MCP_RXD14_N HT_MCP_TXD14_N AB16 14

15 ˛˧˖ˣ˨˲˗˪ˡʽ˄ˈAD14 HT_MCP_RXD15_N HT_MCP_TXD15_N AD16 15

7 HTCPU_DWNCLK0 HTCPU_DWNCLK0 AJ11 HT_MCP_RX_CLK0_P HT_MCP_TX_CLK0_P AH20 HTCPU_UPCLK0 HTCPU_UPCLK0 7

18 HTCPU_UP[15..0] HTCPU_UP[15..0] HTCPU_DWN[15..0] HTCPU_DWN[15..0] 18

7 HTCPU_DWN[15..0] HTCPU_DWN[15..0] HTCPU_UP[15..0] HTCPU_UP[15..0] 7

28,30 PCI_C/BE[3..0] PCI_C/BE[3..0]

USB_OC3/GPIO28/MGPIO1P5 USB_OC67 USB_OC67* 40

USB_OC4/GPIO29 P6 USB_OC98 USB_OC89* 41

R482 0-0402-LF EXT_SMI/GPIO32 F3 EXTSMI RN30-4 4 5 2.7K-8P4R-LF

R471 x33-LF SPI_DI_R HOLD(I) SPI_HOLD R469 x0-0402-LF