Hierarchical Paging

(Multi-levels paging)
(forward paging)
(paging the page table)

page table size * (2)

Hashed Page Tables

Inverted Page Tables

Hierarchical Paging

the page table contiguously in main memory

into smaller pieces.) the page table
the page table
#E: 49E*WEx( divide
itself is also paged 4 MB
MAX 17
BIbI : #*F3/(two level paging. Epage size = 4
KB. th page number (P)LiF# 20
(RB3x# 32-bit logical address space Flsingle-level paging ffi

F 4MB
#1RREXtwo level paging, ainoretet.weonyliliecd.eoomypmeano.ns.o.t.h.e
is an index into the outer page table and
Level-2 paging
inner page table. Level-1 paging
Alilentry #$Atg.E offset
> Level-1 page table pl
p2

Level-2 page table titit!• moleve-2 page 10 bits

12 bits

no.
Table #lentry #*40 Eframe
10 bits
 N-1enel
A two-level page-table scheme
Logical address
Level-2 offset
Level-1

Physical
memory

Physical address
Outer-page
table 2 inner-page
table

in mem.

#*Ri: #t#*hierarchical paging, "E&XB12MMGlTHY INk A HXpagetable,sotheEMATwill be very long.

#Bl : if we use the M levels paging scheme, and assume the TLB hit ratio is P, the EMAT will be

P(TLB time +memory access time)+(1-P)(TLB time+ (M+1)*memory access time)

Hashed page table (* *$)HI)

overflow ( page table if Elentry &L* linked list H-hash address AJ

Node structure in a link list @L&EEd: (1) the virtual page number, (2) the value
of the mapped page frame, and (3) a pointer to the next element in the linked list.

En tE#A*I**32 bits #glogical address. (address spaces larger than 32

bits is to use a hashed page table, with the hash value being the virtual page
number)

18
 Hashing page table Em
physical
Logical address
address
Physical
memory

Hash
15 Nil
function

e.g.

H(p)=p%10 Linear search until the page no. is founded

Hash

Page
Table

Cont.

£1H164 bits logical address 1 5 fhash page table L EtelE ( A variation of

this scheme that is useful for 64-bit address spaces ) .
Clustered page tables
P which are similar to hashed page tables
>
hash table # Elentry &*** pages(i.e. frames) (refers to several frames 6l0
16/E) TiTF-frame. Miit a single page-table entry can store the mappings for
multiple physical-page frames.
 Inverted Page Tables 反轉分⾴表
作法 以physical memory 為記錄對象 如果實際記憶體有 N 個frames 則反轉分真表就有N
個noentry 每⼀個entry frame
紀錄是哪⼀個則標註
process 的哪⼀個
availabte
page 佔⽤ 以 process id page
整 one page table is in the system ⽽不是傳統的⼀個
process ⼀張分⾴表 故有效隆低所需分⾴表空間
Logical address

TA Poye 22 Physical

search
R Peoe 2
PA PMt2
pid
⼲含 memory

H Physical address
0Vaihble

Inverted page table

Cont

優點 the amount of memory needed to store each page table

缺點
需要⼀ 比對反轉分⾴表每⼀個entry內容直到找到符合的 process ID page no 為⽌ 增加⼤量
搜尋時間

花 Rvetted peae tables無法⽀楼 Shared menory 匿擇

MvuMA

队A
1 反躬分五表

IA Plep L ⼀2
KEe PAeL

PIP 就同阿可能夫⼦
V r 以
 Gppmenndoeaahnme mEa Rm
fin a
mdt t aces mem, Wirite tficte mey-atos ine ( Ehn Na
08s ld)24hs ( )
o ( + ) + b (o 4x 2) * 2 )
7

mAaremati
cntries me forbas the6Mpagewital
needed abieses
table? a s a damwg Aps a2X Ho mmyz 5

po 1
V"N R PUe LTwand: ▇ rty ▇ b 1 ttul
49 5 4

ferz 2It * 4- 2'1 =5 b

o pa) Given a compuiler syatem with a vintaAsddress, let the system be only
byte-addressable. Assume that every page is of 32KB with 4 bytes per page entry in the page
table. Suppose that the frame nu needs byes to stor
ore. Please answer the following

ese ) t Jes
eel pa PT . - oefin
(4 konel )
a. (S pts) Suppose that we have multi-level paging, How many leyeks do we have in muli-level
paging?

(S pts) Suppose that TLB is adopted for paging, where the

Lat the memory access time and TLB access time be 1O0ns and IOns, respectively. When the
TLB hit ratio is 80%, what is the effective memnory access time"?
(110
( 61
bi (ir ) + ,2Xt 5 y )
nkey)e 4 to2 a /9
Me $ite = 8
an ony &) 2 en*
= led n hit ki
f 4 lodl 1
21
 ANS:

4 bytes
page Table entrim

20 - 2" Tentry

½. 4- Level payry

b,

(4%) Consider a system with the

virtual
physical address of 28 memory address of
32 bits,
bits. The page and the
In size, size 2KB. Each page
Is
table entry is 4
a) How bytes
many bits are in the
page offset
(b) What
is the total pagetable portion of the virtual address?
size?
(0)
VPN-
21 11
Ans3l
(b)

&kB
Assume a
program
scenario how each has just referenced an
ofthe address in virtual
why.)
/. ILB
following canoccur: memory.
(If a Describe a
miss withno scenario cannot
TLBhitandno page fault(3%) occur, explain
pagefoult b.MLB
(290) missand
pagefault
dTLBhitandpage (3%)
fault(2%)
 wa aetlnineeeceeabrncvtermd e the) ate comen
arr
o adines mure wih TK per pae mnd * hyesper pege titble anitey the ta
)

0) I
t B,bui ha in cache and puge GaAeslnbr mn
s possible to mis in o * 2 4Ba
p106
Ab

Wa:
aeede ecteeinghat bheck a umcae was mAe E
( Ya multilevelmins nt na 2ws tsniusoa msa
page number.page tables, ▇bie eentry contains a frame umber.
aiah penalty
miss will be. tabies, the ore vels a pNge table has, the nighenthe T ▇
aaitileve
08 a
AC

Given a computer system with a 2-bit virtual address, KB pages, and 8 pe

age entryof a page table. Suppose that the number of bits of physical addre
is 48, and the system is byte-addressable. If multiple-level paging is implemented,
please answer the following questior
a)(4 )What is the maximum number of (physical page firames.in the system
where each page frame is the container to store the data of one (virtual) page?
What is the maximum number of pages for a process?
( )(5 ) Suppo level paging is adopted. How many leve s do we
need?
A0
A ;
A
wne #

6b

1PT 4 b
- Y1▇ t- 2

F n
23
 Process logical memory).=-fEsegment Bo4t.•asAlithi.BFlogical
viewpoint.
> PIEd : code segment, data segment, stack segment, etc.

Logical address ‡#R s (segment no) id d (segment offset)E fik _

Logical address rkphysical addresstlia

g> Check d<limit? Ifing, this will cause the trap of illegal memory address
(> Otherwise, it is legal. MMU adds the base and d to form the physical address

scheme
Logical address

CPU

Physical • 5vo
Trap
No limt YES address

Physical
memory
Process limit base
D
3300
7500

730 k 75uo

3300

Segment table
 pactice (度の 計#)
Segment No, Length
Given the following logical address くs, d,
6ー

1219
2300
700
14
Calculate the physical address based on the left-side segment table?
(1)<0,600>
(2)<1,33>
90 100 (3) く 2,80>
(4) く 3,580s
1327 580

1952 96 0 811 (d=い oく fwt :103

@年う5フ 1 不る城
0) ルく p f ォ 8U=

0 邦メ 5 み合志

13. (5 pts.) Consider the following segment table:

Segment Base Length
L よフ UUy

Z5UU Jh

M01UU

1327 580
4 1952 96
Mat are the physical addresses reference in the following item wil cause an illegal)
eddress trap toOs for the following logical addresses?
M 0,830
( -,JU

の 3,350
旭 4,112
(105中央⼯作業系研興計算機組釧
AcE
比較表 中論 segment
各段⼤⼩不⼀定相同
page
各 size ⼤⼩相同 採⽤ viewpoint
⼤⼩
觀點
採⽤ viewpoint 有 Y99 ⾞强
沒有
沒有
外部碎裂
YES 容易實施
以双装员 以er 看法⼀彩
有
内部碎裂

Support
YES 但是比較困難實施
memory
sharing and
protection
比較 d limit
EMAT 比較短
YES
Need YES
hardware
support

table Page table 紀錄frame no

Segment table 紀錄 base and limit

Paged segment memory management 補充

段再分⾴

Physical
好處 memory 是由⼀組frames 所組成
1沒有外部碎裂
缺點
1 Table 數⽬太多
sharing and protection 的好處
2 EMAT更長
③4 會有內部碎裂
也是需要額外硬體⽀援
Paged segment memory management
Logical address
It page size Frune
d
CPU

Physical
No YES
Trap address

Physical
memory
Page no Frame
limit Page no
table frtt

Segment table