TI PLC (Flex) Development Kit User Guide

Version 0.2

August 30, 2010

Copyright  Texas Instruments Incorporated, 2009-2010

The information and/or drawings set forth in this document and all rights in and to inventions disclosed
herein and patents which might be granted thereon disclosing or employing the materials, methods,
techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of
information or drawings shall be made to any other person or organization without the prior consent of
Texas Instruments.

Texas Instruments Proprietary Information

Table of Contents
Table of Contents.............................................................................. 2
1.0 TI PLC Development Kit Overview............................................ 4
1.1 Features....................................................................................................................................... 4

1.2 PLC Development Kit Components ............................................................................................... 5

1.3 System Installation Requirements ................................................................................................ 6

1.4 Software Installation .................................................................................................................... 6

1.5 Hardware Setup ........................................................................................................................... 7

1.3.1 PLC Point-to-Point HW Setup........................................................................................................ 8

1.3.1 PLC-DK Default Jumper/Connector Settings.................................................................................. 8

2.0 Using Demo Application ......................................................... 10

2.1 User Interface ............................................................................................................................ 10

2.2 Port Set Up................................................................................................................................. 11

2.3 System Configuration ................................................................................................................. 11

2.4 Getting System Information ....................................................................................................... 15

2.5 Control Set Up............................................................................................................................ 15

2.6 Configuring PHY Parameters....................................................................................................... 16

2.7 Get/Set MAC PIB ........................................................................................................................ 18

2.8 Get PHY PIB................................................................................................................................ 19

2.9 Configuring Connection Parameters ........................................................................................... 20

2.10 Selecting Frequency Band .......................................................................................................... 20

2.11 Testing PHY Performance ........................................................................................................... 24

2.12 Sending and Receiving Message ................................................................................................. 25

2.13 Sending and Receiving File ......................................................................................................... 26

2.14 Flash Firmware........................................................................................................................... 29

3.0 System Trouble Shoot ............................................................ 31

3.1 Trouble shoot for squirt ............................................................................................................. 31

2
 3.2 Trouble shoot for USB to Serial Dongle Communications............................................................ 31

3.3 Trouble shoot for PLC LQM Diagnostic Tool to Device Communications...................................... 32

APPENDIX A – Code Composer Studio Installation and Setup......... 33

APPENDIX B - PLC-DK Hardware Resource Usages......................... 34
APPENDIX C – Logger Setup ........................................................... 37
APPENDIX D – PHY Example Project............................................... 40
APPENDIX E – SCI Example Project ................................................ 44

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1.0 TI PLC Development Kit Overview
1.1 Features

Figure 1 TI PLC Development Kit

The TI PLC Development Kit for FLEX contains the following main components and supported features:

 DSP control card with Texas Instruments F28335 microcontroller

 AFE daughter card with Texas Instrument operational amplifier OPA564 and
programmable gain amplifier PGA112. Note that default Kit provides AFE daughter card for
Cenelec A band. Special AFE daughter card is needed for other frequency bands.

 Operating frequency range supporting Sub-10KHz band, CENELEC A/B/C/D and FCC band
 Selectable frequency bands with BW of 3 kHz, 12 kHz or 24 kHz

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  Data rates up to 64 kbps
 Transmission with OFDM and FEC
 Number of used data carriers is 24
 Differential Phase modulation (DBPSK/DQPSK/D8PSK)
 ROBO mode provides Repetition code with DBPSK+FEC
 Convolutional encoder/Viterbi decoder
 Bit interleaving for noise effect reduction
 CRC8 in headers and CRC32 in data for error detection
 Data randomization for uniform power distribution
 Automatic gain control
 Zero-crossing detection
 Supports FLEXOFDM PHY, PRIME MAC, IEC61334 -4-32 LLC
 RS-232 interface for diagnostic port interface
 Serial interface for host data port interface: UART, SPI, etc.
 LEDs and test points for firmware and hardware debug
 USB/JTAG for custom firmware download

1.2 PLC Development Kit Components

The development kit includes the following hardware:
 Two sets of development board, each set contains:
o 1 F28335 MCU control card: flashed with FLEX PLC image of: flex_iec432_flash.out
o 1 docking station
o 1 AFE board

The development kit includes the following software:

 FLEX PLC Binaries
o FLEX IEC61334-4-32 project binary image
(flex_iec432_flash.out)
(flex_iec432_flash.srec)
(flex_iec432_flash.hex)

o Firmware upgrade binary image (only used for HW platforms that does not have pre-flashed
image)
(flash_upgrade.out)

 FLEX PLC Software Libraries

o FLEX PHY Library: phy_flex.lib
o PRIME MAC Library: prime_mac.lib
o IEC61334-4-32 LLC Library: iec432_llc.lib
o FLEX AFE Library: hal_afe.lib

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 o F28335 Support libraries: csl.lib, uart.lib

 PC Software/GUI
o TI PLC Quality Monitor GUI

 Example projects:
o FLEX PHY projects: example of using PHY lib only
o SCI/UART project: example of configuring SCI transmit and receive

The development kit includes the following documentations:

 SW API Specifications
o PHY API Spec
o MAC API Spec
o CL IEC432/LLC API Spec
o Host Message Protocol Spec

 HW documentations
o AFE daughter card schematics and Gerber files
o Docking board schematics and Gerber files
o BOM

1.3 System Installation Requirements

To install SW package on PC to communicate with the PLC Development Kit, your computer must meet the
following minimum requirements:
 Microsoft® Windows® XP (SP2) or Windows 2000 (SP4)
 Pentium® IV 1GHz processor
 128 MB RAM (256MB RAM recommended)
 USB 2.0 interface (If using JTAG debug interface)
 CD-ROM drive
 Screen resolution 1024x768 (or better)
 1MB of free space on the HDD for the applications and more for LOG files.

1.4 Software Installation

To install the FLEX PLC software package, run the PLC tool installer “PLC_Host_Installer.msi” that is included
in the CD.
The FLEX PLC software package includes the followings:
1. Software documentation and API specification (FLEX PHY/Prime MAC/Prime CL/IEC432 LLC/Host
Message Protocol) under “doc” directory
2. Hardware documents (Docking board and AFE daughter card) under “HW” directory
3. Software binaries under “SW” directory:

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 a. flex_iec432_flash.out – This image supports IEC61334-4-32 LLC and convergence layer stack
on top of Prime MAC and FLEX PHY operations. It demonstrates the followings:
i. Point to point and point to multi-points operation: Demonstration of PLC device
PHY layer performance, file transfer and message transmission through FLEX
PHY/Prime MAC/PRIME IEC432-CL/IEC432-LLC without a Base Node. This is to be
run with the PLC Quality Monitor (PQM) PC tool.
4. Example projects under “SW” directory zip files
a. FLEX PHY example project – Demonstrates the usage of PHY library API
b. SCI example project – Demonstrate SCI operation in loopback mode.
5. Tool
a. PLC host tool installer – This installs PLC eMeter GUI, “iprawput” application and
“HostAppEmu” application

1.5 Hardware Setup

The following shows steps of how to setup PLC-DK hardware (make sure system is un-powered):
1. Insert the F28335 control card in connector J1 on the docking station
2. Insert the AFE card on the docking board. Connector J2 (AFE card) to connector J4 (docking station).
Connector J3 (AFE card) to J10 (docking station)
3. Connect 12V DC power supply to 12V power jack (make sure the board power supply switch is OFF)
4. Connect power cables to connector TB1.
5. Connect the serial cable to the serial connector on the docking station. Note that a NULL modem
cable (TX/RX cross connected) is used between host PC UART port and the PLC-DK. Note that for
Dock HW Rev-C, a ribbon cable is provided for serial connection and for Dock HW Rev-D, null
modem serial cable should be used.
6. Turn on the board power supply switch (ON/OFF Switch)
7. Check that the LED on the F28335 control card is blinking

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1.3.1 PLC Point-to-Point HW Setup

Host PC
Null modem cable

power line
Null modem cable

Figure 2 PLC-DK Point-to-Point HW Setup

The PLC-DK can be used to demonstrate point-to-point or point-to-multipoint communication over power
line. This is to be used with PLC Quality Monitor GUI Tools to test PHY/MAC operability and send data
between the two boards over the power line media1. It requires 2 PCs, and 2 null modem cables.
If the host PC can be configured to use two serial ports, then the demo setup can be ran on a single PC,
using a different serial port to communicate with each board.

1.3.1 PLC-DK Default Jumper/Connector Settings

The PLC Development Kit provided is configured with the default jumper/connector positions. The following
three tables describe the connector/jumper name, descriptions, default positions and other options if
available.

AFE
Connector/Jumper Descriptions Default Position

1
Note that the DSP control cards are pre-loaded with “Flex_iec432_flash.out” and ready to be used.

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 J2 PLC Docking Board Connector
J3 PLC Docking Board Connector
JP5 RX Path Close
Table 1 PLC AFE Connector/Jumper

PLC Dock
Connector/Jumper Descriptions Default Position Options
J1 DSP Control Card Connector
J2 SCI-A Connector
Open Boot from Flash
J3 Boot Options Open 1-2 Boot from SPI-A
2-3 Boot from SCI-A
Transformer T2 Open T2 Not Used
J4 Close
Selection Close T2 Is Used
ECAP Channel 1-2 ECAP1
J5 2-3
Selection 2-3 ECAP3
J6 SCI-C Connector
2 GPIO1
J7 GPIO Test Pin Open 4 GPIO3
6 GPIO4
Transformer T1 Open T1 Not Used
J8 Open
Selection Close T1 Is Used
1-2 SCI-B to USB
J11, J12 SCI-B, SCI-C Selection Open 2-3 SCI-B to J6
3-4 SCI-C to J6
SPI/McBSP to PGA 1-2 SPI to PGA
J13, J14, J15, J16 1-2
Selection 3-4 McBSP to PGA
Open Mains Not Connected
J10, J17 AC Mains Close
Close Mains Connected
M3 AFE Daughter Card Connector
JP1 Power Supply Connector
TB1 Power Line Connector
Table 2 PLC Dock Connector/Jumper

USB/JTAG/SCI
Macro Descriptions Default Position Options
J1 Boot Selection Open Open Boot from Flash
Close Boot from SCI-A
J2 JTAG Connector
J3 N/A Open Connected to GPIO34
USB/SCI-B Open SCI-B Not Connected to USB
J4 Close
Selection Close SCI-B Connected to USB
Table 3 PLC USB/JTAG/SCI Macro

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2.0 Using Demo Application
The PLC Quality Monitor GUI diagnostic tool - PQM is the window to the PLC-DK user to provide graphical
displays, system information, PHY and MAC parameter configurations and statistics.

2.1 User Interface

The PLC quality monitor consists of the followings:

 Main Menu – All operations are initiated from the main menu with toolbars and buttons.

 Graphical Displays
o PHY Parameters – PHY parameters configuration (see details below)
o RSSI graph – Plot is in dBuV. Note this is limited between 70 dBuV and 98 dBuV.
o SNR graph – Plot is in dB.

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 o Bit Error Rate graph – Plots of PHY layer bit error rate, one line for each MCS (only
applicable to PHY test mode operation)
o Packet Error Rate graph – Plots of PHY layer packet error rate, one line for each MCS
 PHY statistics – This panel provides statistics in the physical link.

 MAC statistics – This panel provides statistics in the MAC and CL layers

 Transfer statistics – This panel provides statistics when file transfer is in operation.

 System Information – This panel provides system version information and PHY/MAC/CL IPv4/LLC
configurations.

2.2 Port Set Up

The Port Setup option provides a way to configure the serial port (Menu->Options->Port Setup). You may
configure the baud, data bits, parity, stop bits and handshaking mode. There are 2 serial ports on the
hardware; both ports baud rate should be set to 57600 bps as shown in the figure below.

Note that the only selection that should be changed is the port number and baud rate (in red box above).
The rest of the port settings should not be modified for PLC device compatibility.

2.3 System Configuration

The system configuration provides a way to configure the PLC device (Menu -> Options -> Set System
Config).

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The following describes the configuration settings:

 Application PIB Attributes

o AppFwVersion – Textual description of firmware version running on device
o AppVendorId - Vendor identifier.
o AppProductId - Vendor assigned unique identifier for specific product.
 Hardware Revision – Docking board revision ID (default: Rev.D)
 Firmware Version – Firmware version ID
 Device Type – The current type of the device
o FLEX IEC-432 LLC Convergence – FLEX PHY with IEC432-LLC convergence layer
 Device Mode
o Point-to-Point (This is the only supported mode)– using the end-to-end setup between the
two PLC devices. This mode interfaces with the eMeter GUI performing its functions such as
PHY testing, File Transfer, Message Transfer, etc.
 Use Message Header RPY Bit As Flow Control

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 o When selected or enabled, the PLC device will set message header RPY bit to 1 during
DATA_TRANSFER message used for Data.Indicate (Rx Data Path) to provide flow control for
host device. (Host has to send an ACK to PLC before next DATA_TRANSFER.Indicate will be
sent to host).
 Serial Ports
o Data port
 The Data Port is the serial port the PLC device used for host and PLC communication
following “plcSUITE host message protocol”. This can be either SCI-A or SCI-B on
Rev C. hardware and newer. This port is used by a host application (hostAPPEMU)
to communicate with the PLC device.
o Diagnostic port
 The Diagnostic Port is the serial port the PLC device uses to transfer diagnostic
messages to the PLC Quality Monitor or Logger Tools. This can be either SCI-A or
SCI-B on Rev C. hardware and newer. If using IEC432/LLC, the Diagnostic port can
be shared with Data port if required, however, if using IPv4, the Data port and
Diagnostic port must be different and cannot be shared.

Note that SCI-B shall not be selected for docking board HW prior to Revision C

 System
o Serial Number
 The hexadecimal serial number of the PLC device, entered as ####-####-####,
where # can be 0-9, a-f.
o EUI address
 The hexadecimal EUI-48 of the PLC device, entered as ##:##:##:##:##:##, where #
can be 0-9, a-f.
 PHY
o FLEX – FLEX PHY normal mode
o FLEX ROBO – FLEX PHY robust mode
 MAC
o Default ARQ enabled: ARQ is enabled by default
o Default PAC enabled: Packet Aggregation disabled by default
o Rx Max Hold PPDU: maximum number of PPDUs Rx MAC can hold
o Maximum number of connection: default maximum number of simultaneous connections
o Maximum connection queue length: default maximum queue sizes
o Default Security profile
 IEC61334-4-32 LLC
o Src LSAP – The local LSAP involved in the data unit transmission
o Default destination LSAP
 The default destination LSAP used by the eAppEMU when in eAppEMU interfaces
with IEC61334-4-32 LLC
o Default destination MAC address

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  The default destination node address used by the eAppEMU when in eAppEMU
interfaces with IEC61334-4-32 LLC

The following example illustrates how to change the device type from “IEC432-LLC” to “Point-to-Point”:

1. Menu -> Options -> Set System Config

2. Pull down menu from Device Type
3. Select Point to Point
4. Click OK

The following window will pop up and selecting “YES” will reset the PLC device and new device mode will be
in effect.

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2.4 Getting System Information
The Get System Info option (Menu->Options->Get System Info) retrieves the current System Information
values from the PLC-DK. These are represented in the System Information view. These values may be set
using the Set System Config (Menu->Options->Set System Config).

2.5 Control Set Up

The Control Setup option (Menu->Options->Control Set up) allows the followings:
 Channel status update - Select “Enable Synchronization Parameters” check box for status
display in statistic window.
 Link quality report update - Select “Enable Link Quality Report” check box for RSSI/SNR/BER/PER
display in the statistics window.
 MAC statistic update – Select “Enable MAC statistics” check box for MAC statistics display in
MAC statistic window.
 Update period in seconds – Enter duration between statistics updates.

15
Note that if both transmit and receive PLC LQM tool is running on the same PC, it is
recommended to use a larger update periods (e.g. 3 seconds) to avoid too many
traffic between device and host PC.

2.6 Configuring PHY Parameters

The PHY parameters configuration (Menu->Options->PHY parameters) is used for configuring the PHY
transmitter (Red Box below) and receiver parameters (Green Box below).

Note that the enabling of PHY “Test Mode” on the Transmit or Receive would require the device mode to be
“Point to Point”. The following window will be prompted if device is not already in “Point to Point”. Click
“Yes” to reset the device and “Point to Point” mode will be set. The PHY test can now be continued,

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The following describes the PHY TX parameters that can be configured :
 ROBO – PHY Robust mode (non-FLEX standard)
 PRM – This is not supported. Do not select.
 Modulation – DBPSK, DQPSK, D8PSK. Note this field is ignored if sweep MCS is selected. If ROBO
mode is selected, then DBPSK + 1/4 repetition or DBPS + 1/8 repetition can be selected.
 FEC - ON or OFF. Note this field is ignored if sweep MCS is selected. If ROBO mode is selected,
this field is not valid since FEC is always on.
 Level – Transmit Level
(Note that the maximum transmit level should be set to 2 for AFE HW prior to Revision C)
0 : Maximum Output Level (MOL)
1 : MOL – 3dB
2 : MOL – 6dB
3 : MOL – 9dB
4 : MOL – 12dB
5 : MOL – 15dB
6 : MOL – 18dB
7 : MOL – 21dB

The following describes the PHY TX parameters that can be configured for PHY Tx test mode only:
 Test Mode - When enabled, it configures the transmitter in test mode and it transmits fixed
data pattern (selected in data pattern box) for BER testing
 Sweep MCS – When enabled, test will sweep through all MCS for the packets transmitted. The
order of MCS used is DBPSK, DQPSK, D8PSK, DBPSK+FEC, DQPSK+FEC and D8PSK+FEC.
 Sweep PPDU length - When enabled, test will sweep through all valid PPDU length in increasing
order for the MCS used.
 Continuous – When enabled, test will continuously transmit PPDUs as specified. When disabled,
test will transmit the “Number of PPDUs per setting” (see below) as specified and stop. .
 Data Pattern – When PHY test mode is enabled, data pattern for the packet payload to be
transmitted can be selected. The following data patterns are available:

o A ramp data pattern from 0 to 255

o A fixed data byte set by octet value
o Prime certification data pattern (PRIME IS A WONDERFUL TECHNOLOGYPRIME IS A
WONDERFUL TECHNOLOGY) with no space between 2 sentences.

The data pattern is repeated for the duration of the payload.

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  PPDU length – PPDU length in bytes. Note this field will be ignored when sweep PPDU length is
selected. The current firmware version supports a PPDU length of 1 byte to maximum of 500
bytes. It is also governed by maximum length allowed for the selected modulation scheme.
 Inter-PPDU time – The gap time between PPDU in unit of 10 microseconds.
 Number of PPDUs per setting – The number of PPDU per setting during MCS sweep, PPDU
length sweep or MCS/PPDU length sweep.

The following describes the PHY Rx Parameters can be configured:

 AGC – If selected, receiver performs automatic gain control. If unselected, manual gain setting is
used. Valid gain values are from 0 to 7 with step of 6dB.

The following describes the PHY Rx Parameters can be configured in PHY Rx Test mode only:
 Test Mode - When enabled, receiver will start comparing receive packet using the data pattern
selected and compute BER for BER testing.
 Data Pattern – When test mode is enabled, it can select data pattern used for comparison in
computing BER. A ramp data patter from 0 to 255 or a fixed data byte set by octet value. Note
this should be identical to the selection in the transmitter for valid BER result.

The following describes the PHY System Parameters:

 AGC Gain Min – Minimum AGC gain in dB
 AGC Gain Max – Maximum AGC gain in dB
 AGC Gain Step – Step size of AGC in dB

2.7 Get/Set MAC PIB

MAC PIB (PRIME standard Section 4.5.1-MAC variable attributes) can be configured as follows (Menu-
>Function->Set MAC PIBs):

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MAC PIB (PRIME standard Section 4.5.1 – MAC variable attributes) can be retrieved as follows (Menu-
>Function->Get MAC PIBs):

2.8 Get PHY PIB

PHY PIB (FLEX standard Section 3.10.1 PHY statistical attributes and 3.10.2 PHY Implementation attributes)
can be retrieved as follows (Menu->Function->Get PHY PIBs):

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2.9 Configuring Connection Parameters

A point-to-point connection without a Base node can be set up as follows (Menu->Function->Connection):

Note AES and PAC should not be used for this release

Once a connection is opened, the “Open” button will change to “Close”. The “Refresh” button will
refresh the dialog based on the current firmware Test Connection status, i.e., if the Test Connection is
open or closed.

2.10Selecting Frequency Band

Frequency band selection is supported. The default build “flex_iec432_flash.out”

supports three configurations:

1. Cenelec A/B/C/D and FCC band with fixed bandwidth of 24 kHz in step of 976.5
Hz.

2. Cenelec A band with fixed bandwidth of 12 kHz in step of 488.28 Hz.

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 3. Sub-10kHz with fixed bandwidth of 3 kHz in step of 122 Hz.

The following table lists the frequency band configuration and tone selection
commands:

Command Descriptions BW Tone

Spacing
Frequency Band Configuration

0xF4 Configure for Cenelec A/B/C/D and FCC

band.

This command should always be followed by

a reset device before tone selection should 24 kHz
take place. See example below. 976.5 Hz
0xF5 Configure for Cenelec A band

This command should always be followed by

a reset device before tone selection should
take place. See example below. 12 kHz 488.28 Hz
0xF6 Configure for Sub-10 kHz

This command should always be followed by

a reset device before tone selection should
take place. See example below. 3 kHz 122 Hz
Frequency Tone Selection

0xF7 0x00 0x40 Select starting frequency at tone 64

Note: The default TMDSPLCKIT-V2 AFE HW supports Cenelec A band only (35-90 kHz). Special
AFE HW is required for other frequency bands. They are provided based on request.

Note when exercising this command, there should be no active packet

transmit or receive ongoing.

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The default setting when running flex (flex_iec432_flash) at power up uses
configuration 1 with:

 Fixed bandwidth of 24 kHz

 Tone spacing of 976.5 Hz
 Frequency at 78-101.6 kHz

Example of Tone Selection

The starting tone can be selected as follows (Menu->Functions->MAC command):

1. Enter the command “0xF7 0x00 0x40”. Note this selects the starting tone index
to be 64. Or if command “0xF7 0x01 0x00” is used, the starting tone index is
256.

2. Click the “Send” button.

Example of Changing Configuration

To change to configuration 2 (Menu->Functions->MAC command):

1. Enter the command “0xF5”. Note this changes the operation to Cenelec A band
with fixed bandwidth of 12 kHz and tone spacing of 488 Hz.

22
 2. Click the “Send” button.

3. Reset device after changing configuration (Menu->Options->Reset Device)

4. Click the “Yes” button.

5. The starting frequency can now be changed.

Example of Tone Selection for Cenelec A/B/C/D and FCC Band

The following table lists the command and the corresponding frequency bands when
configuration 1 is selected:

Command Start Frequency End Frequency (kHz)

(kHz)
Cenelec A Band
0xF7 0x00 0x28 39.06 62.50
0xF7 0x00 0x29 40.04 63.48
0xF7 0x00 0x2A 41.02 64.45
0xF7 0x00 0x2B 41.99 65.43
0xF7 0x00 0x2C 42.97 66.41
0xF7 0x00 0x2D 43.95 67.38
0xF7 0x00 0x2E 44.92 68.36
0xF7 0x00 0x2F 45.90 69.34
0xF7 0x00 0x30 46.88 70.31
0xF7 0x00 0x31 47.85 71.29
0xF7 0x00 0x32 48.83 72.27
0xF7 0x00 0x33 49.80 73.24
0xF7 0x00 0x34 50.78 74.22
0xF7 0x00 0x35 51.76 75.20
0xF7 0x00 0x36 52.73 76.17
0xF7 0x00 0x37 53.71 77.15
0xF7 0x00 0x38 54.69 78.13

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 0xF7 0x00 0x39 55.66 79.10
0xF7 0x00 0x3A 56.64 80.08
0xF7 0x00 0x3B 57.62 81.05
0xF7 0x00 0x3C 58.59 82.03
0xF7 0x00 0x3D 59.57 83.01
0xF7 0x00 0x3E 60.55 83.98
0xF7 0x00 0x3F 61.52 84.96
0xF7 0x00 0x40 62.50 85.94
0xF7 0x00 0x41 63.48 86.91
0xF7 0x00 0x42 64.45 87.89
0xF7 0x00 0x43 65.43 88.87
0xF7 0x00 0x44 66.41 89.84
0xF7 0x00 0x45 67.38 90.82
0xF7 0x00 0x46 68.36 91.80
Cenelec B Band
0xF7 101 98.63 122.07

A special build “flex_iec432_flash_fcc.out” supports following configurations:

1. Cenelec A/B/C/D and FCC band with fixed bandwidth of 12 kHz in step of 488.28
Hz (upto ~500 kHz). The same command “0xF7” as described above for
selecting starting tone can be used.

2. Sending continuous Chirp signal over selected frequencies. The following

command should be used to select:

“0xf8 X1 X2 Y1 Y2 L”

x1 x2 = 2 bytes of starting tone index

y1 y2 = 2 bytes of ending tone index

L = transmit level (0 to 7) in 3 dB steps

For example, to transmit signal from tone index 400 to 800 with level 5 will be:
“0xf8 0x01 0x90 0x03 0x20 5”

Any subsequent tests should reset the device (Menu->Options->Reset Device)

2.11Testing PHY Performance

24
The PHY performance can be tested in a point-to-point configuration where system configuration steps
described on Section 2.3 should be used. One modem should be configured as transmitter in test mode and
the other modem as receiver in test mode (Menu->Options->PHY Parameters). The HW should be set up as
described in Section 3.1. An example for PHY test with DBPSK+FEC, transmitting at level -9 dB, PPDU length
of 100 bytes and inter-PPDU interval of 100 us in continuous mode is shown.
Note it does not support concurrent bi-directional data transfer.

Note that the enabling of PHY “Test Mode” on the Transmit or Receive would require the device mode to be
“Point to Point”. The following window will be prompted if device is not already in “Point to Point”. Click
“Yes” to reset the device and “Point to Point” mode will be set. The PHY test can now be continued,

By enabling the channel status and link quality report and setting report period (as described in Section 4.2),
the PHY performance (SNR/RSSI/PER/BER) will be displayed in the graphs and the statistics will be displayed
in the statistics panel.

2.12 Sending and Receiving Message

25
The Send Message function (Menu->Function->Send Message) sends a small text message from the one
device to another in point-to-point configuration. It is intended to test and verify communication between
the two systems in a point-to-point configuration.
Note that this operation would require the device mode to be “Point to Point”. On the transmitting device,
the following window will be prompted if device is not already in “Point to Point”. Click “Yes” to reset the
device and “Point to Point” mode will be set. Message send can then be continued,

On the receiving device, the device mode must be set to “Point to Point” following steps described in
Section 2.3

Note that the connection type such as ARQ enabled, PAC enabled or security profile used for the message
send can be modified via System configuration settings using steps described in Section 2.3.

When this option is selected, you may fill in a message and press send, and the other host will display the
message.

Note that the connection type such as ARQ enabled, PAC enabled or security profile used for the message
send can be modified via System configuration settings using steps described in Section 2.3.

2.13 Sending and Receiving File

The Send File function (Menu->Function->Send File) sends file from one device to another in a point-to-
point configuration.
Note that this operation would require the device mode to be “Point to Point”. On the transmitting device,
the following window will be prompted if device is not already in “Point to Point”. Click “Yes” to reset the
device and “Point to Point” mode will be set. Message send can then be continued,

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On the receiving device, the device mode must be set to “Point to Point” following steps described in
Section 2.3

Note that the connection type such as ARQ enabled, PAC enabled or security profile used for file transfer
can be modified via System configuration settings using steps described in Section 2.3.

This function is not a guaranteed error-free delivery (the file received may have dropped packets) and is a
means to push data from one board to another. The receiver will note both payload CRC and missing packet
errors and will attempt to notify the sender of these errors.

There are two modes for file transfer, stream and non-stream. Stream mode streams packets to the
receiver without waiting for the receiver to acknowledge receipt. A No NACKS option is also allowed in
stream mode. If un-selected, it requests receiver to only send NAKs when there is error. In non-stream
mode the receiver must ACK each packet before the sender will send the next.
The packet size may also be specified. This value represents the total packet size, including any protocol
headers. If an invalid size is entered, when Send is pressed, the following error will be displayed.

Once the file transfer begins, the Transfer Information section reflects transfer statistics.

27
Statistics may be cleared by selecting “File/New” or by pressing the New File button.

The transfer may be aborted by either the sender or receiver. The sender may abort by pressing the Abort
button and the receiver may abort by selecting the menu option “Functions/Abort file receive”.

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2.14 Flash Firmware
The flash firmware function (Menu->Function->Flash Firmware) downloads the new firmware image to the
DSP control card (instead of via JTAG using CCS flash programming as described in Appendix B).
Note if this is the first time running the “Flash Firmware” function on an old HW (RevB and older), the
procedures described in Error! Reference source not found. should be completed first before continuing.

The following steps should be used:

1. Enter the FLEX application “s record file” and press the Flash button, you will see that Flash upgrade
application is erasing the Flash.

For example, the “Flex_appemu_sn_flash.srec” should be used for the FLEX service node test

29
2. After Flash is erased, you will see the programming is in progress (packet by packet).

3. After programming is complete, you will see the following window. The new downloaded firmware
will boot up.

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3.0 System Trouble Shoot
3.1 Trouble shoot for squirt
The Serial Port is muxed by a driver called Squirt. The driver’s interface is on the windows taskbar. There
may be times that the driver has to be reset because no data is being forwarded to/from the applications.
To reset the Squirt driver, either right click the Squirt Taskbar Icon and select “Reset” or double click the
Squirt Taskbar Icon (which will momentarily turn green to indicate reset).

In the event of application exception (conditions where the applications have encountered a severe error
and is terminated), the Squirt Driver may require termination cleanup. When this occurs, you must exit any
PLC Host tools (PQM, Logger, etc.) and terminate the Squirt Driver by selecting all Squirt tasks (both
SQUIRT*.exe and SquirtSerialPort.exe) from the Task Manager and ending their process.

3.2 Trouble shoot for USB to Serial Dongle Communications

When the USB to serial dongle is plugged into the PC, the enumerated COM port can be found from system
properties->Hardware->device manager as follows:

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Note that the enumerated COM port needs to be lower than “COM19”. If not, it can be changed by selecting
the corresponding serial port, right click and click on “properties”. Then select the “features” panel and the
COM port can changed.

Note that it is recommended to power off the device prior to unplugging the USB serial dongle from the
PC.

3.3 Trouble shoot for PLC LQM Diagnostic Tool to Device Communications
 To check that the PLC LQM tool is communicating to the device, check that it can read system
information following steps in Section 2.4.
 If USB serial converter is being used, check that the correct COM port has been selected. Note that
the COM port may not be enumerated to the same port number when its unplugged an re-
plugged or a new USB port is being used.
 If PLC LQM tool has previously been communicating to the device and it was kept opened while
device has been reset or power cycled, it is recommended to close the PLC LQM tool and re-
opened.

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APPENDIX A – Code Composer Studio Installation and Setup

1. Install Code Composer Studio (CCS)

2. Connect USB cable to USB connector on the docking station.
3. Launch CCS. If CCS is installed, XDS100 emulation is installed and CCS is to configure to use XDS100
emulator.
4. Connect to target and CCS is ready to be used.

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APPENDIX B - PLC-DK Hardware Resource Usages
Table 4 PLC-DK GPIO pins configurations

GPIO PIN Connected to Flex Build Usage

GPIO00 PWM_1A Transmit

GPIO01 TP
GPIO02 PWM_2A Transmit
GPIO03 TP XINT2, TFLAG
GPIO04 TP XINT1, HALT
GPIO05
GPIO06 LED_AFE1 Beacon Indication (toggle per rx beacon)
GPIO07 LED_AFE2 Beacon Acquired (on)
GPIO08 LED_AFE3 Registration with BN completed (on)
GPIO09 ZeroCross 1 Zero crossing capture
GPIO10
GPIO11 ZeroCross 2 Zero crossing capture
GPIO12 TXDRVEN OPA enable pin
GPIO13
GPIO14 SCI (SCITXDB) UART host port
GPIO15 SCI (SCIRXDB) UART host port
GPIO16 SPI (SPISIMOA) PGA (option)
GPIO17 SPI (SPISOMIA) PGA (option)
GPIO18 SPI (SPICLK) PGA (option)
GPIO19 SPI (SPISTEA) PGA (option)
GPIO20
GPIO21
GPIO22 LED7 PNPDU transmission (toggle per PNPDU tx)
GPIO23 LED8 Beacon transmission (toggle per beacon tx)
GPIO24 McBSP (MDXB) PGA (option)
GPIO25 McBSP (MDRB) PGA (option)
GPIO26 McBSP (MCLKXB) PGA (option)
GPIO27 McBSP (MFSRB) PGA (option)
GPIO28 SCI (SCIRXDA) UART diagnostic port
GPIO29 SCI (SCITXDA) UART diagnostic port
GPIO30
GPIO31 LED2 System heart beat (toggle at 1 sec rate)
GPIO32 (I2C) SDAA EEPROM
GPIO33 (I2C) SCLA EEPROM
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40

Table 5 PLC-DK Peripherals and Interrupts Usage

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Peripherals Flex Build Usage Interrupt
32-bit CPU Timers
1. During packet transmission
- Trigger Tx DMA to ePWM/HRPWM @ 500 kHz
2. CSMA
Timer 0 - Track FLEX frame structure PIE 1.7
Timer 1 Absolute timer (FLEX PHY Time Stamp)
Timer 2 DSP-BIOS Systick INT14
Watchdog Timer
TBD (Reset)
ADC
Rx ADC samples @ 250 kHz

McBSP
McBSPB PGA controls (in SPI mode)
SCI
PIE 9.1 - Rx
SCIA Diagnostic port PIE 9.2 - Tx
PIE 9.3 - Rx
SCIB Host port PIE 9.4 - Tx
SPI
SPIA PGA controls (optional)
I2C
Interface to EEPROM
eCAP
eCAP1 Zero crossing measure
eCAP2 Zero crossing measure
ePWM
ePWM1 Tx sample (integer part)
ePWM2 Tx sample (integer part)
HRPWM
Tx sample (fractional part)
DMA
Channel 1 ADC PIE 7.1
Channel 2 PWM PIE 7.2
Channel 3 PWM

Table 6 PLC-DK Flash Configurations and Usage

Sectors Size (words) Flex Build Usage

A 32K Code Start Image
B 32K Reserved
C 32K
D 32K firmware upgrade image
E 32K Reserved
F 32K
G 32K
H 32K Flex Image

Table 7 FLEX System Memory and MIPs usage:

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MEM/MIPS BenchMark
FLASH 139 kB
RAM 68 kB
MIPS Average 95 MIPs

36
APPENDIX C – Logger Setup
A PLC Event Logger can be used for diagnostic purpose. Set up communication Port (via Logger
Settings).
 Goto View

 Click on Settings
 Select the check box for PLC Logger 1(COM1)
 Highlight PLC Logger 1

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 Click Setup and select communication port used for connecting to the serial connection on the
docking board. In this example, it uses COM1 port.

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 Click on Setup and configure serial port as follows:

39
APPENDIX D – PHY Example Project
The PHY examples demonstrate the calling of PHY library API when HW is setup with 2 devices connected
via power line. One device will send one packet and wait for one receive packet and then transmit another
packet. This alternates between Tx and Rx. The packet is of size of 756 bytes with a repeating ramp data
pattern using the followings:
Modulation: DQPSK with FEC enabled
PPDU payload length: 63 symbols

1. Unzip ti_Flex_phy_example.zip
2. In CCS, open Flex phy test project phy_tx_rx_bios.pjt (Menu Project->Open –
test_tx_rx\test_tx_rx_bios.pjt)
3. In CCS, Build project (Menu Project->Build Clean)
4. In CCS, Reset target (Menu Debug->Reset CPU)
5. In CCS, Load phy_tx_rx_bios.out (refer to section Appendix B: Download binary to F28335 Flash)
 Attach the JTAG to the board and connect (Debug->Connect)
 Flash the board (Menu Tools/F28xx On-Chip Flash Programmer)
 Verify the Clock Configuration Settings.
 Under Operation, enter the filename to program, or press the “Browse” button to
locate the .out file)
 Press the “Execute Operation” button
6. In CCS, Reset, Run (Menu Debug->Run) and LED flashes.
7. Load the same code to the second board.
8. Connect the two boards via power line cables. Both boards should be alternating between Rx and Tx
and the LEDs should be blinking.

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Source File Description

• Test bench
– Project file: test_tx_rx_bios.pjt
– Test bench: test_tx_rx_bios.c and test_phy_swi.c demonstrates alternating FLEX PHY Tx and PHY rx
using provided PHY library
– Linker command:test_tx_rx_BIOS_flash.cmd
– Test example for flash

• Header files
– PHY common: phy.h
– PHY Tx: phy_tx.h
– PHY Rx: phy_rx.h
– HAL: hal_afe.h
– Chip support library header files

• Libraries
– PHY lib: phy_flex_lin.lib
– HAL lib: hal_afe_150.lib
– Chip Support lib: csl_150_noFPU.lib

PHY Library Demonstration

• The PHY library example project demonstrates packet transmission and reception at the physical
layer in a TDD fashion.

• Flash 2 F28335 boards with PHY library example executable.

• Connect via powerline

• Sequence of operation
– Board A sends a packet
– Board B receives packet and sends a packet back to board A
– This will be repeated.
– LED on DSP control card will blink if packet transmission and reception is ongoing

Hardware Resource Usage

The PHY library uses the following HW resources:

 DMA Channels
o Channel 1 – Receive ADC input
o Channel 2 – Transmit PWM_1A output
o Channel 3 – Transmit PWM_2A output

 CPU Timers
o Timer 0 – PHY
o Timer 1 – FLEX PHY System Timer 20-bits in 10us increment
o Timer 2 – Not Used

 GPIO

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 a. GPIO 00 – PWM_1A
b. GPIO 02 – PWM_2A
c. GPIO 12 – OPA Enable

PHY Library Test Bench Steps

• HW initialization (F28335 specifics)

• Flash configuration
• ISR Installation
– Timer 0 (PHY_tx_cpuTimer0_isr)
– DMA channel 1 (PHY_RX_DMA_BIOS_isr)
– DMA channel 2 (PHY_TX_DMA_BIOS_isr)

• AFE initialization
– HAL_afeTxInit
– HAL_afeRxInit

• PHY library initialization

– PHY_txInit
– PHY_rxInit

• Generate packet for transmission

• Start PHY Rx to listen to line

– PHY_rxStart(0xFFFF, cb_sync)

• Callback for PHY_rxStart- cb_sync

• If status is success, start PPDU decode (only 1 time)

- PHY_rxPpduStart(cb_ppdu)

• Callback for PHY_rxStart - cb_ppdu

• If status is success, do some processing if needed and release

buffer back to PHY

-PHY_rxPpduRelease

- LED toggle

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 Start packet transmission
– PHY_txPpdu(&PHY_tx_ppdu_s, cb_tx);

• Callback for PHY_txPpdu - cb_tx

• If status is success, do some processing if needed.

• Enable system interrupt

ISR Descriptions

• CPU Timer 0 ISR – Start packet transmission @ specified time

interrupt void PHY_tx_cpuTimer0_isr(void)

{
txSymbDone = 1;
HAL_cpuTint0Func();
}

• DMA1 Channel ISR – Incoming ADC samples ready for process @ symbol rate

interrupt void PHY_rx_dintch1_isr(void)

{
/* Call HAL AFE function for dma handling */
HAL_afeRxDmaCh1IntFunc();

/* post RX SWI */
SWI_inc(&SWI_PHY_RX);

• DMA2 Channel ISR – Outgoing PWM completed @ symbol rate

interrupt void PHY_tx_dintch2_isr(void)

{
HAL_afeTxDmaCh2IntFunc();

/* Post TX SWI */
SWI_inc(&PHY_TX_SWI);

Tx SWI
 PHY_TX_SWI() -- Calls PHY API for TX symbol processing (PHY_txSmRun()).

Rx SWIs

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 • PHY_RX_SWI() -- Wait for DMA channel 1 ready (incoming ADC samples ready)
– Perform PHY Rx symbol processing
• PHY_rxSmRun()

• PHY_RX2_SWI() – Starts RX bit processing

• PHY_rxSmRun2()

APPENDIX E – SCI Example Project

The SCI (Serial Communication Interface) examples demonstrate use of the SCI in loopback mode. The base
TI SCI examples have been extended to demonstrate external loopback, i.e., all RX data is looped back to TX.
The loopback mode is determined by the define SCIA_INTERNAL_LOOPBACK. Both polled and interrupt usage
is provided in the examples.
In External Loopback Mode, a host terminal is attached and data is sent to the firmware. The firmware
echoes all received characters back to the sender. The firmware configures the serial ports at 115200 baud,
no parity, 8 data bits and 1 stop bit (115200,N81), and the host terminal must be configured the same.
1. Unzip sci_demos.zip
2. In CCS, open project Example_2823xScia_FFDLB.pjt for polled mode,
Example_2823xScia_FFDLB_int.pjt for interrupt mode. (Menu Project->Open –
test\scia_loopback[_interrupts]\ Example_2823xScia_FFDLB[_int].pjt)
3. Select the loopback configuration by either comment or uncomment the define
SCIA_INTERNAL_LOOPBACK.
4. In CCS, Build Project (Menu Project->Build Clean)
5. In CCS, Reset target (Menu Debug->Reset CPU)
6. In CCS, Load Example_2833xScia_FFDLB.out for polled mode, Example_2823xSci_FFDLB_int.out for
interrupt mode (refer to section Download binary to F28335 Flash)
o Attach the JTAG to the board and connect (Debug->Connect)
o Flash the board (Menu Tools/F28xx On-Chip Flash Programmer)
 Verify the Clock Configuration Settings
 Under Operation, enter the filename to program, or press the “Browse” button to
locate the .out file)
 Press the “Execute Operation” button
7. Attach and configure Host Terminal, if applicable (note that the even in internal loopback, the SCI
still sends TX data on the wire, so the Host Terminal will still receive internal loopback data).
8. In CCS, Run (Menu Debug->Run)

44