BCAO101

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M1

Q2.Convert 128 to binary


10000000(Ans)

Q3.Convert (128)10 to hexadecimal


1.(80)16

Q6.Given that (16)10 =100b , find the value of b.


4(Ans)

Q5.Add -75 to +26 using the 8-bit 2’s Complement arithmetic


-49(Ans)

Q1. Convert (11011.101)2 to decimal


27.625(Ans)

Q7.Given that 29210=1204b in some number system, find the base of that system?
6(Ans)

1. Differentiate between fixed point and floating point representation.

A fixed point number just means that there are a fixed number of digits after the decimal point. A
floating point number allows for a varying number of digits after the decimal point. For example, if
you have a way of storing numbers that requires exactly four digits after the decimal point, then it is
fixed point.

2. Convert binary number 1101010 into hexadecimal number.


ans-(6A)16
15

1. Explain 4 bit even And odd parity generator with proper k-map, truth table and circuit
diagram. Explain r's complement and (r-1)'s complement with example. Calculate 10's
complement of (2457)10

8+5+2

Solution: 10's complement for (2457)10 is calculated by adding 1 to (7542)10 which is the 9's
complement. Therefore, 10's complement of (2457)10 is (7543)10.

The parity generator is a combination circuit at the transmitter, it takes an original message as input
and generates the parity bit for that message and the transmitter in this generator transmits
messages along with its parity bit.

Even Parity Generator


The even parity generator maintains the binary data in even number of 1’s, for example, the
data taken is in odd number of 1’s, this even parity generator is going to maintain the data as
even number of 1’s by adding the extra 1 to the odd number of 1’s. This is also a
combinational circuit whose output is dependent upon the given input data, which means the
input data is binary data or binary code given for parity generator.

Odd Parity Generator

The odd parity generator maintains the binary data in an odd number of 1’s, for example, the
data taken is in even number of 1’s, this odd parity generator is going to maintain the data as
an odd number of 1’s by adding the extra 1 to the even number of 1’s. This is the
combinational circuit whose output is always dependent upon the given input data. If there is
an even number of 1’s then only parity bit is added to make the binary code into an odd
number of 1’s.

1) (r-1)'s complement

The (r-1)'s complement of a number in any number system with base r can be found out by
subtracting every single digit of a number by r-1.

For Example: In the binary number system, the base is 2. Hence, its (r-1)'s i.e., (2-1 =1)'s
complement can be obtained by subtracting each bit from 1, i.e., 1's complement for 001 can
also be calculated by subtracting 001 from 111 which will be (111-001) = (110)2.

Similarly, in the octal number system, the base is 8 so its 7's complement can be calculated
by subtracting each bit by 7, i.e., 7's complement for 347 in octal number system can be
calculated by subtracting 347 from 777 which will yield (777 – 347) = (430)8.

2) r's complement

The r's complement of a non-zero number in any number system with base r can be
calculated by adding 1 to the LSB of its (r-1)'s complement.

For Example: In binary number system, 2's complement of 001 can be calculated by adding
1 to the LSB of its 1'complement (i.e., 110 + 1) = (111)2.

Similarly, in octal number system, 8's complement of 347 can be calculated by adding 1 to
the LSB of its 7'complement (i.e., 430 + 1) = (431)8.

Calculate 10's complement of (2457)10

Solution: 10's complement for (2457)10 is calculated by adding 1 to (7542)10 which is the 9's
complement. Therefore, 10's complement of (2457)10 is (7543)10.
M2

Q14.A+1=?
1(Ans)

Q11. The NAND gate can functions as a NOT gate if-----------------------


All inputs are connected together.(Ans)

Q12.The Logic expression AB+A’B’ can be implemented by giving the inputs A and B to a two-
input---------------
X-NOR(Ans)

8. Digital circuit can be made by the repeated use of ………………


NAND gates(ANS)

Q11. The NAND gate can functions as a NOT gate if_______________


All inputs are connected together.(Ans)

18. Explain why is a two-input NAND gate called universal gate? 5

NAND gate is called universal gate because any digital system can be implemented with the
NAND gate. Sequential and combinational circuits can be constructed with these gates
because element circuits like flip-flop can be constructed from two NAND gates connected
back-to-back. NAND gates are common in hardware because they are easily available in the
ICs form. A NAND gate is in fact a NOT-AND gate. It can be obtained by connecting a NOT
gate in the output of an AND gate.

M3

Q15. AB+A’C+BC=?
AB+A’C(Ans)

Q16.AB+A’C=?
(A+C)(A’+B)(Ans)

Q17.Duals of A(A+B) is _________________


A+AB(Ans)

Q19.Reduce the expression f=A[B+C’(AB+AC’)’]


AB(Ans)

Q21.Dual of A+B is
AB(Ans)

Q22.Calculate 9's complement of (2457)10

Solution: 9999 – 2457 = (7542)10


5

1. Explain what is Associate law & Commutative Law?

Associate law is a low of addition and multiplication and according to this law grouping of
the variable is the OR-ing or AND-ing of several variables is immaterial and the results
obtained are the same.

2. What is meant by isomorphic Boolean algebra?

Answer:

⟶B1 that retains the three operations +,*, and ‘ for all elements x, y in B,
Isomorphic Boolean algebras B and B1 are those that have a one-to-one correspondence f: B

 f (x+y)=f(x)+f(y)
 f (x*y)=f(x)*f(y) and
 f(x’)=f(x)’

3. What is the equivalent expression for the Boolean expression x’y’z +yz+ xz?

Solution:

Answer: z

Given Boolean expression: x’y’z +yz+ xz

x’y’z +yz+ xz = z(x’y’+y+x)

Now, apply distributive law for the first two terms inside the bracket.

x’y’z +yz+ xz = z[(x’+y) (y+y’)+ x]

x’y’z +yz+ xz = z [(x’ + y) . 1 + x] [Since A+A’ = 1]

x’y’z +yz+ xz = z [x’ + y + x]

Further x+x’ = 1

So, x’y’z +yz+ xz = z(1+y)

Now, using null law, 1+y = 1

x’y’z +yz+ xz = z.1

Now, using identity law, A.1 = A


Therefore, x’y’z +yz+ xz = z.

Hence, the Boolean expression equivalent to x’y’z +yz+ xz is z.

15

1. Explain Demorgan's Theorem . What is principle of duality.

Check whether AC + ABC = AC is true or false? 5+5+5

Solution:

Given Boolean expression: AC + ABC = AC

AC (1+B) = AC

Now, using the null law 1+B = 1, the above expression can be written as:

AC.1 = AC

Thus, using the identity law, 1.A = A, the above expression becomes:

AC = AC

Hence, AC + ABC = AC is true.

2. Reduce the Boolean expression: A = XY + X(Y+Z) + Y(Y+Z) 7

Solution:

Given: A = XY + X(Y+Z) + Y(Y+Z)

The given Boolean expression can be written as follows:

A = XY + XY + XZ + YY + YZ

Using Idempotent law, Y.Y = Y

Thus, A = XY + XY + XZ + Y + YZ

Again, XY + XY = XY, we get

A = XY + XZ + Y + YZ
A = XY + XZ + Y(1+Z)

Using null law, (i.e., 1+A = 1), we can write

A = XY + XZ + Y.1

Using Identity law, 1.Y = Y.

So, A = XY + XZ + Y

Now, the above form can be written as:

A = Y(1+X) + XZ

A = Y.1 + XZ

A = Y + XZ

Hence, the reduced form of the Boolean expression A = XY + X(Y+Z) + Y(Y+Z) is A =


Y+XZ.

What is the simplified sum of product form for the Boolean expression:

(A + B’ + C’)(A + B’ + C)(A + B + C’) 8

Solution:

Given Boolean expression: (A + B’ + C’)(A + B’ + C)(A + B + C’)

Now, using the distributive law, we can write

(A + B’ + C’)(A + B’ + C)(A + B + C’) = [(A+B’) + C’C](A + B + C’)

Using AA’ = 0, it becomes

(A + B’ + C’)(A + B’ + C)(A + B + C’) = [(A+B’) + 0](A + B + C’)

Since A + 0 = A,

(A + B’ + C’)(A + B’ + C)(A + B + C’) = (A+B’)(A + B + C’)

(A + B’ + C’)(A + B’ + C)(A + B + C’) = A + B’.(B+C’)

Again, using distributive law

(A + B’ + C’)(A + B’ + C)(A + B + C’) = A + B’B +B’C’

(A + B’ + C’)(A + B’ + C)(A + B + C’) = A + 0 + B’C’

(A + B’ + C’)(A + B’ + C)(A + B + C’) = A + B’C’.


M4

Q. If a three variable switching function is expressed as the product of maxterms by f(A,B,C)=


II(0,3,5,6) then it can also be expressed as the sum of minterms by ________
Σ(1,2,4,7)(ans)

Q23. The simplified SOP (Sum Of Product) form of the Boolean expression (P + Q' + R') . (P
+ Q' + R) . (P + Q + R') is ________
(P+Q’R’)(Ans)

Q24. The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is


m2+m4+m6+m7(Ans)

Q. Total no of cells in karnaugh map of a switching function(A,B,C) consisting only three


variables are _______________ 8(ans)

Q27. What is the minimum number of two-input NAND gates used to perform the function of
two input OR gate?
Three(Ans)

Q28. The most simplified form of the boolean function, x (A,B,C,D) = Σ


(7,8,9,10,11,12,13,14,15) (expressed in sum of minterms) is?
A+BCD(Ans)

Problem-01

Minimize the following boolean function-

F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 4, 5)

Solution-

 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.


 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.
Then, we have-

Now,

F(A, B, C)

= (A + A’)(B’C’ + B’C) + A(B’C’ + B’C + BC + BC’)

= B’ + A

Thus, minimized boolean expression is-

F(A, B, C) = A + B’

Problem-02:

Minimize the following boolean function-

F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)

Solution-
 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.
 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,

F(A, B, C)

= A'(B’C’ + B’C) + A(BC + BC’)

= A’B’ + AB

Thus, minimized boolean expression is-

F(A, B, C) = AB + A’B’

15
Q. What are the advantages of k-map. Explain different methods to
minimize boolean expressions. 3+4

Minimize the following boolean function-

F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15) 8

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.


 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-
Now,

F(A, B, C, D)

= (A’B’ + A’B + AB + AB’)(C’D + CD) + (A’B’ + AB’)(C’D’ + C’D)

= D + B’C’

Thus, minimized boolean expression is-

F(A, B, C, D) = B’C’ + D

Q2. Implement the Function given below using the SOP. 7

F = AB + CD + EF + GH

In SOP several product terms are logically added, AND-OR gates are used.

Explain minterm & maxterm with example. What is canonical form? 3+3+2
Minterms:

A binary variable may be either in its normal form (x) or in it’s complement form x’.
Consider three binary variables x, y, and z. The possible combinations will be eight (8).

2n = 23 = 8

Where n = number of variables.

Combining all combinations with AND gate in such a way that we take each variable being
primed if the corresponding bit is zero and unprimed if the corresponding bit is 1.

Each of these 8 AND terms represents one of the distinct area in the Venn diagram and is
called a Minterm or a standard product. Minterms are represented by small letter (m).

Maxterm:

Consider three binary variables x, y, and z. We will have eight possible combinations.

2n = 23 = 8

Where n is the number of variables.

Combining all combinations with OR gate in such a way that, we take each variable being
primed if the corresponding bit is 1 and unprimed if the corresponding bit is zero (0). Each of
these 8 OR terms represents one of the distinct area in the Venn diagram and is called a
Maxterm or a standard sums. Note that each Maxterm is the compliment of its corresponding
Minterm and Vice Versa. Minterms and Maxterms for three variables shown in the table.
Canonical form:

Expressing a Boolean function in SOP or POS is called Canonical form.

M5

1. Dual of NAND function is_____________


NOR function(Ans)

2. The NOR function is dual of ________________


NAND function(Ans)

Q32. Besides NAND gate universal gate ___________


1. NOR function(Ans)

Q33.Rather than AND-OR gates combinational circuit are made by _______


1. NAND-NOR(Ans)

1. Represent a NAND gate as OR gate using Demorgan's law. 5

(A.B)'=A'+B'
2. How will you obtain OR, AND gates from the NAND and NOR gates? Write symbols, Boolean
formula, and truth table.
ans- When we join the inputs of a NAND gate we can obtain a NOT gate. Also, when joining the two
inputs of a NOR gate together we can obtain a NOT gate.

15

Q1. Explain Multi-level Implementation using NOR Gate and NAND Gate. 15

Multi-level Implementation using NOR Gate

Schematic having more than two levels of gates is known as a multi-level schematic.

We can implement multi-level POS expression using NOR gate. The conversion of
multi-level expression into NOR gate has the same method as two-level
implementation.

The multi-level expression can be converted into two-level expression but for the
sake of realization, we will implement a multi-level expression.

Suppose a 4-level function:

F = ( A + B ( C + D )) ( B + D’ )

First, we will draw its schematic using AND, OR, NOT gates.

Notice the OR-AND pattern like two-level implementation. It can be easily converted
since the bubble cancels each other.

Now we will convert it into mixed notation for NOR.


The two bubbles along a single line cancel each other. However, there is a single
bubble at the 2nd level gate’s input. so we will complement the input B to compensate
the bubble.

Now redraw the whole schematic replacing OR-Invert and Invert-AND with NOR gate
symbol as shown in the figure below.

MULTI-LEVEL Implementation using NAND Gate

Schematic having more than two levels of gates is known as a multi-level schematic.

We can implement multi-level SOP expression using NAND gate. The conversion of
multi-level expression into NAND gate has the same method as two-level
implementation.

The multi-level expression can be converted into two-level expression but for the
sake of realization, we will implement a multi-level expression.
Suppose a multi-level function be;

F = A ( B + CD ) + BD’

This is a four-level function

First, we will draw its AND-OR schematic

Notice the AND-OR pattern. So it can be easily converted into NAND gates. Now we
will convert this into mixed notation i.e. AND gate will be converted into AND-
INVERT and OR will be converted into INVERT-OR as shown in the figure given
below.
Remember double bubbles along a single line cancel each other, and a single
bubble along a line should be compensated by inserting an inverter in that line.

Notice the 3rd line of input B, there is a single bubble. To compensate this bubble,
either an inverter should be added or the input B should be complimented.

Then redraw the whole schematic using all NAND gates by replacing AND-INVERT
and INVERT-OR with NAND gates as shown in the figure below.

M6

Q34. If A and B are the inputs of a half adder, the carry is given by __________
A AND B(Ans)

Q35. The difference between half adder and full adder is __________
Half adder has two inputs while full adder has three inputs(Ans)

Q. How many AND, OR and EXOR gates are required for the configuration of full adder?
2, 1, 2(Ans)

1. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.


b) Borrow
1. Full subtractor is used to perform subtraction of ___________bits.
a) 3 bits

7. What does minuend and subtrahend denotes in a subtractor?


c) Its inputs

Q1.What is the difference between a half adder and a full adder? 5


The main difference between a half adder and a full adder is that the half adder can only add two
operands, whereas the full adder can add three operands.

Q2. Explain single bit comparator with proper circuit, truth table and Boolean expression . 5

A comparator used to compare two bits is called a single-bit comparator. It consists of two
inputs each for two single-bit numbers and three outputs to generate less than, equal to,
and greater than between two binary numbers.30 Aug 2023

15

Q1. Design a combination circuits for a half & full subtractor and explain it in detail. 10+5

Explain the limitations of half subtractor over full subtractor.

Only handles subtraction of two single-bit binary numbers. Cannot perform addition or handle
multi-bit numbers. Only gives a difference and a borrow output, not the sum and carry. Cannot
handle negative numbers or perform signed subtraction.

Q2. Design a combination circuits for a carry look ahead adder and explain it in detail. 7+8

Design a combination circuits for a 4 bit parallel adder and explain it in detail.

A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic. A
carry-lookahead adder improves speed by reducing the amount of time required to determine carry
bits.

Q3. Design a combination circuits for a half adder & full adder and explain it in detail. 10+5

Explain binary adder-subtractor with block diagram.

The Half Adder is a type of combinational logic circuit that adds two of the 1-bit binary digits. It
generates carry and sum of both the inputs. The Full Adder is also a type of combinational logic that
adds three of the 1-bit binary digits for performing an addition operation.

A Binary Adder-Subtractor is a special type of circuit that is used to perform both operations, i.e.,
Addition and Subtraction. The operation which is going to be used depends on the values contained
by the control signal. In Arithmetic Logical Unit, it is one of the most important components.

M7
Q. What is the indication of a short to ground in the output of a driving gate?
b) There is a signal loss to all load gates(ANS)

Q . _______________ combinations of logic gates can decode binary 1101?


b) One 4-input AND gate, one inverter(ANS)

Q39. Convert given binary number to gray code(1101)2


1011(Ans)

Q. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator.
What are the output levels?
A > B = 1, A < B = 0, A = B = 0

18. How many data select lines are required for selecting eight inputs?
3(ans)

20. Which gate is best used as a basic comparator?


Exclusive-OR

Q1. Explain the difference between encoder & decoder. 5

An encoder is a device, circuit, or program that converts digital data into an analogue signal. A
decoder is a device, circuit, or program that converts an analogue signal into digital data. Input
lines: Encoders usually have more input lines than decoders.

Q2. Explain the difference between decoder & demultiplexer. 5

Main Differences between Decoder and Demultiplexer A decoder is a logic circuit that
changes the format of an encrypted input stream. In contrast, a demultiplexer (DEMUX)
is a combination circuit that is utilized to build general-purpose logic. It routes the single
input signal into one of the various output signals.

Q3. Explain 1X2 multiplexer with proper diagram, truth table, Boolean expression. 5

In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0, and
single input, i.e., A. On the basis of the selection value, the input will be connected to one of the
outputs.

15

Q1. Explain binary to gray code converter and gray to binary code converter with proper example,
diagram, truth table, Boolean expression. 15
The Binary to Gray code converter is a logical circuit that is used to convert the binary code into its
equivalent Gray code. By putting the MSB of 1 below the axis and the MSB of 1 above the axis and
reflecting the (n-1) bit code about an axis after 2n-1 rows, we can obtain the n-bit gray code.

Q2.Design a full adder using 3:8 decoder. 8+7

Explain the difference between multiplexer & demultiplexer.

A Multiplexer generates a single output for data and signals. A Demultiplexer generates multiple
outputs for data and signals.

Q3. What is multiplexer? Explain 4X1 multiplexer. 2+7+6

Explain encoder with proper diagram, truth table, Boolean expression.

4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one output
Y. The block diagram of 4x1 Multiplexer is shown in the following figure. One of these 4 inputs will
be connected to the output based on the combination of inputs present at these two selection lines.

M8

Q40. How is a J-K flip-flop made to toggle?


J = 1, K = 1(Ans)
Q41. In J-K flip-flop, “no change” condition appears when ___________
J = 0, K = 0(Ans)
Q42. In D flip-flop, D stands for _____________
Data(Ans)
43. The characteristic equation of S-R latch is ____________
Q(n+1) = (S + Q(n))R’(Ans)

7. The logic circuits whose outputs at any instant of time depends only on the present input but also
on the past outputs are called ________________
b) Sequential circuits

1. Explain what is an excitation table and a state table?

Excitation table gives an information about Explain what should be the flip-flop inputs if the
outputs are specified before and after the clock pulses.

State table consists of complete information about present state, next state, and outputs of a
sequential circuit.

2. What is toggling state & race condition?


Race around condition happens when current output triggers a change in future output (as in
the case of JK flip flop). Within the same clock pulse the output keeps changing. ( resulting
in race between 0 & 1) Toggling is when a particular input changes the output (i.e. from
0 to 1 or vice versa)

15

1. Explain the difference between sequential circuit & combinational circuit. Explain SR Flip-flop in
detail. What is the disadvantage of it and how it can be eliminated? 5+5+5

Combinational Circuit does not require any memory element to store the output. Sequential Circuit
requires a memory element to store the previous state output. It requires no feedback for
generating the next output. Sequential Circuit requires feedback as it relies on the previous
output/feedback and the current input.

2. With logic diagram and truth table explain the working JK Flip-flop. Also obtain its characteristic
equation. How JK flip-flop is the refinement of RS flip-flop? Explain D- Flip-flop in detail. 7+4+4

JK flip flop operates on sequential logic principle, where the output is dependent not only on the
current inputs but also on the previous state. There are two inputs in JK Flip Flop Set and Reset
denoted by J and K. It also has two outputs Output and complement of Output denoted by Q and Q̅.

3. Explain the difference between latch & flip flop. Explain T- Flip-flop in detail. Explain master-slave
Flip-flop in detail. 5+5+5

The difference between latch and flip flop is that a latch is level-triggered (outputs can change as
soon as the inputs change) and Flip-Flop is edge-triggered (only changes state when a control
signal goes from high to low or low to high). Latches are something in your design that always
needs attention.

M9

Q44. A decimal counter has ______ states.

10(ans)

Q45. Ripple counters are also called ____________


Asynchronous counters(Ans)
Q46. In digital logic, a counter is a device which ____________
Stores the number of times a particular event or process has occurred(Ans)
Q47. Synchronous counter is a type of ____________
MSI counters(Ans)

Q. 1. Explain the difference between serial &parallel counter.

Serial mode offers the advantage of fewer traces on the pc board, and fewer pins on the devices.
Parallel offers the advantage of transferring 8 data bits per I/O clock cycle, but at the disadvantage of
many more pins required on the devices.

15

Q. Design and draw the 3 bit up-down synchronous counter? Explain about Ring
counter? 8+7

A ring counter is a type of counter composed of flip-flops connected into a shift register, with the
output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.

Q. Explain about ripple counter? Explain the difference between asynchronous & synchronous
counter. 8+7
Various flip flips in an asynchronous counter, sometimes called a ripple counter, are triggered by
different clocks rather than simultaneously. Asynchronous counters operate more slowly than
synchronous counters because the same clock simultaneously activates all flip-flops in a
synchronous counter.

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external
clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous
counters are also called ripple-counters because of the way the clock pulse ripples it way through
the flip-flops.

M10

Q48. A register is defined as ___________


The group of flip-flops suitable for storing binary information(Ans)

Q49. The register is a type of ___________


Sequential circuit(Ans)

Q50. The main difference between a register and a counter is ___________


A register has no specific sequence of states(Ans)
Q51. A shift register is defined as ___________
The register capable of shifting information either to the right or to the left(Ans)

1. Explain the difference between SISO & SIPO. 5

SISO shift registers are commonly used in communication systems, where data is transmitted over a
single wire. SIPO stands for Serial-In, Parallel-Out. It is a type of shift register where data is inputted
one bit at a time and outputted in parallel, meaning all bits are outputted simultaneously.

2. . Explain the difference between PISO & PIPO. 5

PISO shift registers are commonly used in digital circuits, where data needs to be processed serially.
PIPO stands for Parallel-In, Parallel-Out. It is a type of shift register where data is inputted in parallel
and outputted in parallel.
15

Q. What is buffer register? With the help of simple diagram explain 4-bit controlled buffer
register. Explain bidirectional shift register. 5+5+5

A memory buffer register (MBR) or memory data register (MDR) is the register in a computer's CPU
that stores the data being transferred to and from the immediate access storage. It contains a copy
of the value in the memory location specified by the memory address register.

A bidirectional shift register is a versatile circuit used for shifting data either to the right or left
based on an input signal. It can be implemented using D flip-flops and logic gates, enabling the
transfer of data from one stage to the next stage in the desired direction determined by a mode
control signal.

Q. What is the function of shift register? With the help of simple diagram

explain its working. With block diagram and timing diagram explain the

serial transfer of information from register A to register B. 5+5+5

Shift registers are used in several signal-processing applications, including radar, electronic warfare,
and communications, where they supply such functions as convolution, error correction, and
encryption.

Q. What is time delays? Explain universal shift register? What is Ring & Johnson counter?3+6+6

Ring shift counters and Johnson shift counters are used to generate sequential control waveforms.
The Ring shift counter is a recirculating register in which the serial output is connected back to the
serial input. The Q outputs of the Ring shift counter will go high for one clock pulse one at a time in
sequence

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