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verilog basics

Verilog

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16 views

verilog basics

Verilog

Uploaded by

narendrasetty961
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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INTRODUCTION TO VERILOG

INTRODUCTION TO VERILOG:
 Verilog as HDL
 Levels of design Description
 Module
 Simulation and Synthesis Tools
 Test Benches.

LANGUAGE CONSTRUCTS AND CONVENTIONS:


 Introduction, Keywords, Identifiers, White Space Characters, Comments,
 Numbers
 Strings
 Logic Values
 Strengths
 Data Types
 Scalars and Vectors
 Parameters
 Operators.
Unit- I

Objectives and Outcomes

Objective: To make the student learn and understand


 Acquire a basic knowledge of the Verilog HDL
 Language constructs and conventions in Verilog
 Basic Concepts of Verilog HDL like Data Types, System Tasks and
Compiler Directives.

Outcomes: The student will be able to


 Define basic terms in HDL
 Knows Syntax and lexical conventions
 Remembers Data types, operators
 Remember testbenches for simulation and verification
VERILOG AS AN
HDL
 Verilog aimed at providing a functionally tested and a
verified

design description for the target FPGA or ASIC.


LEVELS OF DESIGN
DESCRIPTION
Gate Level

Data Flow

Behaviora
l Level

Circuit
Level or
switch
level
Circuit Level or switch level

 At the circuit level, a switch is the basic element with


which digital circuits are built.

 Switches can be combined to form inverters and other


gates at the next higher level of abstraction.
Gate Level

 At the next higher level of abstraction,design is carried


out in terms of basic gates.

 All the basic gates are available as ready modules


called “Primitives”.
Data Flow

 Data flow is the next higher level of abstraction.

 All possible operations on signals and variables


are represented here in terms of assignments

y = (ab+cd)
Behavioral Level

 Behavioral level constitutes the highest level of design


description; it is essentially at the system level itself.

 With the assignment possibilities, looping constructs


and conditional branching possible, the design
description essentially looks like a “C” program.
MODULE

 Any Verilog program begins with a keyword – called a


“module.”
 A module is the name given to any system considering it as
a black box with input and output terminals as shown in
Figure
 The terminals of the module are referred to as ‘ports’.
Cont
…
 The ports attached to a module can be of three types:
 input ports through which one gets entry into the module
 output ports through which one exits the module.
 inout ports: These represent ports through which one gets entry into
the module or exits the module

 All the constructs in Verilog are centred on the module.


MODULE SYNTAX

 module module_name (port_list);

Input, output, inout declaration


Intermediate variable
declarations

Functional Description
(gate / switch / data flow / Behv.)

endmodule
Module declaration

Module

Input
Circuit
X Wire

Y Output
Z
O
Module declaration

Module
Input
Circuit
X Wire
Y Output

O
Z

Module name

module

sample (X,Y,Z,O); input

X,Y,Z;
output O;

// Describe the circuit using logic symbols


endmodule
assign O = (X^Y)&Z;
SIMULATION AND SYNTHESIS TOOLS

 A variety of Software tools related to VLSI design is


available.

 Two of them are


- Modelsim and

- Leonardo Spectrum of MentorGraphics.

 Modelsim has been used to simulate the designs.

 Leonardo Spectrum has been used to obtain the


synthesized circuits
TEST BENCH SYNTAX

 A test bench is HDL code that allows you to provide


a
documented, repeatable set of stimuli.

 module tb_module_name ;

Input, output, inout declaration


Intermediate variable
declarations

Stimulus (initial /
LANGUAGE CONSTRUCTS AND
CONVENTIONS IN
VERILOG
 CASE SENSITIVITY

Verilog is a case-sensitive language like C

 KEYWORDS

 The keywords define the language constructs. A keyword


signifies an activity to be carried out, initiated, or
terminated

 All keywords in Verilog are in small letters


IDENTIFIERS

 IDENTIFIERS

 Any program requires blocks of statements, signals, etc.,


to be identified with an attached nametag. Such nametags
are identifiers

 All characters of the alphabet or an underscore can be


used as the first character. Subsequent characters can be of
alphanumeric type, or the underscore (_), or the dollar ($)
sign
WHITE SPACE CHARACTERS , COMMENTS

 WHITE SPACE CHARACTERS

 Blanks (\b), tabs (\t), newlines (\n), and form feed form

the white space characters in Verilog

 COMMENTS
 A single line comment begins with “//”
 multiline comments “/*” signifies the beginning of
a comment and “*/” its end.
NUMBERS, STRINGS

 NUMBERS
Integer Numbers : the number is taken as 32 bits wide.
 25, 253, –253
 - 8 'h h f 4

Real Numbers: Real numbers can be specified in decimal


or scientific notation
4.3, 4.3e2

 STRINGS : A string is a sequence of characters enclosed


within double quotes
 “This is a string”
LOGIC VALUES

 1 signifies the 1 or high or true level

 0 signifies the 0 or low or false level.

 Two additional levels are also possible designated as x and


z.
 x represents an unknown or an uninitialized value. This corresponds
to the don’t care case in logic circuits.

 z represents / signifies a high impedance state


STRENGTHS
Declaration
Strength Name Strength Element Modelled
Abbreviation
Level
Power supply connections. supply
Supply Drive 7 Default gate & assign output
strong
strength.
Strong Drive 6
Gate & assign output
pull
strength.
Pull Drive 5
Size of trireg net capacitor. large
Large Capacitor 4 Gate & assign output
weak
strength.
Weak Capacitor 3
Medium
2 Size of trireg net capacitor. medium
Capacitor
Small Capacitor 1 Size of trireg net capacitor. small
High Impedence 0 Not highz
Applicable.
Data
Types
 The data handled in Verilog fall into two categories:
(i) Net data type

(ii) Variable data type

 The two types differ in the way they are used as well as
with regard to their respective hardware structures.
Net data type

 A net signifies a connection from one circuit unit to another,


which carries the value of the signal it is connected to and
transmits to the circuit blocks connected to it.
 If the driving end of a net is left floating, the net goes to
the high impedance state.
 Various nets supported in Verilog
WIRE / TRI WAND / TRIAND
WOR / TRIOR TRI1
TRI0 TRIREG -- Infers
a capacitance
SUPPLY1 --
For Vdd SUPPLY0 -- For
Vss
DIFFERENCES BETWEEN WIRE AND
TRI
 wire: It represents a simple wire doing an interconnection.
Only one output is connected to a wire and is driven by that.

 tri: It represents a simple signal line as a wire. Unlike the


wire, a tri can be driven by more than one signal outputs.
Contention

WIR 0 1 X Z WAND 0 1 X Z
/
E TRI
/TRI AN
0 0 X X 0 D

1 X 1 X 1 0 0 0 0 0
X X X X X 1 0 1 X 1
Z 0 1 X Z X 0 X X X
Z 0 1 X Z
WOR 0 1 X Z
/ TRI1(0 0 1 X Z
TR )
IO 0 0 X X 0
R
1 X 1 X 1
0 0 1 X 0
1 1 1 1 1 X X X X X
X X 1 X X Z 0 1 X 1(0)
Z 0 1 X Z
Variable Data Type

 A variable is an abstraction for a storage device


 reg
 time
 integer
 real
 Realtime

 MEMORY

 Reg [15:0] memory[511:0];

 an array called “memory”; it has 512


locations.

 Each location is 16 bits wide


Scalars and
Vectors
 Entities representing single bits — whether the bit is
stored,
changed, or transferred — are called “scalars.”

 Multiple lines carry signals in a cluster treated as a


“vector.”

reg[2:0] b;

reg[4:2] c;

wire[-2:2] d ;

 All the above declarations are vectors.

 If range is not specifies it is treated as scalars


Parameters,
Operators.
PARAMETERS
All constants can be declared as parameters at the
outset in a Verilog module
 parameter word_size = 16;
 parameter word_size = 16, mem_size = 256;

OPERATOR
S – for example, ~a.
 Unary: – for example, a&b.
 Binary:
 Ternary: – for example, a?
b:c

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