Département d’Electronique Faculté de l’Ingénieur Département d’Electronique Faculté de l’Ingénieur Laboratoire Hyperfréquence& Semi-conducteur (LHS) Laboratoire Hyperfréquence& Semi-conducteur (LHS)
in Université Constantine1, Algérie Université Constantine1, Algérie bella.mourad@yahoo.fr latreche.saida@gmail.com
s. .re Abstract— We present in this paper the main results of a two- dimensional numerical study based on the finite difference
df method. The static current-voltage characteristics I(V) of a double gate MOS transistor (DGMOS) are compared with a
as single gate MOSFET with SOI (Silicon On Insulate) technology. For this, we use a self consistent calculation of Schrodinger-Poisson coupled equations with pseudo - 2D
. ib scheme. Simulation results show that the drain current values of the transistor DGMOS are higher compared with those of
dl the SOI MOS transistor. In addition, the DIBL effect and the leakage current are minimized in the case of DGMOS. This .e confirms the performances of the double gate transistor and its ability to better control the channel and thus the drain current. w Figure1. Schematic of double gate structure Keywords- single gate transistorMOSFET, double gate w
DIBL, self consistent, leakage current. We consider, in order to compare the electrical w
I. INTRODUCTION performances, a same transistor as the DGMOS structure
(same size, same features) but a single gate one (Fig. 2). The semiconductor industry is always looking for m
developing semiconductor technology to finer geometries [1,
2]. fro
The aim of the decrease in size of microelectronic
devices is to reduce the cost and to improve the performance devices, but this, however, leads to the occurrence of adverse d
effects. To minimize these latters, it is interesting to turn to
de
new transistor architectures such as double gate MOSFET
which is now proving to be a very promising alternative [3, 4, 5]. oa
II. STRUCTURE STUDIED
nl
The schematic description of double-gate MOS device is Figure2. Schematic of single gate structure with SOI technology shown in Fig.1. It has 10 nm gate length LG, the gate oxide ow
Tox and Silicon body thicknesses TSi are equal to 1.5 nm. The source and drain lengths LSD are equal to 5 nm. The doping density is N D = 10 20cm-3 in N+ source/drain regions and NA III. FUNDAMENTAL EQUATIONS =1010 cm-3 in the channel (P type). The work function of the D
The size reduction devices to nanometric sizes reveal
gate material considered is 4.46 eV to achieve the theoretical quantum phenomena, previously considered largely non- threshold voltage VT to 0.2V. existent or negligible. For this, it is necessary to use equations derived from quantum mechanics [6]. The most rigorous approach is to solve the Poisson and Schrödinger equations simultaneously to take into account the quantum phenomena.
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Proceedings of The first International Conference on Nanoelectronics, Communications and Renewable Energy 2013 400
d 2V ( x, y ) d 2V ( x, y ) ρ ( x, y ) (1) V. RESULTS AND DISCUSSIONS
2 + 2 =− dx dy ε 0ε r We have considered this model in order to develop our h2 d 2ψ ( y) Matlab code [9]. This modelisation was used to compare the − * + qV ( y )ψ ( y ) = Eψ ( y ) (2) both devices. Indeed, Figures 3 and 4 represent the current 2m dy 2 voltage characteristics ID (VDS) for single and double gate architectures simulated with LG = 10 nm respectively for TSi Where: ψ(y) is the wave function corresponding to the = 2 nm and 1.5 nm. eigenvalue E; V(y): the electrostatic potential and ρ(x) is the We observe an increase in the slope of the transistors charge density. (single gate and double gate) in the linear regime when the
in thickness TSi is reduced from 2 to 1.5 nm. We clearly see that the equations (1) and (2) are coupled. It is therefore self consistency in their resolution [7, 8, 9].
s. We can illustrate the self consistent system by the following one:
.re ρ ( y ) = S [V ( y )]
df as V ( y ) = P [ρ ( y )]
. Where: the functions S [V(y)] and P [ρ(y)] represent the
ib Schrödinger and Poisson equations.
dl IV. V ALIDATION MODEL .e Figure 3. ID vs.VDS for a gate voltage of 0.6V and thickness silicon of In order to validate the obtained results, we compare our 2nm w model with Sentaurus numerical simulation (ISE-TCAD software). w
The comparison between the modelled and simulated
characteristics gives good agreement for V GS down to 0.4 V. w
these devices are operated at VGS lower than 0.4 V (linear
regime), and therefore, the model is valid for the regimes of m
practical interest. fro d de oa
Figure 4. ID vs.VDS for a gate voltage of 0.6V and thickness silicon of
1.5 nm nl
The On-current ION (saturation current) is more important
ow
in the DGMOS compared with single gate transistor. Worth
2150 µA is for SOI MOS transistor and 2745 µA for DGMOS in the case of thickness silicon TSi=2nm. D
On the transfer characteristic ID (V GS) (fig. 5 and 6) we
Figure 11. Comparison of the output characteristics between simulation confirm the previous result [ION (DGMOS)>ION (SOI)]. program and ISE-TCAD
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Proceedings of The first International Conference on Nanoelectronics, Communications and Renewable Energy 2013 401
in s. .re Figure5. ID vs.VGS for a drain voltage of 0.6V and thickness silicon of Figure 8. I D (VGS) characteristics at VDS=0.6V and TSi =1.5 nm 2 nm
df The Off-current (IOFF) is significantly lower in the
as DGMOS than in the single gate. We can have a better control of the output current by considering DGMOS.
. Fig. 9 shows the evolution of the conduction band in the
ib DGMOS device (V GS=0V) for different drain voltage VDS=10mv, 0.2V and 0.6V with LG=10nm and TSi=1.5nm. Is
dl clearly shown the Drain Induced Barrier Lowering (DIBL). .e w w w
Figure 6. ID vs.VGS for a drain voltage of 0.6V and thickness silicon of
1.5 nm The figures 7 and 8 show the characteristics ID (V GS), in a m
semi-logarithmic scale, simulated with LG = 10 nm
respectively for TSi = 2 nm and 1.5 nm. fro d de
Figure 9. Conduction Band for differences drain voltage
oa
Fig 10.a and 10.b clearly illustrate that the DIBL effect is lower in DGMOS architecture. nl ow D
Figure 7. ID (V GS) characteristics at V DS=0.6V and TSi =2 nm
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Proceedings of The first International Conference on Nanoelectronics, Communications and Renewable Energy 2013 402
VI. CONCLUSION We have present in this paper a self-consistent Poisson and Schrödinger simulation. This method has allowed us to have significant results with good convergence. We have shown that for a small thickness of the active a) layer, a best performance is obtained with double gate transistor. More, the analysis of DIBL effect in both single and double gate transistors, confirms that the performances of double gate transistor are better.
in Finally, the comparison between our model and Sentaurus numerical simulation gives good agreement for
s. VGS down to 0.4 V.
.re REFERENCES
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