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    EXP1

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    janardhanan1711
    The document outlines an experiment to implement a 4-bit Ripple Carry Adder using Quartus Prime and ModelSim on a Cyclone V SoC FPGA. The experiment successfully demonstrated the addition of two 4-bit binary numbers with a carry-in, displaying the result on two 7-segment displays. The provided code includes modules for the Ripple Carry Adder, Full Adder, and 7-segment display decoder.

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    EXP1

    Uploaded by

    janardhanan1711
    2 views5 pages
    The document outlines an experiment to implement a 4-bit Ripple Carry Adder using Quartus Prime and ModelSim on a Cyclone V SoC FPGA. The experiment successfully demonstrated the addition of two 4-bit binary numbers with a carry-in, displaying the result on two 7-segment displays. The provided code includes modules for the Ripple Carry Adder, Full Adder, and 7-segment display decoder.

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    The document outlines an experiment to implement a 4-bit Ripple Carry Adder using Quartus Prime and ModelSim on a Cyclone V SoC FPGA. The experiment successfully demonstrated the addition of two 4-bit binary numbers with a carry-in, displaying the result on two 7-segment displays. The provided code includes modules for the Ripple Carry Adder, Full Adder, and 7-segment display decoder.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    2 views5 pages

    EXP1

    Uploaded by

    janardhanan1711
    The document outlines an experiment to implement a 4-bit Ripple Carry Adder using Quartus Prime and ModelSim on a Cyclone V SoC FPGA. The experiment successfully demonstrated the addition of two 4-bit binary numbers with a carry-in, displaying the result on two 7-segment displays. The provided code includes modules for the Ripple Carry Adder, Full Adder, and 7-segment display decoder.

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    © All Rights Reserved
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    Page 1 of 5

    EXPERIMENT -1
    RIPPLE CARRY ADDER

    VERIFICATION:

    AIM: To perform the Ripple Carry Adder experiment using Quartus Prime with
    the ModelSim simulation tool and the hardware 5CSXFC6D6F31C6 (Cyclone
    V SoC FPGA)

    Sailesh S 22BEC1177
    Page 2 of 5

    CODE:
    module RIPPLE_CARRY(a, b, cin, sum, cout, seg1, seg2);
    input [3:0] a, b;
    input cin;
    output wire [3:0] sum;
    output cout;
    output [6:0] seg1, seg2;

    wire cout1, cout2, cout3;


    FullAdder FA1(a[0], b[0], cin, sum[0], cout1);
    FullAdder FA2(a[1], b[1], cout1, sum[1], cout2);
    FullAdder FA3(a[2], b[2], cout2, sum[2], cout3);
    FullAdder FA4(a[3], b[3], cout3, sum[3], cout);

    wire [3:0] tens_digit, ones_digit;

    assign tens_digit = sum / 10;


    assign ones_digit = sum % 10;

    segment7 SEG1(tens_digit, seg1);


    segment7 SEG2(ones_digit, seg2);
    endmodule

    module FullAdder(a, b, cin, sum, cout);


    input a, b, cin;
    output wire sum, cout;
    wire s1, c1, c2, c3;

    Sailesh S 22BEC1177
    Page 3 of 5

    xor(s1, a, b);
    xor(sum, s1, cin);
    and(c1, a, b);
    and(c2, b, cin);
    and(c3, a, cin);
    or(cout, c1, c2, c3);
    endmodule

    module segment7(bcd, seg);


    input [3:0] bcd;
    output [6:0] seg;
    reg [6:0] seg;

    always @(bcd)
    begin
    case (bcd)
    4'b0000 : seg = 7'b0000001;
    4'b0001 : seg = 7'b1001111;
    4'b0010 : seg = 7'b0010010;
    4'b0011 : seg = 7'b0000110;
    4'b0100 : seg = 7'b1001100;
    4'b0101 : seg = 7'b0100100;
    4'b0110 : seg = 7'b0100000;
    4'b0111 : seg = 7'b0001111;
    4'b1000 : seg = 7'b0000000;
    4'b1001 : seg = 7'b0000100;
    default : seg = 7'b1111111;
    endcase

    Sailesh S 22BEC1177
    Page 4 of 5

    end
    endmodule

    OUTPUT:
    A=3 B=3 C=0  A+B+C=06

    A=7 B=5 C=0  A+B+C=12

    Sailesh S 22BEC1177
    Page 5 of 5

    RESULT: The experiment successfully implemented a 4-bit Ripple Carry Adder


    (RCA) with a 7-segment display decoder on an FPGA using Quartus Prime
    and ModelSim for simulation. The RCA correctly performed the addition of two
    4-bit binary numbers along with a carry-in input. The sum was displayed as a
    two-digit decimal value on two 7-segment displays.

    Sailesh S 22BEC1177

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