Computer Organization &

Architecture
Chapter 2
System Busses

By Bhushan Inje
Outline
• Computer Components
• Computer Function
• Instruction Fetch and Execute
• Interrupts
• I/O Function
• Interconnection Structures
• Bus Interconnection
• Bus Structure
• Multiple-Bus Hierarchies
• Elements of Bus Design
Von Neumann architecture

• Data and instructions are stored in a single read–write memory.

• The contents of this memory are addressable by location, without

regard to the type of data contained there.

• Execution occurs in a sequential fashion (unless explicitly modified)

from one instruction to the next.
 Program Concept

• The entire program is actually a sequence of steps.

• At each step, some arithmetic or logical operation is
performed on some data.
• For each step, a new set of control signals is needed.

• Programming is now much easier. Instead of

rewiring the hardware for each new program, all
we need to do is provide a new sequence of
codes.
• Each code is, in effect, an instruction, and part of
the hardware interprets each instruction and
generates control signals.
 Computer Function

• The basic function

performed by a computer is
execution of a program,
which consists of a set of
instructions stored in
memory.
• The processor does the actual
work by executing
instructions specified in the
program.
Computer Function
• Execution of program which consists of set of instructions
stored in memory.
• Processors does not actual work by executing instruction
specified in the program.
• Instruction processing consist of two steps:
• The processor reads(fetches) instruction from memory.
• Execute each instruction.
• Processing require for single instruction is called an
instruction cycle.
Instruction Cycle

• Two steps:
• Fetch cycle
• Execute cycle
Fetch Cycle

• Program Counter (PC) holds address of next instruction to fetch

• Processor fetches instruction from memory location pointed to by PC
• Increment PC
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs required actions
Execute Cycle
• Processor-memory
• data transfer between CPU and main memory
• Processor I/O
• Data transfer between CPU and I/O module
• Data processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations
• e.g. jump
• Combination of above
Example of Program Execution
Example of Program Execution
• Step 1. The PC contains 300, the address of the first instruction. This
instruction (the value 1940 in hexadecimal) is loaded into the instruction
register IR, and the PC is incremented. Note that this process involves the
use of a memory address register and a memory buffer register. For
simplicity, these intermediate registers are ignored.
• Step 2. The first 4 bits (first hexadecimal digit) in the IR indicate that the
AC is to be loaded. The remaining 12 bits (three hexadecimal digits)
specify the address (940) from which data are to be loaded.
• Step 3. The next instruction (5941) is fetched from location 301, and the
PC is incremented.
• Step 4. The old contents of the AC and the contents of location 941 are
added, and the result is stored in the AC.
• Step 5. The next instruction (2941) is fetched from location 302, and the
PC is incremented.
• Step 6. The contents of the AC are stored in location 941.
Instruction Cycle State Diagram
• The states can be described as follows:
• Instruction address calculation (iac): Determine the address of the next instruction to be
executed. Usually, this involves adding a fixed number to the address of the previous instruction.
For example, if each instruction is 16 bits long and memory is organized into 16-bit words, then
add 1 to the previous address. If, instead, memory is organized as individually addressable 8-bit
bytes, then add 2 to the previous address.

• Instruction fetch (if): Read instruction from its memory location into the processor.

• Instruction operation decoding (iod): Analyse instruction to determine type of operation to be

performed and operand(s) to be used.

• Operand address calculation (oac): If the operation involves reference to an operand in memory
or available via I/O, then determine the address of the operand.

• Operand fetch (of): Fetch the operand from memory or read it in from I/O.

• Data operation (do): Perform the operation indicated in the instruction.

• Operand store (os): Write the result into memory or out to I/O.
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing
• Program
• e.g. overflow, division by zero
• Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
• I/O
• from I/O controller
• Hardware failure
• e.g. memory parity error
Interrupts Cont…
• Interrupts are provided primarily as a way to improve
processing efficiency.
• For example, most external devices are much slower than the processor.
Suppose that the processor is transferring data to a printer using the
instruction cycle scheme After each write operation, the processor must
pause and remain idle until the printer catches up.

• The length of this pause may be on the order of many hundreds

or even thousands of instruction cycles that do not involve
memory. Clearly, this is a very wasteful use of the processor.
Program Flow Control
Program Flow Control

“Because the I/O operation may take a relatively long time to

complete, the I/O program is hung up waiting for the operation to
complete; hence, the user program is stopped at the point of the
WRITE call for some considerable period of time.”
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
• Suspend execution of current program
• Save context
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Instruction Cycle (with Interrupts) - State Diagram
Multiple Interrupts

• Disable interrupts
• Processor will ignore further interrupts whilst processing one interrupt
• Interrupts remain pending and are checked after first interrupt has been
processed
• Interrupts handled in sequence as they occur
• Define priorities
• Low priority interrupts can be interrupted by higher priority interrupts
• When higher priority interrupt has been processed, processor returns to
previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
INTERCONNECTION STRUCTURES
• A computer consists of a set of components or modules of three
basic types (processor, memory, I/O) that communicate with each
other.
• In effect, a computer is a network of basic modules. Thus, there must
be paths for connecting the modules.
• The collection of paths connecting the various modules is called the
interconnection structure.
• The design of this structure will depend on the exchanges that
must be made among modules.
Computer Modules
• Figure suggests the types of exchanges that are needed by indicating the major
forms of input and output for each module type.
• Memory:
• Typically, a memory module will consist of N words of equal length.
• Each word is assigned a unique numerical address (0, 1, …, N - 1).
• A word of data can be read from or written into the memory.
• The nature of the operation is indicated by read and write control signals.
• The location for the operation is specified by an address.
Computer Modules Cont..

• I/O module:
• From an internal (to the computer system) point of view, I/O is functionally
similar to memory.

• There are two operations, read and write.

• Further, an I/O module may control more than one external device.

• We can refer to each of the interfaces to an external device as a port and give
each a unique address (e.g., 0, 1, …, M - 1).
Computer Modules Cont..
• Processor:
• The processor reads in instructions and data, writes out data after
processing, and uses control signals to control the overall operation of the
system.
• It also receives interrupt signals.
Computer Modules Cont..
• The preceding list defines the data to be exchanged. The
interconnection structure must support the following types of
transfers:
• Memory to processor: The processor reads an instruction or a unit of
data from memory.
• Processor to memory: The processor writes a unit of data to memory.
• I/O to processor: The processor reads data from an I/O device via an I/O
module.
• Processor to I/O: The processor sends data to the I/O device.
• I/O to or from memory: For these two cases, an I/O module is allowed
to exchange data directly with memory, without going through the
processor, using
direct memory access.
Buses Interconnection
• There are a number of possible interconnection systems
• Single and multiple BUS structures are most common
• e.g. Control/Address/Data bus (PC)
Bus Structure

• There are 3 types of buses

• Address Bus

• Data Bus

• Control Bus
Data Bus
• Carries data
• Remember that there is no difference between “data” and “instruction” at
this level

• Width is a key determinant of performance

• 8, 16, 32, 64 bit
Address bus

• Identify the source or destination of data

• e.g. CPU needs to read an instruction (data) from a given location in

memory

• Bus width determines maximum memory capacity of system

• e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus
• Control and timing information
• Memory read/write signal

• Interrupt request

• Clock signals
Bus Interconnection Scheme
• Memory write: causes data on the bus to be written into the addressed location

• Memory read: causes data from the addressed location to be placed on the bus

• I/O write: causes data on the bus to be output to the addressed I/O port

• I/O read: causes data from the addressed I/O port to be placed on the bus

• Transfer ACK: indicates that data have been accepted from or placed on the bus

• Bus request: indicates that a module needs to gain control of the bus

• Bus grant: indicates that a requesting module has been granted control of the bus

• Interrupt request: indicates that an interrupt is pending

• Interrupt ACK: acknowledges that the pending interrupt has been recognized

• Clock: is used to synchronize operations

• Reset: initializes all modules.

Single Bus Problems

• Lots of devices on one bus leads to:

• Propagation delays
• Long data paths mean that co-ordination of bus use can adversely affect performance

• If aggregate data transfer approaches bus capacity

• Most systems use multiple buses to overcome these problems

Traditional (ISA) (with cache)
High Performance Bus
ELEMENTS OF BUS DESIGNS

1) Bus Types
2) Method of Arbitration
3) Timing
4) Bus Width
5) Data Transfer Type
6) Block Data Transfer
Bus Types
A) Dedicated
•A line is permanently assigned either to one function.
•An example of functional dedication is the use of separate
dedicated address and data line.
B) Multiplexed
•Using the same lines for multiple purpose.
•Eg:- Address and data information may be transmitted over the
same set of lines.
•At the beginning of the data transfer the address is placed on
the bus and the address valid line is activated.
•The address is then remove from the same bus line is used for
data transfer.
C) Physical Dedication
•The use of multiple buses,each of which connects to only a
subset of modules.
Bus Arbitration
•Determining who can use the bus at a particular time.
A) Centralized
•A single hardware device called the bus controller or arbiter
allocate time on the bus.
•The device may be a separate or a part of a processor.
B) Distributed
•There is no centralized controllers.
•Each module contains assess control logic and the modules act
together.
Methods of Centralized BUS Arbitration –

•
There are three bus arbitration methods:
• (i) Daisy Chaining method –
• Advantages –

• Simplicity and Scalability.

• The user can add more devices anywhere along the chain, up to a
certain maximum value.

• Disadvantages –

• The value of priority assigned to a device is depends on the position

of master bus.

• Propagation delay is arises in this method.

• If one device fails then entire system will stop working.

• (ii) Polling or Rotating Priority method –
• Advantages –

• This method does not favor any particular device and processor.

• The method is also quite simple.

• If one device fails then entire system will not stop working.

• Disadvantages –

• Adding bus masters is difficult as increases the number of address

lines of the circuit.
• (iii) Fixed priority or Independent Request method –
Timing
• Co-ordination of events on bus
• Synchronous
• Events determined by clock signals
• Control Bus includes clock line
• A single 1-0 is a bus cycle
• All devices can read clock line
• Usually sync on leading edge
• Usually a single cycle for an event
Synchronous Timing Diagram
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
4) Bus Width
•The width of data bus has an impact on the databus has an
impact on the system performance.
•The wider data bus, the greater number of bit transferred at
one time.
•The wider address bus, the greater range of location that can be
referenced.
5) Data Transfer Type
•Read-Modify-Write : A read followed immediately by a write
to the same address.
•Read-After-Write : Consisting of a write
followed immediately by a read from the same address (for error
checking purposes).
6) Block Data Transfer
•One address cycle followed by n data cycles.
•First data item to or from specified address.
•Remaining data items to or from subsequent addresses.