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ModelSim Datasheet

ModelSim is a powerful HDL simulation tool from Siemens that offers advanced verification capabilities for VHDL, Verilog, and SystemVerilog designs. It features a user-friendly GUI, integrated project management, and supports various simulation modes, making it suitable for small to medium-sized FPGA designs. The tool also includes code coverage metrics and assertion-based verification options to enhance design quality and debug productivity.

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10 views3 pages

ModelSim Datasheet

ModelSim is a powerful HDL simulation tool from Siemens that offers advanced verification capabilities for VHDL, Verilog, and SystemVerilog designs. It features a user-friendly GUI, integrated project management, and supports various simulation modes, making it suitable for small to medium-sized FPGA designs. The tool also includes code coverage metrics and assertion-based verification options to enhance design quality and debug productivity.

Uploaded by

mentronix.drive
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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HDL Simulation

ModelSim in one design. Its architecture allows


platform-independent compile with the
outstanding performance of native
compiled code. The graphical user
interface is powerful, consistent, and
intuitive. All windows update automati-
Verification and simulation tools from Siemens cally following activity in any other
Digital Industries Software window. For example, selecting a
design region in the structure window
automatically updates the source, sig-
nals, process, and variables windows.
Benefits Sophisticated FPGA Verification You can edit, recompile, and re-simu-
• Native compiled, single kernel ModelSim® packs an unprecedented late without leaving the ModelSim
simulator technology level of verification capabilities in a environment. All user interface opera-
cost-effective HDL simulation solution. tions can be scripted and simulations
• VHDL, Verilog, and SystemVerilog
In addition to supporting standard can run in batch or interactive modes.
design constructs
HDLs, ModelSim increases design qual-
• Intelligent, easy-to-use GUI with ModelSim simulates behavioral, RTL,
ity and debug productivity.
Tcl interface and gate-level code, including VHDL
ModelSim’s award-winning single ker- VITAL and Verilog gate libraries, with
• Integrated project management, nel simulator (SKS) technology enables timing provided by the standard delay
source code templates, and transparent mixing of VHDL and Verilog format (SDF).
wizards
• Wave viewing and comparison;
objects, watch, and memory win-
dows increase debug productivity
• Code coverage
• Standard support for
Xilinx® SecureIP
• SystemC option available
• SVA and PSL assertions

ModelSim offers the most verification capabilities in its class.

www.siemens.com/eda
SIMULATION AND
VERIFICATION
HDL Simulation – ModelSim

A More Intelligent GUI saving the time-consuming step of ini-


An intelligently engineered GUI makes tializing sections of testbenches just to
efficient use of desktop real estate. load memories. All functions are avail-
ModelSim offers a highly intuitive able via the command line, allowing
arrangement of interactive graphical ele- their use in scripting.
ments (windows, toolbars, menus, etc.),
making it easy to view and access the Waveform and Results Viewing
many powerful capabilities of ModelSim. ModelSim provides a high performance,
The result is a feature-rich GUI that is full-featured Wave window. The Wave
easy to use and quickly mastered. window provides cursors for marking
ModelSim redefined openness in simula- interesting points in time and measur-
tion by incorporating the Tcl user inter- ing the time distance between cursors.
face into its HDL simulator. Tcl is a simple Wave window contents can be format-
but powerful scripting language for con- ted flexibly through powerful virtual
trolling and extending applications. signal definitions and grouping.

The ModelSim GUI delivers highly pro- Waveform comparisons are easily per-
ductive design debug and analysis capa- formed between two simulation results.
bilities as well as project and file Timing differences between RTL and Source Window Templates & Wizards
management. gate-level simulation results are easily VHDL and Verilog templates and wiz-
handled through user-specified time-fil- ards allow you to quickly develop HDL
Memory Window tering capabilities. code without having to remember the
The memory window allows intuitive exact language syntax. All the language
ModelSim provides a unique WLF
and flexible viewing and debugging of constructs are available with a click of a
management utility (aka WLFMAN)
design memories. mouse. Easy-to-use wizards step you
that allows the manipulation of WLF
VHDL and Verilog memories are auto- result files, enabling you to specify through creation of more complex HDL
extracted from the source and viewed the amount of information to record blocks. The wizards show how to create
in the GUI, allowing powerful search, to a WLF file or to subset an existing parameterizable logic blocks, testbench
fill, edit, load, and save functionality. WLF file based on signals or time. stimuli, and design objects. The source
The Memory window supports pre-load- The WLFMAN utility allows efficient window templates and wizards benefit
ing memories from a file or using con- management of disk space and post- both novice and advanced HDL develop-
stant, random, and computed values, simulation debug efficiency. ers with time-saving shortcuts.
SIMULATION AND
VERIFICATION

Project Manager
The project manager greatly reduces
the time it takes to organize files and
libraries. As you compile and simulate,
the project manager stores the unique
settings of each individual project,
allowing you to restart the simulator
right where you left off. Simulation
properties allow you to easily re-simu-
late with pre-configured parameters.

Code Coverage
Design verification completeness can
be measured through code coverage.
ModelSim supports statement, expres-
sion, condition, toggle, and FSM cover-
age. Code coverage metrics are
automatically derived from the HDL
source. As many design blocks are
created to be configurable and reusable Using integrated code coverage, ModelSim tracks how much of the design has been tested.
and not all metrics are valuable, code
coverage metrics can be flexibly Powerful, Cost-Effective Simulation
managed with source code pragmas ModelSim delivers a powerful simula-
and exclusions specified in the code tion solution ideally suited for the
coverage browser. verification of small and medium sized
FPGA designs; especially designs with
Assertion Based Verification complex, mission critical functionality.
ModelSim delivers a comprehensive,
standards-based assertion based Platform Support
verification (ABV) solution, offering ModelSim is supported on 32/64-bit
the choice of SystemVerilog Assertions Windows 10, Linux RHEL6 and RHEL7,
(SVA), Property Specification Language and Linux SLES 11 and SLES 12 based
(PSL), or both. platforms. When running on a 64-bit
system, ModelSim runs in 32-bit mode.

Siemens Digital Industries Software


www.siemens.com/eda

Americas +1 314 264 8499


Europe +44 (0) 1276 413200
Asia-Pacific +852 2230 3333

© Siemens 2019. A list of relevant Siemens trademarks


can be found here. Other trademarks belong to their
respective owners.
78330-C2 9/19 M/TGB

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