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21VD104 - Cad For Vlsi Set 1

This document is an examination question paper for the M.E Degree in VLSI Design at Sri Shakthi Institute of Engineering and Technology, covering various topics related to CAD for VLSI Circuits. It includes multiple parts with questions ranging from fill-in-the-blanks and true/false to detailed explanations of algorithms and concepts. The paper is structured into four parts, with a total of 100 marks available.

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narmathaaiml
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13 views4 pages

21VD104 - Cad For Vlsi Set 1

This document is an examination question paper for the M.E Degree in VLSI Design at Sri Shakthi Institute of Engineering and Technology, covering various topics related to CAD for VLSI Circuits. It includes multiple parts with questions ranging from fill-in-the-blanks and true/false to detailed explanations of algorithms and concepts. The paper is structured into four parts, with a total of 100 marks available.

Uploaded by

narmathaaiml
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Reg. No.

Question Paper Code :21N24759


SRI SHAKTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY
COIMBATORE – 641 062
(Autonomous Institution)

M.E DEGREE EXAMINATION, NOV/DEC 2024

First Semester
21VD104 CAD for VLSI Circuits (Regulation 2021)
VLSI Design
Time : Three Hours Maximum : 100 Marks
PART – A (Answer ALL questions) (20*0.5=10 Marks)
1. Name the powerful tool used to illustrate different design methodologies.

2. Increasing the testability of a chip implies an increase in its area. True / False?

3. Design methods with limited freedom are referred to by the term __________.

4. Expand the term FPGA.


_________ is concerned with the generation and optimization of a circuit at the level of
5.
boolean gates.
6. Name any one of the verification methods.
A graph that can be drawn on a two dimensional plane without any pf its edges
7.
intersecting is called ______.
8. ________ is a connected graph without cycles.
The mask patterns that are used for the fabrication of an integrated circuit have to
9. obey certain restrictions on their shapes and sizes, these restrictions are known as
__________.
10. Mention anyone placement algorithm.

11. Min cut placement is a top down method. True / False?

12. In floor planning, the cells that are made from the leaf cells are called _______.

13. In floor planning, the lowest level of cells is called as ________.


14. Write about the first stage of routing.

15. Give the other name for detailed routing.

16. Name anyone parameter that define routing.

17. __________ type of simulation is the best choice for synchronous circuits.
18. In event driven simulation, a change occurred in a signal is known as ________.

1
19. Expand the term ROBDD.
20. Scheduling is one of the task involved in actual mapping. True / False?

PART – B (Answer ALL questions) (5*2=10 Marks)

21 List the types of minimum distance rules.

22 Define tractable and intractable problems.

23 Name the parameters characterizing the local routing problem.

24 How is routing performed in standard cell layout?

25 What are the goals of high level synthesis?

PART – C (Answer any five questions) (5*14=70 Marks) Marks

26 (i) Explain the various design domains of Gajski’s Y-chart in detail. 7

(ii) Explain a suitable data structure for representation of a graph. 7

27 (i) Explain Prim’s algorithm for minimum spanning trees. 7

(ii) Explain the sequence of actions involved in structural and logical design, layout 7
design of an integrated circuit.
28 (i) Describe the concepts of Floor planning. 7

(ii) Distinguish between the types of placement algorithms. 7

29 (i) Write algorithms used for Area routing. 7

(ii) Write the Efficient Rectilinear Steiner-tree Construction algorithm for global 7
routing.

30 (i) Explain the principle and implementation of ROBDD in detail. 7

(ii) Explain the optimization issues and formulation of assignment problem. 7

31 (i) Explain Breadth-first search algorithm along with necessary pseudo-code. 7

2
(ii) Explain compiler driven simulation and its applications. 7

32 (i) Explain the concepts of linear programming with suitable expressions. 7

(ii) With suitable diagrams explain the types of data flow graph. 7

PART – D (Answer the questions) (1*10=10 Marks)

33 (i) Explain Liao-Wong algorithm for constraint-graph compaction along with


pseudo code in detail.
(OR)
(ii) Explain in detail about Assignment using clique partitioning .

3
Part A : Questions should be Fill in the blanks, True or False, Choose the correct and
matching.

Bloom’s Taxonomy Level (BTL)

Part A
QP No 1 2 3 4 5 6 7 8 9 10
BTL K2 K1 K1 K2 K1 K2 K1 K1 K2 K1
QP No 11 12 13 14 15 16 17 18 19 20
BTL K2 K1 K2 K1 K2 K1 K2 K1 K1 K2
Part B
QP No 21 22 23 24 25 - - - - -
BTL K2 K1 K2 K2 K1 - - - - -
Part C
QP No 26(i) 26(ii) 27(i) 27(ii) 28(i) 28(ii) 29(i) 29(ii) 30(i) 30(ii)
BTL K2 K1 K2 K1 K3 K1 K5 K1 K3 K6
QP No 31(i) 31(ii) 32(i) 32(ii) - - - - - -
BTL K2 K3 K6 K5 - - - - - -
Part D
QP No 33(i) 33(ii) - - - - - - - -
BTL K4 K1 - - - - - - - -

BTL Remember Understand Apply Analyze Evaluate Create


(K1) (K2) (K3) (K4) (K5) (K6)
Percentage of
18% 30% 20% 12% 10% 10%
Questions

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