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COA_syllabus

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12 views3 pages

COA_syllabus

Uploaded by

ashwinpatani.ce
Copyright
© © All Rights Reserved
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INDUS INSTITUTE OF TECHNOLOGY& ENGINEERING

Constituent Institute of Indus University

Subject: Computer Organization and Architecture


Program: CE/IT/CS Subject Code: CE0417 Semester: III
Teaching Scheme (Hours per week) Examination Evaluation Scheme (Marks)
Continuous Continuous
University University Internal Internal
Lecture Tutorial Practical Credits Theory Practical Evaluation Evaluation Total
Examination Examination (CIE)- (CIE)-
Theory Practical
3 0 0 3 40 0 60 0 100

Course Objectives
 To conceptualize the basics of organizational and architectural issues of a digital computer.
 To analyze performance issues in processor and memory design of a digital computer.
 To understand various data transfer techniques in digital computer.
 To analyze processor performance improvement using parallelism.

CONTENTS

UNIT-I

Basic Computer Organization and Data Representation [12 hours]

Overview of computer organization, CPU organization components classification


of computer architecture, Register, types of register, Bus, types of bus, quantitative
techniques in computer design, measuring and reporting performance, Amdahl’s
Law, number system, fixed point representation, floating point representation.

UNIT-II

Instruction Set Architecture [12 hours]

Instruction, instruction format, instruction execution cycle, instruction timing


cycles, ISA, ISA design issue, types of ISA, Accumulator organization, stack
organization, memory-memory organization, register memory organization,
register-register organization, addressing mode, RISC, CISC,8085 microprocessors,
Architecture, Operations of 8085, Instruction Set for 8085, Addressing Modes of
8085.
UNIT-III
Pipeline [12Hours]

What is pipeline, Flynn's taxonomy for Parallel Processing, types of pipeline,


Arithmetic Pipeline, Instruction Pipeline, measuring performance of pipeline, types
of hazard, structural hazard, data hazard, control hazard, method for avoiding hazard,
Vector Processing, Array Processors, Parallel Processing

UNIT-IV
Memory Organization [12 Hours]

Memory Hierarchy, types of memory, Main Memory, Auxiliary Memory, Inclusion,


Coherence and locality properties, Cache Memory, Organization of cache memory,
performance of cache memory with examples, cache memory mapping algorithms,
cache optimization techniques, Virtual Memory, demand paging, page replacement
algorithms.

Course Outcomes

At the end of this subject, students should be able to:


After successful completion of the course, student will able:

1. To understand and describe the basics of various architectural units of the


Computer System
2. To apply the knowledge of combinational and sequential logical circuits to
mimic a simple computer architecture
3. To demonstrate the simulations for basic computer operations
4. To recognize the importance of parallelism in computer architecture
5. To understand the basic working of various memory system.
6. This course is the bridge between digital electronics and microprocessor.

Text Books:
1. Computer system Architecture Mano, M. Morris Pearson publication
2. Computer Architecture and Organization Ghoshal, Subrata Pearson
publication
Reference Books:
1. Carl Hamacher -Computer Organization, Fifth Edition, Tata McGraw Hill.
2. John P Hayes -Computer Architecture & Organization–McGraw Hill
3. William Stallings-Computer Organization and Architecture, Seventh
Edition, Pearson Education
Web Resources

https://nptel.ac.in/courses/106/105/106105163
https://www.youtube.com/channel/UC2GUBG_WsP0OO5tXXocwp3Q/videos

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