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The document outlines a syllabus for a course on digital computers, covering topics such as computer organization, design, microoperations, and arithmetic operations. It includes details on input/output systems, memory hierarchy, and control units, as well as concepts related to reduced instruction set computers and multiprocessing. The syllabus emphasizes the structure and functioning of digital systems, including the role of registers and bus systems in data transfer and processing.
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0% found this document useful (0 votes)
9 views40 pagesCOA unit 1
The document outlines a syllabus for a course on digital computers, covering topics such as computer organization, design, microoperations, and arithmetic operations. It includes details on input/output systems, memory hierarchy, and control units, as well as concepts related to reduced instruction set computers and multiprocessing. The syllabus emphasizes the structure and functioning of digital systems, including the role of registers and bus systems in data transfer and processing.
Uploaded by
priyakumari97082Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 40
_ COP SYLLABUS,
anes eS — a
ee “Topics eee [ate
Uait-1i- Digital computers | |
' tndvoduetton 25 [ogfaaz|
a
3.
Def ination of computer Organigatton as |04/acaa
4 computer oesign and Avchitectuye 03 /9g/a0a3
| Registes Transfex language and os fiola 623!
| Micyo operations : |
|
Block dtagyam of Digital compute as}oq]a0a3 |
|
| Register Transfew language os |t0/avaz |
| Register Transfer os fio facgs |
| Bus and memoxy Transtexs 10 [10 J90Q3 |
| Arithmetic Micro operations |
| (09°C ratcro opexations |
6 Shift Micro operations |
1 Atthmetic logte Shift unit |
Basic computer Organtzaton |
and pesign: |
instruction codes ee
2 | computer Registers computer
insteuctions
0a{t1/a0a3 HW of WwW &
fw w&
l
| Input and outpul and interrupt
| pata Transfer and manipulalton
Timings andl contsol
instauctton cycle
memosy Reference instsuctions
OnMit- lL Microprogranmed contol!
Conta! memosy
Address Sequencing
Micyd progam example
vestgn of contsol unit
central processing unit: |
Beneral Register oxgantgatton
instruction Formats |
Adasessing races |
pwogsam contaol
unrrute bata Repvesemtation '
Data types
complements
Fixed point Represerrtatton
Floating potnl Repyeserrtatfon
computer Artth metic:
ob (alaoa3
07] ]90Q3 |
| o+/u]aoa3
| 09(i]a0a3
13 ]2023
13 (112023
qu] aaa
16 (4) 093
a(ulacaz
a9 (1/2033
| oul] aaa
Ghia|ang3
agzlia}aoa3
Add tion and substaction
06 (laa |
ul) 2093 | | Mudliplrcation Algosrthrs
3 | Diveston Algosithms © 92/12]2033 |
Floating-point Aatthmettc 28/12 )Q0az
operations I]
S Decimal Arthmetic unit
€ Decimal Ayithme??¢ opexations |
| bmit-ivi input-output organtzatton: 30 [12]2023 ||
| & input -output interface 1olorfacau |
2 Asynchyonous clatatwansfer to(orfacau. ||
3 Mocles of Teanster
4 priosity intersup} otsect uforfaoau., ||
mMemosy Access I
Memozy osganigzation ? {|
c 3 Bk
Memory Htexarchy 30[1aJacaa
2 Matn Memosy
Auxtliasy memory o3loilaoay, |
u_ Assoctate Memory | 1 |
5 Cache Memory rolo'Javuau.
unit-v: Reduced instuct?on
set computer : | [|
(else charactesistics valoijacau
2 RSC chasactertstics ya tot] 20au woman
2 nt BD,
(| pawalle! processing
pipelining
| Pipeline and vector processing.
2
3 | tithmetic pipeline
4 Insbuctton pipeline
S RISC pipeline
6 vectow processing
y Array processoy
mult? processovs *
t chaxactertst?cs of Multiproces-
~ SONS.
2 interconnection Structures
3. Intexprocessoy arbitvation
(4 Intewprovessor communication
| and synchroniaation
| & cache coherence.
12/01 )Q0QU |
17-/01)20au
PrJor}acau ||
Itoi) rau ||
zJoi}avau
17Jo1facay. |
30(01]acau
Qo(o1/d0au
25/orfaray
av)or Jaoau
|
as] fag |
a /o /a0an,
|
|
2/01 aeay
as |i /a0ag | | eel
|
| wae
|
\
{
| Digital computer Inbrocluctton $- :
ON ee
| A Digital computes can be considered 05 a bigttal
) in tate 190 and was primasily used From numesical
Date s- 8S orbs
umitel - @igital Computer, oO Day ‘Monday
Electvonic pevice that pexforms vastous computation,
~al tasks.
R the Fixst Clectvonte digital computer was developed
computatfonal. Cor] Computations.
# Which ts used 40 peafosm any of the operation only
In binary language.
# Te digital computes Block Diagsam ts as shown
below
input reo | | —] output |
D invpur unit i
wae on
a This unit ts responsible tos given the data to the
central processing uatt (CPU.
Example :- Keyboard, mouse, Camera, Scanner
: eetba me iy rOCeSS
ag mty unit 15 responstble dor showing the P
data which ts cone by centwal processing unit Lepy | Examples 4 S- speaker, Monitos, parnter.
Mone Pp Pp
> central processing uort unit [CPU] =
wee
& ae processing unit 1s athe bvatn oF Computer,
which ts used to process the infomation given by
input unit and give the process infosmatton to the
| output unit
& The cpu consists of thsee main blocks
|) Aku
> cv
i» MU
d} AuithmediC K ogic unid unit [ALDI -
[# THIS penenctn ts responsible for perfosming Axtthme-
|-tte and sogical operations:
| Arsthmetic operations Such as?
it Adattion C+]
8 substeaction C~J
\* multiplication (J
# piviston 0/7
* logical operations such as.’
x And CFI
* Ov Caj
1g alor Ce]
iia tare Was ¢ | 2 contwol unit Coud-
a
it 15 used to perform the operation
% contol unt
| 40 ahtch the system was need 40 be given and
m the Input
alt the data need to be Flow to
| unte--to the output uate
[> Memory voxtt fran] +
X Memory unit i$ used to stoxe the process data
and input unit data into tt.
4 €xamples i- Secondasy Memosy, paimary Memosy,
Register and cache.
Dole 26 /09]a0a3
Day i ‘Tues.
Computer organrgation, ;- Vine
‘Tie way haxdwase components operate and the coay
they axe connected together +0 form “the computer system
‘THe vastous components are assumed to be fn place and
the task 15 to investigate the ovganigational structure
| 40 vertty that the computer parts operate as intended.
1S concerned with the structure and behaviour of -the
computes as geen by the user :
1 includes the infomation. formats the Instuctton set
and techniques for addvessing memory.
concerned eotth the spectrcations ofthe vavtous Junctio-
|-RAl modules [ex + processovs and memos?es], | Digttal Electronics -
ane
digital electronics #8 th
that are used to process and contv0! digtta j
contrast to analog electvontcs » where iuntormatton fs
‘ fgttal
Yepresentecl by a continuously varying vortage « dty ta
signals ave repsesented by 40 dtucrete voltages os
togrc levels.
common BUS operal?ons i
INNO bn
¢ study of electronic Clacutts
| signals. in
| common bus operations refer fo the standard and
Soutine functions tvalved in the opevatton of buses
within a public transportation system. mese operations
eMcornpass acttyites such as scheduling + routing + axe
cowtectton » matntenance :dxtvex -tratning . Satery
measures, customer service svehfele management,
accesstbtltty ,and vaxtous other tasks that collectively
ensure the efftetent and effective provision of bus
Seweces to the public.
ce tek prgeing DevIYO/ Deke 03 JouJaoas
Seu ip Levé Raabe Day tweada
Ow ws ¢
i peripherals
cornmunsiation tines Structure of CPU
ON or
conn) )
anit
conto! und \
at % 4 \
seguenctng |
|
|
|
|
[® computer pestgntng structure p> -
\ 'n whICh components
pata eet Pepa ne deat ing
Yystem ata time and they are
different type ot issue at citferent leyel Ot each
| tevel the cestgner fs concerned- wrth Stuctire and
-function . he Structure ts-the skeleton oF vartous
Component related to each other Yor cornmunicationy : utey
Following are the Msu es in the rah aaa
aw av
Onno
Designing i-
X 4% Asumplton of infinite Specd
at Assumplion of inefpntie memory
4 Speed mumatch between memory BP Processor
x tlandling of bugs and ervor
& Multeple processor
*% multiple thread
Shade Memory
¥ OFS axicess (ax)
#% Better perfomance
4 part tom that we have 3 ma?n tssues
compatability
® user txpestence
Datle 1 05 /10/aoaa
D Securtty .
| ; “v Day i Thursday
Registered d
operations 5-
S. ,
Is A ofgital system in interpre tat
that accornpol th a
fon of digital
specitic tntormation
processing tas!
> the Modulus / Hardware or consteucted From pigita!
components Such as Flip Flops, vEGiSTCES » De coclexs al)
| avsthmettt elements and conted! lagics «
| > The vartous modulus ave talestonnected wrth lornrra
| pata ond controlpath to form a digital computer
| system,
|> ofgital modulus ave the bul defined by 7h registers
| theycontatn und the operation tha # ave perform on tne
| data stoyed nn thewt.
|> The operation executed onthe data stored tnthe
| vegtsters are calted the Micro operatttons
[<> The vesurt of the operatton may replace the previous
fnary [opevattons)* intormation ofa register. axe
| may be transfered to another register
| Example + Shift, clear. toad and count.
|= Te internal havdwaxe oxgantaation of a digital
computer *s best defined by the specttied .
|) the set of vegftters I contains and there func-
fons
® The Sequence of microoperations performs on the
Pnary intosmatton, Stored in the registers
2) The contolled that inittates the Sequence of
micro operatfons.
Regestey Transfered Layguage [ert]
> Me Symbolte notatton used to desertbhe -the pitcro
operation Tranifors amount vegtiters ts Called
RTL J mn for expressing 1” Lym by)
|=) The RTL 18 a Jyste
among the
form the microoperation Sequence
Registers of a digital modules
3 The RTL ts an approprtate tool -for explatning
“the begital computer internal organtaat ton
Regier red anne” RAT ye
computer Registered ave destgnated someting!
toliowed by numerttal denote the fancton v4
vegrsters
Example !- mar[ memovg Address Regtster]
{ pc £ program counter]
| aR C instruction Registed ]
; Ri [processor Register] CR /RaPs)
= the indtvidual Fliptlops tn an end bit regtsters
and numbered in sequence fom o-to(n-t) .
Starting from 0 «a the véght mast posrtton..aq
increasing the numbers towards \ere.
| | fener eon Registey R
| > The indtvedual bits can be ditetbutes as follows
ee | alislinguithed
| 16543910
| => The numbering of biis 0 a Ié bet regtttered can
| be mavited on the top of the box as shown below.
| >the 16 bil registers ts posttant into two pasts as
Shocon inthe Jgure below
1S OY H% 6
[9]
otis ero to though 6x60 Rae OBaD Ls
hyough 1S are asségn
SBS ia
Symbol 4’ and bits Bt
SYM Don Aw OY
The symbol
a
=> information transfered rom one vegttteyto anol
is destgnated #n Symbolic osm by means of replale-
ment operation
Example - RQ eR
S14 denote the transfer of the content of register
| R, into Ra,
R > The content of the source Reg
e Raw after the epanstey
sty a vegister transfered
slable trom the output of
ut of destinatton register.
aster has a paratiel
sider Ri does not
chang
| A statement that spec
implies the coreutt ate ava)
| the Jource register 70 the lop
land thal the destinatfon veg
toad Capability .
| > nlormally #e want to transfer to a ceiae OCCUr
only under a predetermined controlled tondttton.
p f(p=t) then (Ree RD
where pis a conteol Signal Dole + “Alielaeay
day
J
Elementary operation,
formed en dato stored tn the veg ister:
vlear which art shored 10
{ai micro operation.
crscugt (n Which -the
every partifor
bicck and completed at the lait 7 BA
oe +
|
| |8.N Typreal vEgHal computey has many hia and
path much be provided -to banster eofor alton, on,
| one regtler-to another reg tler
|x Amore efftesent scheme tor hanstering Infoun
|ratton between vegtrlers tn a multiple vegtsler
| contre avatton tg a common bus System
ik Bus shuctuve const of A set of common
“nes ane toy each bil of a veg titer through which
| Binaxy wtormation ts -transfoyed one ata lime,
(R contvol stgnal determine which register ls selected
| by the Bus ausing each partiiulas vegistey Transfey
* one woay of Constructing A CommMoN bus System
| fs with mulitPlexes
RThe mulltplexers Select the Source ¥
eg tslers Whase
| 8tnaxy wnformel
Son tt then -place on the bus.
| Fach vegivlers has & big#tt number oto 3
| The Bus constuts of 4X1 bus each having 4 data
tnputs oto 3 and WBh' selected input ‘S10,
x at wt dtve output one of register 9.25 connected
[40 input '0' of muyd ¢. Because thts Input tag ts
label suffix |.
¥ The Dfagvam shows the bit Inthe same Signtha-
nt poseleon in each vegkstex are connected to “the
| data input of one multiplexer -to form 2 18ne Of the
| Bus. | Etardwaxe tmplementation of contro led
| mow anny ow rw
TransFed :-
barons 1b~ byl regrsle
pe eee
) | control | i)
| J retreat? jhoad, yo ue ap, kK
7 |
no)
a ee
| clock L__ L bn 3
|
load a e “Ay
|
Tronsder p-
occas here
kg implementation of conteol tranitey “Pre +R
® HHalement that Specity 4 a regutered Transfer,
| implies that the etrutts are avatlable fom the out-
| put of Source register to the input ot destination
| reguter- and a destination register has a paral
| toad capability. noxmally we want to Transfer %
| octured only under a predetermined contro)
| cond ttton,
| € For Example im Wf P=1 -then -hantter the lomtent of
tegtster Ro toR), where p ts @ contsol Signal.
| & contol Functton i
| Ne
X contol Funclfons Separate the contaol vartable troy
veguter bansfer opexatton
# It % a booleant vartable that ts egualto Dor,
The contol Function $6 included in the statement
las follow Pt Rie Ra, Ln)
% The control conattfon 1s texminated ewrth a gateamn
HS symbolezes the requirement that the banstex
| operatton be edecutect by the hardware only If
| pal
|x 1f we have g or more opera
|y “they ave seperated by comma C3)
| hamples Pi Rie R2 » MORES PC
| here if the contsol Functton. P=! . load the cont
ent of Ro xR, -and at the same treme (same clocx|
pertod) me content of program counter [PL] whl
| be waded in memory address Regtiter [MAR]
t20n to occur Sémaltaneoy
| Symbous Desexeptron Lxamp kes |
nT pl re
||* capita ( a |
|| eters 2 Denotes a Register PAR Ra |
Alumbexs af ot yh ite p23 9 4
(© parenthe-| Denotes a part of registey R2 (0.1) pRale),
Sesc) | ae an
“+ Arrow (4) | oenodks transfer of tnformat-| Rae-Ri |
| —10n |
|
renotes termination of
© colon ct) | penoles teamtnalion 0 contro! | ps
| Fuaelion |
| * comma) Separales two MOO - operat, A+ Bs Be p
| ~ fon
L
Block fOkagyam
|% Mts block atagram represents transfer from Rito Ra
IR The n outputs of register Rr ave connected Fo 0» inputs
0g
of vegistey Ra. :
(® Register Ra has a oad tnpul -that ts activated by the
| control variable pa
1 1E 48 assumed thal the control clase Civil 3s Synchre-
|" ntaed wtth the Same clocks as the one applied 1 the
segisler,
* pts aclvated’ i the contvol sectton by the aurag
| edge of-a clock pulse al -limet,
lat The nex postltve “lanstfon of the clock at time tH)
finds the Woad input active and the data mputs of m
| Ra are then loaded mlothe vegtsler in pavallel,
€ p may 90 back to 0 at lime ttl Othevesse rthe
transten coflt occuy eotth every clock pube bhansiifon eohile p remains cclive.
Bus and Bus Transder t-
we AW ww
ae
® Bus fs a path Cota group of wires] ove which
infosmatton €s dsansterred trom any of Several Sources
e any of Several destinations
trom a regex to bus + Bus 3R Translen From Bus to 0, Bestinaton Register c
K— & [enablé)
| |
| elect ax
| wa De
| Three -state Bus Buffers 7-
mw Ny
) | Noxmal input A th outpul x=A wPce)
}
contol input ¢ 4igh - impedence he=o
i
} Bus line with three State butters
‘ i
Petes Bus line For bito
| 8 ————
Co if
Do
2 Bo
Bus Fransfen MN RTL i-
Aw Wn ow
| R Depending on Hh whether the Bus ts to be mentio-
| ned explttitly ox not , register can be endrcated
| as. ether. Rae Ri
or)
Bus <— Ri, Ra <— Bus
% inthe former case the bus ts expiteth but tn the
latter id ts expitertly indtcated
. Date i- 10/10/25
Plemory TransJen *- Bay ;- Tuesclay
wee
Pataout pala in
- |
| A 97 operand address] i- operand reid specity the
rocateon of opesand (reg tsten and memory words) .
specttsed by there address
bil binary Code
|
|
|
Memosy words are
RRegtsles are specitied by the K
| K bis a” regiters
alts 10ay
| stored program organtsation +
SEUSS BRAD SRN
| The abiltty to Stove and execute uni
most importani property ofa general Purpose computer
& that type of stored program concept *5 called Shore at
| program organtzation,
ay tO organize the computer ty to have
teon code tox
ucttons #9 the
2 Ine stmpliesd w
| one processor computes and a 1ngsteue
| vegtsten
| with 00 past
seThe Feud past Specthy the eperutton to be performed
|
and the second specity the an addres!
the below Ay shows the stoxed program organ tzation|
vo ue °
ene
opcode [operand | (address)
1S
- (at
| Binary operand ]
| ¢ Bs bs i
UDGbX 16
Cpa 04 am)
operand Cdatq)
Program veguie
Caccumulat ® Instructony ave slorecl in one section or sesston oF
memosy and dela tn another sesston of ounory.
# For memosy untl wih 09s words we need 18 PT to
Spectty an address
pate - 08(ulao3
: Computey Reg iste Day i- uid
The nced of ~the registes 19 the computer for
> Instructtons Seguencing need a counter +0 calculate
the address of next mstruction after the execution of
the current instruction 15 completed [Pc]
® Veceisary to provide a regtstes in the contol unit
for storing -the inctructton code after tt ts read tom
j memory Ling
® need psocessoy regtstey for manuputating data [hc
TR] and regtster For holding memoxy addvess a,
[Regtstey | mo.of
(abbr | ars | Register name Function
m | ee
lor | | pata Regtstey | trots memory operand
| |
| AR | 19 | Adesess vegtstey. | holds addxess memory
|
Ac 16 | Accumatlatos Processor regrstex
| = |
| R | 16 Instuctos register | Holds Nsbuclion code
| Pc | 12 | progtam code Holes addvess of next
| | | insbu ctor
| |
| TR | #6 | Tempowary vegtiter | Hoids temporay g net
| | | elata
ipa lg | Input regtstey Holds Input data
| output register | e1otds outpul deta lame data vegtttex (RJ holels the opexand read tom
memory
|2 The Acumulatoy register #5 place in the rnstructfon
vegistey (IRJ« The Input register vecetve & bil Kee
| chavacter From the tnpul clevire» the output clevice
hotds\an 3 bfl rhaxactes From an oulpul devive.
+ foumen Bus Prehttecturs
Temory
nT ucaexib
fi our] [inpe)”
| LF te taste computer has eight registers a memory unite and & contyyy
unt
/ ¥ paths must be provided + Transfex information trom one registey
te another and between memory ana registers
2A more effecient scheme fox transferring formation 0 oe
with many registers ts 40 use a common bus.
¥ The connection of the registers and memory of the baste ton]
~putey toa common bus system ts shown in Hg.
1% TRE output of seven registers and memovy ave corr eclect t
the common bus.
R ThE spectfic ouput that ts selectedl for the bus Itnes atany ate]
time 15 determined trom the binary vaueot the select£on
vartasles ss, 5, and Sy
¥ The number along each cutput shows the decimal equtvalen
ot the rejutred binary selection.
3 For example the numbex along the output of OR 153. The Ib-
Ut output of pr axe piaced on the bus fines when $25,51=00,
~7 tie tines trom the common bus axe connected -to the Inpicks
ct each registes and the data inputs of the memovy
PF the parttcular regtster whose Lo Lioad] imput ts ends
| vecetves the data ‘hom the bus dusing the neat clock
pulse transition
vt the memory recetves the contents of the bus when
3 catie wette input is activated.
ft ThE memosy places 14s 16-b;1 output onto -the bus
“ when the read input t activated and 535,50 =
Jt Two vegistess AR and PC, have 12 bits each since
-they hold a memory address
AR when the contents of AR or PC are applied 40 the I6-bil
common bus the tous most Stynthiant bts are set
+0 olf
|
4
7 MPR 1s connected +0 provide infommaitonto-the bus out our’
4
|with pasallel toad and Synchrenous clear
“R when AR or pC recetves Information from “the bus, only
‘the 12 least stgnititand bits ave teaniterred sto “the
register
& The input vegestey mvpR and the output register ovre
have @ btt each
& The communtiate cfth the eight leas! signtticant bits in
“the bus.
ean enty recetve information From the bus
f Its is because MPR xecetves a chavacter From an input
device which ts then hantlested 40 Re.
4 ObrR vecetves a chasactes trom Re and délivess M10 an
output device
‘4 Prue regtetess have three control inputs + LO CI10adI, Ime
Cincrementj sand c1R Celeas)
4 this type of vegtstes ts equivalent to a binary counter
4 nwo regtitess‘have bnly a Lo input
% Ihe input data and outputdata of the memory axe tonn.
~ectea to the common bus. bal the memory address ¢.
connected to AR
Ik Therefore , ARmust always be used 10 spectty a memoy
address
If the content of any register can be pplted onto the bus
and an operatton can be performed in the adder and
togte etrutt dating the same clock cycle.
4 For example rthe two mtcrooperatfons oRLAC And Al