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Course Handout

The document is a course handout for CS F342: Computer Architecture at Birla Institute of Technology and Science, Hyderabad Campus for the second semester of 2024-25. It outlines the course objectives, learning outcomes, textbook references, a detailed course plan, and evaluation scheme. The course focuses on computer architecture concepts, performance metrics, and design techniques, with practical lab assignments and consultations scheduled.

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7 views3 pages

Course Handout

The document is a course handout for CS F342: Computer Architecture at Birla Institute of Technology and Science, Hyderabad Campus for the second semester of 2024-25. It outlines the course objectives, learning outcomes, textbook references, a detailed course plan, and evaluation scheme. The course focuses on computer architecture concepts, performance metrics, and design techniques, with practical lab assignments and consultations scheduled.

Uploaded by

venkatatejap2022
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Hyderabad Campus

SECOND SEMESTER 2024-25


COURSE HANDOUT
Date: 02.01.2025
Course No : CS F342

Course Title : Computer Architecture

Instructors incharge : S Gurunarayanan

Instructor (Lab) : Aalelai Vendhan, K Gopi krishna

1. Scope and Objective:

This course aims at introducing the concept of computer architecture and organization. It involves design aspects, and
deals with the current trends in computing architecture. System resources such as memory technology and I/O
subsystems needed to achieve proportional increase in performance will also be discussed.

2. Learning outcomes:

❖ Understand various architectural techniques used in implementation of complex logic functions


❖ Apply these techniques in building different computing architectures
❖ Analyze different performance metrics of different computing architectures
❖ Design associated systems resources to achieve proportional increase in performance.

3. Text Book:

(T1) Patterson, David A & J L Hennessy, Computer Organization& Design, Elsevier, 6th Ed., 2021.

4. Reference Books:

(i) J.L. Hennessy & D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kauffmann, 6th Ed,
2019.
(ii) Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education Asia, 2nd Ed. 2006.

5. Course Plan:

Lecture No. Topics to be covered Learning Outcomes Reference to T1

01 Introduction Overview of the course Ch. 1.1-1.3.

02 Introduction to Performance metrics Definition different Ch. 1.5-1.10


of computing architectures parameters impacting
processor Performance

03, 04 MIPS Architecture & Instruction Set Overview of different Ch. 2


classes of instructions
Overview of different classes and
and addressing modes of
formats of MIPS instruction set a select RISC Processor.

1
BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Hyderabad Campus

05-06 Computer Arithmetic: Building Understanding the Ch. 3.1 – 3.5


hardware structures design and
implementation of
different arithmetic and
logic blocks

07,08,09 Data path Design: Building using Single Cycle & Multicycle Ch. 4.1 – 4.4
functional blocks Datapath
Implementation of MIPS
Processor

10,11 Control Hardware: FSM based Design Controller Design of a Appendix – D


Multicycle
12,13 Exceptions & Microprogramming Implementation of MIPS Ch. 4.9
Processor

14,15 Floating Point Arithmetic: Hardware Understanding floating Ch 3.6 – 3.10


Architectures point algebra and its
hardware
implementation

16 Role of Performance Ch. 1.4

17, 18 Memory organization- Introduction Role of Memory in a Ch5.1


Processor based Cache
19, 20 Cache Memory Organization: Memory Design Ch.5.2
Mapping Schemes techniques
21, 22, 23 Cache Performance Ch. 5.3

24, 25,26 Pipelining – Design Issues Designing a Pipelines Ch. 4.5 – 4.6
Processor and
27,28 Data Hazards understanding the Ch. 4.7

29,30 Control Hazards associated hazards and Ch. 4.8


methods to handle them
31, 32 Static Branch Prediction effectively. Class notes

33,34,35 Dynamic Branch Prediction Class notes

36,37 I/O Organization Ch. 6

38-40 Advanced Concepts in pipelining Concept of Instruction Ch. 4.12


Level Parallelism and its
impact in Processor
Performance

2
BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Hyderabad Campus

6. Evaluation Scheme:

EC Evaluation Component Duration Maximum


No. (Min) marks Date & Time Remarks

1 Mid Semester Test 90 60 08/03/2025 Closed Book


4 to 530 PM

2 Lab/Assignments/quizzes ** ----- 60 Will be Open Book


announced

3 Comprehensive examination 180 80 15/05/2025, Open Book/Closed Book


AN

** Details will be announced in the class & on course web page. Ref book R2 will be used for Lab Assignments. (A
Detailed Instruction sheet and plan for Laboratory sessions will be shared separately)

7. Chamber Consultation Hours: Tue: 4PM to 5 PM

8. Notices: Notices regarding the course will be put up on the CMS.

Instructor - in - charge

CS F342

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