Digital System Design Using Verilog 21EC32

Module-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description. (Section
1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description.
(Section 2.1 to 2.2 (only Verilog) of Text 3)

1.1 Hardware Description Language

Hardware Description Language (HDL) is an essential computer aided design (CAD) tool for the modern
design and synthesis of digital systems. The recent steady advances in semiconductor technology continue to
increase the power and complexity of digital systems. Due to their complexity, such systems cannot be easily
realized using discrete integrated circuits (ICs) or even the newer schematic-level simulation. These systems
are usually realized using high-density programmable chips, such as application- specific integrated circuits
(ASICs) and field-programmable gate arrays (FPGAs), and require sophisticated CAD tools. HDL is an
integral part of such tools. HDL offers the designer a very efficient tool for implementing and synthesizing
designs on chips. The designer uses HDL to describe the system in a computer-language code that is similar
to several commonly used software languages such as C. Debugging the design is easy because HDL packages
implement simulators and test benches. The two widely used hardware description languages are VHDL and
Verilog. After writing and testing the HDL code, the user can synthesize the code into digital logic components
such as gates and flip-flops that can be downloaded into FPGAs or compatible electronic components. The
HDL and synthesizer have made the task of designing complex systems much easier and faster than before.
Verilog was introduced in 1980s and has gone through several iterations and standardization by the
Institute of Electrical and Electronic Engineers (IEEE), such as in December 1995 when Verilog HDL became
IEEE Standard 1364-1995, in 2001 when IEEE Std. 1364-2001 was introduced, and in 2005 when IEEE 1800-
2005 was introduced. VHDL, which stands for very-high-speed integrated circuit (VHSIC) hardware
description language, was developed in the early 1980s. In 1987, the IEEE Standard 1076- 1987 version of
VHDL was introduced, and several upgrades followed. In 1993, VHDL was updated and more futures were
added; the result of this update was IEEE Standard 1076-1993. Recently, in 2008, the VHDL IEEE 1076-2008
was introduced.

1.2 Structure of the HDL Module

HDL modules follow the general structure of software languages such as C. The module has a source code
that is written in high-level language style. The most recently introduced feature in HDL packages allows
automatic generation of HDL code from C-language code. VHDL has a somewhat different structure than
Verilog HDL.
To illustrate the structure of the HDL module, let’s consider a half-adder circuit. A half adder is a
combinational circuit, which is a circuit whose output depends only on its input and which adds two input bits
and outputs the result as two bits, one bit for the sum and one bit for the carry out.
Examples of half addition include: 1 + 0 = 01, 1 + 1 = 10, and 0 + 0 = 00.

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TABLE 1.1 Truth Table for the Half Adder

The Boolean function of the output of the adder is obtained from the truth table. The Boolean function of the
output is generated using minterms (where the output has a value of 1) or maxterms (where the output has a
value of 0). The Boolean function using minterms in the sum of products (SOP) form is

After minimization (aa = 0 and bb =0), the SOP and the POS yield identical Boolean functions. Figure 1.1a
shows the logic symbol of the half adder. Figure 1.1b shows the logic diagram of the half adder.

1.2.2 Structure of the Verilog Module

Verilog module has declaration and body. In the declaration, the name, inputs, and outputs of the module are
entered. The body shows the relationship between the inputs and the outputs. Listing 1.2 shows a Verilog
description of a half adder based on the Boolean function of the outputs.

Listing 1.2 Example of a Verilog Module

module Half_adder(a,b,S,C);
input a,b;
output S, C;
assign S = a ^ b; // statement 1
assign C= a & b; // statement 2
endmodule

The name of the module in Listing 1.2 is a user-selected Half_adder. Verilog is case sensitive. Half_adder,
half_adder, and half_addEr are all different names. The name of the module should start with an alphabetical

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letter and can include the special character underscore (_). The declaration of the module starts with the
predefined word module followed by the user-selected name. The names of the inputs and outputs (they are
called input and output ports) follow the same guidelines as the module’s name. They are written inside
parentheses separated by a comma. The parenthesis is followed by a semicolon. In Listing 1.2, a, b, S, and C
are the names of the inputs and outputs. The order of writing the input and output ports inside the parentheses
is irrelevant. We could have written the module statement as: module half_adder (S, C, a, b); The semicolon
(;) is a line separator. Carriage return here does not indicate a new statement, the semicolon does. Following
the module statement, the input and output port modes are declared. For example, the statement input a;
declares signal a as an input port. The type of the input and output port signals need not be declared. The order
of writing the inputs and outputs and their declaration is irrelevant. For example, the inputs and outputs in
Listing 1.2 can be written as:
module half_adder (a,b, S, C);
output S;
output C;
input a;
input b;
Also, more than one input or output could be entered on the same line by using a comma (,) to separate each
input or output as:
module half_adder (a,b, S, C);
output S, C;
input a, b;
Statements 1 and 2 in Listing 1.2 are signal assignment statements . In statement 1, the symbol ^ represents
an EXCULSIVE-OR operation; this symbol is called a logical operator . So, statement 1 describes the
relationship between S, a, and b as S = a xor b. In statement 2, the symbol & represents an AND logic; the
symbol is called a logical operator. So, statement 2 describes the relationship between C, a, and b as C = a and
b. Accordingly, Listing 1.2 simulates a half adder. The double slash (//) is a comment command where a
comment can be entered. If the comment takes more than one line, a double slash or pair (/ …….. /) can be
used. The module is concluded by the predefined word endmodule. Leaving blank lines is allowed in the
module; also, spaces between two words or at the beginning of the line are allowed.

1.3 Styles (Types) Of Description

Several styles of code writing can be used to describe the system. Selection of the styles depends on the
available information on the system. For example, some systems may be easily described by the Boolean
function of the output; for other systems, such as biological mechanisms, it will be hard to obtain the Boolean
function of the output, but they can be described if the relationship between the changes of the output with the
input is known. In the following section, six styles will be discussed: data flow, behavioral, structural, switch
level, mixed type, and mixed language.

1.3.1 Data Flow Description

Data flow describes how the system’s signals flow from the inputs to the outputs. Usually, the description is
done by writing the Boolean function of the outputs. The data-flow statements are concurrent; their execution
is controlled by events. The Verilog module data-flow description, does not include any of the key words that

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identify behavioral, structural, or switch-level descriptions. Boolean function of S and C have been
implemented to describe the half adder; Listing 1.2 (Verilog).

1.3.2 Behavioral Description

A behavioral description models the system as to how the outputs behave with the inputs; usually, a flowchart
is used to show this behavior. In the half adder, the S output can be described as “1” if the inputs a and b are
not equal, otherwise S = “0,” . The output C can be described as acquiring a value of “1” only if each input (a
and b) is “1.” The HDL behavioral description is the one where the module (Verilog) contains the predefined
word always or initial . Behavioral description is usually used when the Boolean function or the digital logic
of the system is hard to obtain. Listing 1.3 shows a behavioural description of the output S of the half adder.

FIGURE 1.2 Behavior of output S with changes in inputs a and b.

LISTING 1.3 Example of Behavioral Description

Verilog Description
module Half_adder(a,b,S,C);
input a,b;
output S, C;
reg S,C;
always @ (a,b)
begin
if (a != b)
S = 1’b1;
else
S = 1’b0;
end
endmodule

1.3.3 Structural Description

Structural description models the system as components or gates. This description is identified by the presence
of the gates construct such as and, or, and not in the module . For the half adder, Figure 1.1b is used to write
the structural code. Listing 1.4 shows a structural description for the half adder.

Verilog Description
module Half_adder1(a,b,S,C);
input a, b;

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output S,C;
and a1(C,a,b);
//The above statement is AND gate
xor x1(S,a,b);
//The above statement is EXCLUSIVE-OR gate
endmodule

1.3.4 Switch-Level Description

The switch-level description is the lowest level of description. The system is described using switches or
transistors. Some of the Verilog predefined words used in the switch level description are nmos, pmos, cmos,
tranif0, tran, and tranif1. VHDL does not have built-in switch-level primitives, but a construct package can be
built to include such primitives.

Listing 1.5 shows the switch-level description of an inverter.

LISTING 1.5 An Example of A Switch-Level Description

Verilog Description
module invert(y,a);
input a;
output y;
supply1 vdd;
supply0 gnd;
pmos p1(y, vdd, a);
nmos n1(y, gnd, a);
/*The above two statement are using the two primitives pmos and nmos*/
endmodule

1.3.5 Mixed-Type Description

Mixed-type or mixed-style descriptions are those that use more than one type or style of the above-mentioned
descriptions. In fact, most of the descriptions of moderate to large systems are mixed. Some parts of the system
may be described using one type and others using other types of description.

1.3.6 Mixed-Language Description

The mixed-language description is a newly added tool to HDL description. The user now can write a module
in one language (VHDL or the other language). Listing 1.6 illustrates the mixed-language description. In this
Listing, inside Verilog module Full_Adder1, the VHDL entity HA is instantiated (imported). The information
given in that entity is now visible to the Verilog module.

LISTING 1.6 Example of Mixed-Language Description

module Full_Adder1 ( x,y, cin, sum, carry);
input x,y,cin;
output sum, carry;

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wire c0, c1, s0;

HA H1 (y, cin, s0,c0);
// Description of HA is written in VHDL in the
// entity HA
..................
endmodule
library IEEE;
use ieee.std_logic_1164.all;
entity HA is
--For correct binding between this VHDL code and the above
--Verilog code, the entity has to be named here as HA
port (a, b : in std_logic; s, c: out std_logic);
end HA;
architecture HA_Dtflw of HA is
begin
s <= a xor b;
c <= a and b;
end HA_Dtflw;

1.4 Ports
A simple definition of ports can be stated as a communication means between the system to be described and
the environment.
Verilog ports can take one of the following three modes:
• input: The port is only an input port. In any assignment statement, the port should appear only on the
right-hand side of the statement (i.e., the port is read).
• output: The port is an output port. In contrast to VHDL, the Verilog output port can appear in either
side of the assignment statement.
• inout: The port can be used as both an input and output. The inout port represents a bidirectional bus.

Operators
HDL has an extensive list of operators. Operators perform a wide variety of functions. These functions can be
classified as:
• Logical such as AND, OR, and XOR.
• Relational to express the relation between objects.These operators include equality, inequality, less
than, less than or equal, greater than, and greater than or equal.
• Arithmetic such as addition, subtraction, multiplication, and division.
• Shift to move the bits of an object in a certain direction, such as right or left

1.5.1 Logical Operators

These operators perform logical operations, such as AND, OR, NAND,NOR, NOT, and XOR. The operation
can be on two operands or on a single operand. The operand can be single or multiple bits.

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Verilog Logical Operators

Verilog has extensive logical operators. These operators perform logical operations such as AND, OR, and
XOR. Verilog logical operators can be classified into three groups: bitwise, Boolean logical, and reduction.
The bitwise operators operate on the corresponding bits of two operands. Consider the statement: Z= X & Y,
where the AND operator (&) “ANDs” the corresponding bits of X and Y and stores the result in Z. For
example, if X is the four-bit signal 1011, and Y is the four-bit signal 1010, then Z = 1010. Table 1.3 shows
bitwise logical operators. For example, the NAND operation on X and Y is written as: Z = ~(X & Y).

Other types of logical operators include the Boolean logical operators. These operators operate on two
operands, and the result is in Boolean: 0 (false) or 1 (true). For example, consider the statement Z = X && Y
where && is the Boolean logical AND operator. If X = 1011 and Y = 0001, then Z = 1. If X = 1010 and Y =
0101, then Z = 0. Table 1.4 shows the Boolean logical operators.

The third type of logical operator is the reduction operator. Reduction operators operate on a single operand.
The result is in Boolean. For example, in the statement Y = &X, where & is the reduction AND operator, and
assuming X = 1010, then Y = (1 & 0 & 1 & 0) = 0. Table 1.5 shows the reduction logic operators.

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1.5.2 Relational Operators

Relational operators are implemented to compare the values of two objects. The result returned by these
operators is in Boolean: false (0) or true (1).

Verilog Relational Operators

Table 1.7 shows Verilog relational operators. The relational operators return Boolean values: false (0) or true
(1).

For the equality operator (==) and inequality operator (!=), the result can be of type unknown (x) if any of the
operands include “don’t care,” “unknown (x),” or “high impedance z.” The following are examples of a
Verilog relational operators:
if (A == B) .…….
If the value of A or B contains one or more “don’t care” or z bits, the value of the expression is unknown.
Otherwise, if A is equal to B, the value of the expression is true (1). If A is not equal to B, the value of the
expression is false (0).
if (A === B)…..
This is a bit-by-bit comparison. A or B can include x or high impedance Z; the result is true (1) if all bits of A
match that of B. Otherwise, the result is false (0).
For the conditional operator “?” the format is:

Conditional-expression ? true-expression : false-expression ;

The conditional expression is evaluated; if true, true-expression is executed ,If false, false-expression is
executed. If the result of the conditional expression is “x,” both false and true are executed, and their results
are compared bit by bit; if two corresponding bits are the same, the common value of these bits is returned. If
they are not equal, an “x” is returned.

1.5.3 Arithmetic Operators

Arithmetic operators can perform a wide variety of operations, such as addition, subtraction, multiplication,
and division.
Verilog Arithmetic Operators
For most operations, only one type of operation is expected for each operator. An example of an arithmetic
Verilog operator is the addition operator (+); the statement Y = (A + B) calculates the value of Y as the sum
of A and B. Table 1.9 shows the Verilog arithmetic operators.

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1.5.3.3 Arithmetic Operator Precedence

The precedence of the arithmetic operators in VHDL or Verilog is the same as in C. The precedence of the
major operators is listed below from highest to lowest:
**
*/ mod (%)
+-

1.5.4 Shift and Rotate Operators

Shift and rotate operators are implemented in many applications, such as in multiplication and division. A
shift left represents multiplication by two, and a shift right represents division by two.

Verilog Shift Operators

Verilog has the basic shift operators. Shift operators are unary operators; they operate on a single operand. To
understand the function of these operators, assume operand A is the four-bit vector 1110. Table 1.11 shows
the Verilog shift operators as they apply to operand A.

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Data Types
As HDL is implemented to describe the hardware of a system, the data or operands used in the language must
have several types to match the need for describing the hardware. For example, if we are describing a signal,
we need to specify its type (i.e., the values that the signal can take), such as type bit, which means that the
signal can assume only 0 or 1, or type std_logic, in which the signal can assume a value out of nine possible
values that include 0, 1,X and high impedance. Examples of types include integer, real, vector, bit, and array.

Verilog Data Types

Verilog supports several data types including nets, registers, vectors, integer, real, parameters, and arrays.

1.6.2.1 Nets
Nets are declared by the predefined word wire. Nets have values that change continuously by the circuits that
are driving them. Verilog supports four values for nets, as shown in Table 1.13.

Examples of net types are as follows:

wire sum;
wire S1 = 1’b0;
The first statement declares a net by the name sum. The second statement declares a net by the name of S1;
its initial value is 1’b0, which represents 1 bit with value 0.

1.6.2.2 Register
Register, in contrast to nets, stores values until they are updated. Register, as its name suggests, represents
data-storage elements. Register is declared by the predefined word reg. Verilog supports four values for
register, as shown in Table 1.14.

An example of register is:

reg Sum_total;
The above statement declares a register by the name Sum_total.

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1.6.2.3 Vectors
Vectors are multiple bits. A register or a net can be declared as a vector. Vectors are declared by brackets [ ].
Examples of vectors are:
wire [3:0] a = 4’b1010;
reg [7:0] total = 8’d12;
The first statement declares a net a. It has four bits, and its initial value is 1010 (b stands for bit). The second
statement declares a register total. Its size is eight bits, and its value is decimal 12 (d stands for decimal).

1.6.2.4 Integers
Integers are declared by the predefined word integer. An example of integer declaration is:
integer no_bits;
The above statement declares no_bits as an integer.

1.6.2.4 Real
Real (floating-point) numbers are declared with the predefined word real. Examples of real values are 2.4,
56.3, and 5e12. The value 5e12 is equal to 5 × 1012. The following statement declares the register weight as
real:
real weight;

1.6.2.5 Parameter
Parameter represents a global constant. It is declared by the predefined word parameter. The following is an
example of implementing parameters:
module compr_genr (X, Y, xgty, xlty, xeqy);
parameter N = 3;
input [N:0] X, Y;
output xgty, xlty, xeqy;
wire [N:0] sum, Yb;
To change the size of the inputs x and y, the size of the nets sum, and the size of net Yb to eight bits, the value
of N is changed to seven as: parameter N = 7

1.6.2.6 Arrays
Verilog, in contrast to VHDL, does not have a predefined word for array. Registers and integers can be written
as arrays. Consider the following statements:
parameter N = 4;
parameter M = 3;
reg signed [M:0] carry [0:N];
The above statements declare an array by the name carry. The array carry has five elements, and each element
is four bits. The four bits are in two’s complement form. For example, if the value of a certain element is 1001,
then it is equivalent to decimal –7. Arrays can be multidimensional.

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Verilog Data flow description

2.1 Highlights Of Data-Flow Description
Data flow is one type (style) of hardware description. Other types include behavioral, structural, switch level,
mixed type, and mixed language. Listed below are some facts about data-flow description:
• Data-flow description simulates the system to be described by showing how the signal flows from the
system inputs to its outputs. For example, the Boolean function of the output or the logical structure
of the system shows such signal flow.
• Signal-assignment statements are concurrent. At any simulation time, all signal-assignment statements
that have an event are executed concurrently

2.2 Signal Declaration And Assignment Statement

Figure 2.1 shows an AND-OR circuit. Signals a, b, c, and d are the inputs, signal y is the output, and signals
s1 and s2 are intermediates. The Boolean function of the output y can be written as:
Verilog description

module andor (a,b,c,d, y );

input a,b,c,d;
output y;
wire s1, s2; /* wire statement here is not necessarily needed since s1 and s2 are single bit*/
assign s1 = a & b; //statement 1.
assign s2 = c & d; //statement 2.
assign y = s1 | s2; //statement 3.
endmodule
Using a CAD package with HDL simulator the code in Listing 2.1 can be simulated on the screen of the
computer, and a waveform showing a graphical relationship between the input and the output can be obtained.
Figure 2.2 shows such a waveform.

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Referring to Listing 2.1, the input and output signals are declared in the module as ports. In HDL, a signal has
to be declared before it can be used (although in Verilog, it is not necessarily needed if the signal is a single
bit). Accordingly, signals s1 and s2 have to be declared using the predefined word wire:
wire s1, s2;
By default, all ports in Verilog are assumed to be wires. The value of the wire is continuously changing with
changes in the device that is deriving it. For example, s1 is the output of the AND gate in Figure 2.1, and s1
is continuously updated as a or b changes. A signal-assignment statement is used to assign a value to a signal.
The left-hand side of the statement should be declared as a signal. The righthand side can be a signal, a
variable, or a constant. The operator for signal assignment is <= in VHDL or the predefined word assign in
Verilog. In Listing 2.1, statements 1, 2, and 3 are signal-assignment statements. Statements 1–3 need an event
to occur on its right-hand side to start execution. If no event occurred on any statement, this statement would
not be executed. An event is a change in the value of a signal or variable such as a change from 0 to 1 (from
low to high) or from 1 to 0 (from high to low). The statement that receives an event first will be executed first
regardless of the order of its placement in the HDL code. If more than one statement has an event at the same
time, all of these statements will be executed concurrently (i.e., simultaneously). Accordingly, statement 3,
for example, could have been written before statement 1 in Listing 2.1, and the order of execution would not
be affected. The signal-assignment statement is executed in two phases: calculation and assignment. If an
event occurs on the right-hand side of a statement, then this side is calculated at the time of the event; after
calculation, the value obtained from the calculation is assigned to the left-hand side, taking into consideration
any timing information given in the statement. Consider Listing 2.1 and Figure 2.2. At T0, an event has
occurred in signal a and signal b (both signals changed their value from 0 to 1, which is an event). Accordingly,
an event occurred in statement 1; the value of (a and b) is calculated as (1 and 1 = 1).
Because no delay time is specified, the value 1 is assigned immediately to s1, changing s1 from 0 to 1.
Changing the value of s1 from 0 to 1 constitutes an event in s1 and in statement 3, which is executed as a
result of the event in its right-hand side. The right-hand side of statement 3 is calculated at T0 as (s1 [1] or s2
[0] = 1). The value of 1 is assigned to y; all at T0 because no delay time is specified. At T1, there is event on
signals a (1 to 0), c (0 to 1), and d (0 to 1). Statements 1 and 2 will be executed concurrently because an event
occurred on their right-hand side. The right-hand side of statement 1 and 2 is calculated at T1 as (0 and 1 = 0)
and (1 and 1 = 1); the value of 0 is assigned to s1, and the value of 1 is assigned to s2 at T1. Changing the
value of s1 and s2 constitutes an event on s1 and s2, which selects statement 3 for execution at T1; statement

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3 is executed (calculation, s1 or s2 = 0 or 1 = 1), and accordingly, 1 is assigned to signal y. At T2, an event

occurred on signal c, statement 2 is executed at T2, and the calculation results in 0 and 1 = 0; the value 0 is
assigned to s2, changing its value from 1 to 0 and generating an event in s2. Statement 3 is executed because
an event (changing the value of s2 from 1 to 0) occurred on the right-hand side. The calculation results in 0 or
0 = 0; the value 0 is assigned to y at T2.

2.2.1 Constant Declaration and Constant Assignment Statements

A constant in HDL is treated as it is in C language; its value is constant within the segment of the program
where it is visible. A constant in VHDL can be declared using the predefined word constant. In Verilog, a
constant can be declared by its type such as time or integer. For example, the following statements declare
period as a constant of type time:
time period; // Verilog
To assign a value to a constant, use the assignment operator = in Verilog. For example, to assign a value of
100 nanoseconds to the constant period described above:
period = 100; // Verilog
In the above Verilog statement, there are no explicit units of time; 100 means 100 simulation screen time units.
If the simulation screen time units are defined as nanoseconds (ns), for example, then 100 will mean 100
nanoseconds.
The declaration and assignment can be combined in one statement as:
time period = 100 //Verilog

2.2.2 Assigning a Delay Time to the Signal-Assignment Statement

To assign a delay time to a signal-assignment statement, the predefined word # in Verilog is used. For example,
the following statement assigns a 10 ns delay time to signal S1:
assign #10 S1 = a & b // Verilog
In Verilog, the delay is in simulation screen unit time. Let us assume that there is a delay of 10 ns between the
output of each statement 1–3 and its input in Listing 2.1. This is equivalent to saying that operation (and) or
(or) takes 10 ns to be completed. Listing 2.2 shows the HDL code for Figure 2.1 with a 10 ns delay for the
(and) and (or) operations.

LISTING 2.2 HDL code of Figure 2.1 with 10 ns delay

Verilog description
module and_orDlyVr( a,b,c,d, y );
input a,b,c,d;
output y;
time dly = 10;
wire s1, s2;
assign # dly s1 = a & b; //statement 1.
assign # dly s2 = c & d; //statement 2.
assign # dly y = s1 | s2; //statement 3.

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endmodule

Figure 2.3 shows the simulation waveform of Listing 2.2. Table 2.1 shows analysis of the waveform according
to Listing 2.2. At T0, an event occurred on signal a and signal b (both changed from 0 to 1). This event will
invoke execution of statement 1. The right-hand side (R.H.S) of statement1 is calculated at T0 as (1 and 1 =
1). However, this value of 1 will not assigned to s1 at T0; rather, it will be assigned at T0 + 10 ns = T1. The
rest of Table 2.1 could be understood by following the same analysis that has been done above at T0.

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From Table 2.1, the worst total delay time between the input and the output of Figure 2.1, as expected, is 20
ns. It is to be noted that if a signal assignment statement did not specify a delay time, the assignment to its
left-hand side would occur after the default infinitesimally small delay time of D (delta) seconds. This
infinitesimally small time cannot be detected on the screen, and the delay time will look as if it is zero. In the
following several examples, data-flow descriptions are introduced.

EXAMPLE 2.1 DATA-FLOW DESCRIPTION OF A FULL ADDER

A full adder is a combinational circuit (output depends only on the input) that adds three input bits (a + b + c)
and outputs the result as two bits; one bit for the sum and one bit for the carryout. Examples of full addition
are: 1 + 0 + 1 = 10 (in decimal 1 + 0 + 1 = 2) and 1 + 1 + 1 = 11 (in decimal 1 + 1 + 1 = 3). Table 2.2 shows
the truth table of the full adder.

FIGURE 2.4 K-maps for the minterms (m) for the Sum and Carryout.

The Boolean function of the Sum and Carryout can be obtained from K-maps as shown in Figure 2.4.
Sum = a bc + a b c + ab c + abc (2.3)
Carryout = ab + ac + bc (2.4)
The symbol diagram of the full adder is shown in Figure 2.5a. The logic diagram of a full adder based on
Equations 2.3 and 2.4 is shown in Figure 2.5b.

The full adder can be built from several existing logic components such as two half adders and multiplexers.
Building a full adder from two half adders is based on the following analysis. The full adder adds a plus b plus
c = carryout sum. If the addition is performed in two steps: a plus b = C1 S, and c plus S = C2 sum (sum is the

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sum of the three bits). C1 and C2 cannot have a value of 1 at the same time. If C1 has value of 1, then C2 has
to be 0 and vice versa. For example, to add 1 plus 1 plus 1, divide the addition in two halves; the first half is
1 plus 1 = 10, and the second half is 0 plus 1 = 1. The carryout will be (C1 or C2); in this example, it is 1 and
the sum = 1. Figure 2.6 shows the logic diagram

Listing 2.3 shows the HDL code for the full adder as shown in Figure 2.5. The code assumes no delay time.
The parenthesis in the code, as in C language, gives the highest priority to the expression within the parenthesis
and makes the code more readable.
LISTING 2.3 HDL Code of the Full Adder From Figure 2.5

Verilog description
module fulladder(a, b, c);
output Sum, Carryout;
input a, b, c;
assign Sum = (~ a & ~ b & c)|( ~ a & b & ~c)|( a & ~b & ~c)|( a & b & c) ;
assign Carryout = (a & b) | (a & c) | (b & c);
endmodule

EXAMPLE 2.2 FULL SUBTRACTOR

A full subtractor performs the following operation: a - b - c = Borrow Diff. Borrow and Diff are each one-bit
output. The Diff is the difference, and Borrow is the borrow. For example, 0 - 1 - 0 = 11. The subtraction is
done as follows: 0 - 1 cannot subtract 1 from 0 because 1 is greater than 0, so borrow 1 from the higher-order
bit. Accordingly, this 1 has a weight of 21, so its value is 2; subtract 2 - 1 = 1. Now, for bit c, 1 - 0 = 1, so the
difference is 1, and the borrow is 1. Table 2.3 shows the truth table of a full subtractor.

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Compare the Diff in Table 2.3 and the Sum in Table 2.2; they are identical, so the Boolean function of the
Diff is the same as the sum in Equation 2.3. For the Borrow, draw the K-map as shown in Figure 2.8.

EXAMPLE 2.3A 2x1 MULTIPLEXER WITH ACTIVE LOW ENABLE

A 2x1 multiplexer is a combinational circuit; it has two one-bit inputs, a one-bit select line, and a one-bit
output. Additional control signals may be added, such as enable. The output of the basic multiplexer depends
on the level of the select line. If the select is high (1), the output is equal to one of the two inputs. If the select
is low (0), the output is equal to the other input. A truth table for a 2x1 multiplexer with active low enable is
shown in Table 2.4.

If the enable (Gbar) is high (1), the output is low (0) regardless of the input. When Gbar is low (0), the output
is A if SEL is low (0), or the output is B if SEL is high (1). From Table 2.4, the Boolean function of the output
Y is: Y = (S1 and A and SEL) or (S1 and B and SEL); S1 is the invert of Gbar.
Figure 2.9a shows the logic symbol, and Figure 2.9b shows the gatelevel structure of the multiplexer.

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Listing 2.4a shows the HDL code. To generate the code, follow Figure 2.9b. Propagation delay time for all
gates is assumed to be 7 ns. Because this is a data-flow description, the order in which the statements are
written in the code is irrelevant. For example, statement st6 could have been written at the very beginning
instead of statement st1. The logical operators in VHDL and (Verilog) implemented in this Listing are: OR
(|), AND (&), and NOT (~).

LISTING 2.4a HDL Code of a 2x1 Multiplexer: Verilog

Verilog Description
module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
wire S1, S2, S3, S4, S5;
time dly = 7;
/* Assume 7 time units delay for all and, or, not operations. The delay here is expressed in simulation screen
units. */
assign # dly Y = S4 | S5; //st1
assign #dly S4 = A & S2 & S1; //st2
assign #dly S5 = B & S3 & S1; //st3
assign #dly S2 = ~ SEL; //st4
assign #dly S3 = ~ S2; //st5
assign #dly S1 = ~ Gbar; //st6
endmodule

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Analysis of Listing 2.4a

Referring to Listing 2.4a, because the description is a data flow, the order of statements st1 to st6 is irrelevant;
statement st5 could have been written before statement st1 without changing the outcome of the HDL program.
In Figure 2.10, signal A changes from 1 to 0, and signal B changes from 0 to 1 at T0; these changes constitute
an event in signal-assignment statements st2 and st3. Accordingly, statements st2 and st3 are executed
simultaneously. As previously mentioned, execution is done in two phases: calculation and assignment. For
statement st2, at T0, A = 0, S2 = 1 (the inversion of SEL), and S1 = 1 (the inversion of Gbar); hence, the
calculated new value of S4 at T0 is (A AND S1 AND S2) = 0. This is a change in value for S4 from 1 to 0,
which is assigned to S4 after 7 ns from time T0 (at 107 ns). For statement st3, at T0, B = 1, S3 = 0, and S1 =
1. The calculated value of S5 is 0, as it was before T0. At T = 107 ns, an event occurs on S4, and this causes
execution of statement st1. Y is calculated as (0 or 1) = 1, and this value is assigned to Y after 7 ns, that is, at
T1 = 107 + 7 = 114 ns. Alternatively, statements st1 to st5 can be replaced by one statement:
assign # 21 Y = ~ (Gbar) & ((SEL & B ) | (~ SEL & A));
The above delay time of 21ns is an estimated average delay time. If either of the above two statements is used,
individual delay times cannot be assigned, as was done in Listing 2.4a.

EXAMPLE 2.3B 2x1 MULTIPLEXER WITH ACTIVE LOW ENABLE USING

VERILOG CONDITIONAL OPERATOR (?)
The conditional operator ? (see Section 1.5.2.2) can be used to describe a multiplexer or any other similar
system that utilizes a selector signal to select between two options. The format of this operator can be written
as:
Assign Y = Conditional-expression ? true-expression : false-expression
If the conditional expression is true, the value of the true expression is assigned to Y; if the conditional
expression is false, the value of the false expression is assigned to Y. Listing 2.4b illustrates a Verilog code
for a 2x1 multiplexer using the conditional operator ? to select the value of the output Y according to the level
of the enable Gbar. If Gbar is high (1), that is to say the conditional expression is true, the output Y is assigned
to low (0). Otherwise, the output Y is assigned the false expression (SEL & B ) | (~ SEL & A). Also, both the
true and the false
expressions can contain high impedance and don’t care; this will allow for describing systems such as
multiplexers with tri-state output .

LISTING 2.4b HDL Code of a 2x1 Multiplexer Using Verilog Conditional (?)

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module Mux2x1_conditional(input A,B,SEL,Gbar, output Y );

assign Y = (Gbar) ? 1’b0 : (SEL & B ) | (~ SEL & A);
endmodule

EXAMPLE 2.4 A 2x4 DECODER

A decoder is a combinational circuit. A 2x4 decoder has two inputs and four outputs. For any input, only one
output is active; all others are inactive. For active high output decoders, only one output is high. The output
of n-bit input decoder is 2n bits. Table 2.5 shows the truth table of the 2x4 decoder.

Listing 2.4 shows the HDL code of the decoder. Figure 2.12 shows the simulation waveform of the decoder.

LISTING 2.4 HDL Code of a 2x4 Decoder Without Time Delay

Verilog description
module decoder2x4( a, b, D);
input a,b;
output [3:0]D;
assign D[0] = ~a & ~ b;
assign D[1] = a & ~ b;
assign D[2] = ~a & b;

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assign D[3] = a & b;

endmodule

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