STRUCTURAL MODELLING

Basic Gates
AIM:-
Write verilog HDL codes in gate level for basic gates
OBJECTIVES:-
Upon completion of this experiment the students will be able to know various keywords
for gate level modeling
PROCEDURE
1. Open Xilinx ISE and create a new project with a project name (eg:-Gates)
2. Create a verilog source file with filename same as module name
3. Write the given program1 on the editor window
4. Select synthesis/Implementation in the drop down list of source window
5. Create source file of test bench waveform with timings as the following information for
the signal in1
♦ Clock High Time: 100 ns.
♦ Clock Low Time: 100 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
6. Modify the test bench waveform by click on relevant part of the waves(May use the rescale
timing tab on the testbench menu to change edges and timings) and save it
7. Now select Behavioral simulation from source window after selecting the tbw file in the
process window
8. Double click on simulate behavioral model
9. Observe the output waveforms obtained by simulation and verify truth table
10. Repeat steps 3 to 9 for other programs

LOGIC DIAGRAM

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HDL and MATLAB at GPC Thrikaripur by SITTTR Kerala
 Structural Modelling

TRUTH TABLE

AND Gate OR Gate NOR Gate NAND Gate

Input Output Input Output Input Output Input Output

i1 i2 out1 i1 i2 out2 i1 i2 out4 i1 i2 out5

0 0 0 0 0 0 0 0 1 0 0 1
0 1 0 0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0

BUFFER EXOR Gate EXNOR Gate

in out7 Input Output Input Output NOT gate
0 0 i1 i2 out3 in out8
i1 i2 out6
1 1 0 0 0 0 0 1 0 1
0 1 1 0 1 0 1 0
1 0 1 1 0 0
Program 1 1 1 0 1 1 1
// Verilog HDL program in Gate level for basic gates
// module declaration

module gate_2(out1 ,i1,i2);

//gate_2 is the module name (it should be same as verilog source file name)

// port declaration
input i1,i2,in;
output out1;

// gate level declaration for AND

and an_2(out1,i1,i2);

// and is the keyword for AND operation, output variable should be specified first (out1)
//an_2 is the name of the gate specified by the user, gate name specification can be omitted

endmodule
Program 2
module gate_2(out2 ,i1,i2);
input i1,i2;
output out1;

// gate level declaration for OR

or Or_2(out2,i1,i2);
// or is the keyword for OR operation, output variable should be specified first (out2)

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 Structural Modelling

endmodule

Program 3
module gate_2(out3, out4, out5, out6,i1,i2);
// gate level declaration for other gates
input i1,i2;
output out3,out4,out5,out6;

xor x_2(out3,i1,i2);
nand na_2(out4,i1,i2);
nor no_2(out5,i1,i2);
xnor xnr_2(out6,i1,i2);
endmodule

Program 4
module gate_1(out7,out8,in);
input in;
output out7,out8;

not nt(out8,in);
buf bu(out7,in);
endmodule

4 x 1 MULTIPLEXER
AIM:-
Write verilog HDL codes in gate level for 4 X 1 Multiplexer
OBJECTIVES:-
Upon completion of this experiment the students will be able to understand the usage of
keyword “wire”
1. Open Xilinx ISE and create a new project with a project name (eg:-Mux)
2. Create a verilog source file with filename same as module name
3. Write the given program on the editor window
4. Select synthesis/Implementation in the drop down list of source window
5. Create verilog source file of test bench waveform with timings with the following
information for the signal i0
♦ Clock High Time: 20 ns.
♦ Clock Low Time: 20 ns.
♦ Input Setup Time: 0 ns.
♦ Output Valid Delay: 0 ns.
♦ Offset: 0 ns.
6. Modify the test bench waveform by click on relevant part of the waves and save it
7. Now select Behavioral simulation from source window after selecting the tbw file in the
process window
8. Double click on simulate behavioral model
9. Observe the output waveforms obtained by simulation and verify truth table
10. Repeat steps 3 to 9 for other programs

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HDL and MATLAB at GPC Thrikaripur by SITTTR Kerala
 Structural Modelling

LOGIC DIAGRAM:-

TRUTH TABLE:-
Select lines Output
S1 S0 Out
0 0 i1
0 1 i2
1 0 i3
1 1 i4

PROGRAM
Program 1
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;

// Internal wire declarations

wire s1n, s0n;
wire y0, y1, y2, y3;

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HDL and MATLAB at GPC Thrikaripur by SITTTR Kerala
 Structural Modelling

// Gate instantiations

// Create s1n and s0n signals.

not (s1n, s1);
not (s0n, s0);

// 3-input and gates instantiated

and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);

// 4-input or gate instantiated

or (out, y0, y1, y2, y3);
endmodule
ONE BIT FULL ADDER
AIM:-
Write verilog HDL codes in gate level for one bit full adder
PROCEDURE
1. Open Xilinx ISE and create a new project with a project name (eg:-Adder1)
2. Create a verilog source file with filename same as module name
3. Write the given program on the editor window
4. Select synthesis/Implementation in the drop down list of source window
5. Create source file of test bench waveform with timings as the following information for
the signal c_in
♦ Clock High Time: 100 ns.
♦ Clock Low Time: 100 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
6. Modify the test bench waveform by click on relevant part of the waves and save it
7. Now select Behavioral simulation from source window after selecting the tbw file in the
process window
8. Double click on simulate behavioral model
9. Observe the output waveforms obtained by simulation and verify truth table

LOGIC DIAGRAM:-

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HDL and MATLAB at GPC Thrikaripur by SITTTR Kerala
 Structural Modelling

TRUTH TABLE:-
INPUT OUT PUT
a B c_in Sum c_out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROGRAMS:-
Program 1
// Define a 1-bit full adder in Gate level
module fulladd(sum, c_out, a, b, c_in);

// I/O port declarations

output sum, c_out;
input a, b, c_in;

// Internal nets
wire s1, c1, c2;

// Instantiate logic gate primitives

xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
or (c_out, c2, c1);
endmodule

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 Structural Modelling

FOUR BIT FULL ADDER

AIM:-
Write verilog HDL codes in gate level for 4- bit full adder
OBJECTIVES:-
Upon completion of this experiment the students will be able to
1. To understand the structural modeling by interconnection of gate level blocks
(bottom to top approach of design- four bit full adder as interconnection of one bit
full adder)

LOGIC DIAGRAM:-

PROGRAMS
Program 1
// Structural Model
// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;
output c_out;
input[3:0] a, b;

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 Structural Modelling

input c_in;

// Internal nets
wire c1, c2, c3;

// Instantiate four 1-bit full adders.

fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);

endmodule

// Define a 1-bit full adder

module fulladd(sum, c_out, a, b, c_in);

// I/O port declarations

output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;

// Instantiate logic gate primitives

xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
or (c_out, c2, c1);
endmodule

Do it yourself(DIY)

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