Session_06_Encoder ^0 Decoder
Session_06_Encoder ^0 Decoder
Session No: 06
AIM OF THE SESSION
INSTRUCTIONAL OBJECTIVES
LEARNING OUTCOMES
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
Y2 = I 7 + I 6 + I 5 + I 4
I7 0 0 0 0 0 0 0 1 0 0 0 Y1 = I 7 + I 6 + I 3 + I 2
I6
0 0 0 0 0 0 1 0 0 0 1 Y0 = I 7 + I 5 + I 3 + I1
I5
Y2 0 0 0 0 0 1 0 0 0 1 0
Encoder
I4 I7
Binary
I3 Y1 0 0 0 0 1 0 0 0 0 1 1 I6 Y2
Y0 I5
I2 0 0 0 1 0 0 0 0 1 0 0 I4
I1 0 0 1 0 0 0 0 0 1 0 1 I3 Y1
I0 I2
0 1 0 0 0 0 0 0 1 1 0
I1
1 0 0 0 0 0 0 0 1 1 1 I0 Y0
ENCODER Application
North 0 0 0
North-East 0 0 1
East 0 1 0
South-East 0 1 1
South 1 0 0
South-West 1 0 1
West 1 1 0
North-West 1 1 1
DECODER
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of
these outputs will be active High based on the combination of inputs present, when the decoder is
enabled.
3–to-8 DECODER
X Y Z F7 F6 F5 F4 F3 F2 F1 F0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
DECODER Application
𝒀𝟎 Addition
𝒀𝟏 Subtraction
0 𝑪𝟎 𝒀𝟐
Multiplication
0 𝑪𝟏 𝒀𝟑 Division
Decoder
𝒀𝟒 AND
0 𝑪𝟐 𝒀𝟓
OR
𝒀𝟔
NOT
𝒀𝟕
XOR
EN
Implementation of Boolean Functions using Decoder
Eg : Implement a Full adder using a suitable decoder and OR gates.
S (x, y, z) = ∑m(1, 2, 4, 7)
C (x, y, z) = ∑m(3, 5, 6, 7)
x
y
z
TRADITIONAL ENCODE-DECODE MODEL OF COMMUNICATION
SELF-ASSESSMENT QUESTIONS
A. 2
B. 3
C. 4
D. 8
SELF-ASSESSMENT QUESTIONS
4. In a 2-to-4 Encoder, if the input is 01, which output line will be active?
A. Output 0
B. Output 1
C. Output 2
D. Output 3
TERMINAL QUESTIONS
Reference Books:
1. Computer System Architecture by M. Moris Mano
2. Fundamentals of Digital Logic with Verilog HDL by Stephen Brown and ZvonkoVranesic