(Advanced) Computer Architechture

Prof. Dr. Hasan Hüseyin BALIK

(6th Week)
Outline

3. Instruction sets
—Instruction Sets: Characteristics and Functions
—Instruction Sets: Addressing Modes and Formats
—Assembly Language and Related Topics
+
3.2 Instruction Sets: Addressing
Modes and Formats
3.2 Outline
• Addressing Modes
• x86 and ARM Addressing Modes
• Instruction Formats
• x86 and ARM Instruction Formats
Addressing Modes

Immediate

Direct

Indirect

Register

Register indirect

Displacement

Stack
Addressing Modes
Instruction Instruction Instruction
Operand A A
Memory Memory

Operand

Operand

(a) Immediate (b) Direct (c) Indirect

Instruction Instruction Instruction

R R R A
Memory Memory

Operand

Operand Operand
Registers Registers Registers
(d) Register (e) Register Indirect (f) Displacement

Instruction

Implicit
A = contents of an address field in the instruction
R = contents of an address field in the instruction that refers to a
Top of Stack
Register register
(g) Stack

Figure 14.1 Addressing M odes

Basic Addressing Modes
Mode Algorithm Principal Advantage Principal Disadvantage

Immediate Operand = A No memory reference Limited operand magnitude

Direct EA = A Simple Limited address space

Indirect EA = (A) Large address space Multiple memory references

Register EA = R No memory reference Limited address space

Register indirect EA = (R) Large address space Extra memory reference

Displacement EA = A + (R) Flexibility Complexity

Stack EA = top of stack No memory reference Limited applicability

A = contents of an address field in the instruction

R = contents of an address field in the instruction that refers to a register
EA = actual (effective) address of the location containing the referenced operand
(X) = contents of memory location X or register X
Immediate Addressing
• Simplest form of addressing
• Operand = A
• This mode can be used to define and use constants or
set initial values of variables
– Typically the number will be stored in twos complement form
– The leftmost bit of the operand field is used as a sign bit

• Advantage:
– No memory reference other than the instruction fetch is required to obtain the
operand, thus saving one memory or cache cycle in the instruction cycle

• Disadvantage:
– The size of the number is restricted to the size of the address field, which, in
most instruction sets, is small compared with the word length
Direct Addressing
Address field
contains the
effective address of
the operand

Effective address
(EA) = address
field (A)

Was common in
earlier generations
of computers

Requires only one

memory reference
and no special
calculation

Limitation is that it
provides only a
limited address
space
Indirect Addressing
• Reference to the address of a word in memory which contains a
full-length address of the operand
• EA = (A)
– Parentheses are to be interpreted as meaning contents of

• Advantage:
– For a word length of N an address space of 2N is now available

• Disadvantage:
– Instruction execution requires two memory references to fetch the operand
▪ One to get its address and a second to get its value

▪ A rarely used variant of indirect addressing is multilevel or cascaded indirect

addressing
– EA = ( . . . (A) . . . )
– Disadvantage is that three or more memory references could be required to fetch
an operand
Register Addressing

Address field
refers to a
register rather EA = R
than a main
memory address

Advantages: Disadvantage:
• Only a small • The address space
address field is is very limited
needed in the
instruction
• No time-consuming
memory references
are required
Register Indirect Addressing
• Analogous to indirect addressing
– The only difference is whether the address field refers to a memory
location or a register

• EA = (R)
• Address space limitation of the address field is overcome
by having that field refer to a word-length location
containing an address
• Uses one less memory reference than indirect
addressing
Displacement Addressing
• Combines the capabilities of direct addressing and register
indirect addressing
• EA = A + (R)
• Requires that the instruction have two address fields, at least
one of which is explicit
– The value contained in one address field (value = A) is used directly
– The other address field refers to a register whose contents are added to
A to produce the effective address

• Most common uses:

– Relative addressing
– Base-register addressing
– Indexing
 Relative Addressing

The implicitly referenced register is the program counter (PC)

• The next instruction address is added to the address field to produce the EA
• Typically the address field is treated as a twos complement number for this
operation
• Thus the effective address is a displacement relative to the address of the
instruction

Exploits the concept of locality

Saves address bits in the instruction if most memory references

are relatively near to the instruction being executed
Base-Register Addressing
• The referenced register contains a main memory address and
the address field contains a displacement from that address
• The register reference may be explicit or implicit
• Exploits the locality of memory references
• Convenient means of implementing segmentation
• In some implementations a single segment base register is
employed and is used implicitly
• In others the programmer may choose a register to hold the
base address of a segment and the instruction must reference
it explicitly
Indexing
• The address field references a main memory address and the referenced
register contains a positive displacement from that address
• The method of calculating the EA is the same as for base-register addressing
• An important use is to provide an efficient mechanism for performing iterative
operations
• Autoindexing
– Automatically increment or decrement the index register after each reference to it
– EA = A + (R)
– (R) = (R) + 1

• Postindexing
– Indexing is performed after the indirection
– EA = (A) + (R)

• Preindexing
– Indexing is performed before the indirection
– EA = (A + (R))
Stack Addressing
• A stack is a linear array of locations
– Sometimes referred to as a pushdown list or last-in-first-out queue
• A stack is a reserved block of locations
– Items are appended to the top of the stack so that the block is partially filled
• Associated with the stack is a pointer whose value is the address of the top of
the stack
– The stack pointer is maintained in a register
– Thus references to stack locations in memory are in fact register indirect
addresses

• Is a form of implied addressing

• The machine instructions need not include a memory

reference but implicitly operate on the top of the stack
x86 Addressing Mode Calculation
x86 Addressing Modes
Mode Algorithm
Immediate Operand = A
Register Operand LA = R
Displacement LA = (SR) + A
Base LA = (SR) + (B)
Base with Displacement LA = (SR) + (B) + A
Scaled Index with Displacement LA = (SR) + (I) × S + A
Base with Index and Displacement LA = (SR) + (B) + (I) + A
Base with Scaled Index and Displacement LA = (SR) + (I) × S + (B) + A
Relative LA = (PC) + A

LA = linear address R = register

(X) = contents of X B = base register
SR = segment register I = index register
PC = program counter S = scaling factor
A = contents of an address field in the instruction
ARM Indexing Methods
STRB r0, [r1, #12] Offset
0xC 0x20C 0x5
r0 Destination
0x5 register
r1 for STR
Original
base register
0x200 0x200

(a) Offset

STRB r0, [r1, #12]!

r1 Offset
Updated
base register 0x20C 0xC 0x20C 0x5
r0 Destination
0x5 register
r1 for STR
Original
base register
0x200 0x200

(b) Preindex

STRB r0, [r1], #12

r1 Offset
Updated
base register 0x20C 0xC 0x20C
r0 Destination
0x5 register
r1 for STR
Original
base register
0x200 0x200 0x5

(c) Postindex
ARM Data Processing Instruction Addressing
and Branch Instructions

• Data processing instructions

– Use either register addressing or a mixture of register and
immediate addressing
– For register addressing the value in one of the register operands
may be scaled using one of the five shift operators

• Branch instructions
– The only form of addressing for branch instructions is immediate
– Instruction contains 24 bit value
▪ Shifted 2 bits left so that the address is on a word boundary
▪ Effective range ± 32MB from from the program counter
 ARM Load/Store Multiple Addressing

LDMxx r10, {r0, r1, r4}

STMxx r10, {r0, r1, r4}
I ncrement I ncrement Decrement Decrement
after (I A) before (I B) after (DA) before (DB)
r10
Base register 0x20C (r4) 0x218
(r4) (r1) 0x214
(r1) (r0) 0x210
(r0) (r4) 0x20C
(r1) (r4) 0x208
(r0) (r1) 0x204
(r0) 0x200

Figure 14.4 ARM Load/Store M ultiple Addressing

Instruction Formats

Must include
Define the
an opcode For most
layout of the
and, implicitly instruction
bits of an
or explicitly, sets more than
instruction, in
indicate the one
terms of its
addressing instruction
constituent
mode for each format is used
fields
operand
Instruction Length
• Most basic design issue
• Affects, and is affected by:
– Memory size
– Memory organization
– Bus structure
– Processor complexity
– Processor speed

• Should be equal to the memory-transfer length or one should be a

multiple of the other

• Should be a multiple of the character length, which is usually 8 bits,

and of the length of fixed-point numbers
 Allocation of Bits

Number of Register
Number of
addressing versus
operands
modes memory

Number of Address Address

register sets range granularity
PDP-8 Instruction Formats
M emory Reference I nstructions
Opcode D/I Z/C Displacement
0 2 3 4 5 11

I nput/Output I nstructions
1 1 0 Device Opcode
0 2 3 8 9 11

Register Reference I nstructions

Group 1 Microinstructions
1 1 1 0 CLA CLL CMA CML RAR RAL BSW IAC
0 1 2 3 4 5 6 7 8 9 10 11

Group 2 Microinstructions
1 1 1 1 CLA SMA SZA SNL RSS OSR HLT 0
0 1 2 3 4 5 6 7 8 9 10 11

Group 3 Microinstructions
1 1 1 1 CLA MQA 0 MQL 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11

D/I = Direct/Indirect address IAC = Increment ACcumulator

Z/C = Page 0 or Current page SMA = Skip on Minus Accumulator
CLA = Clear Accumulator SZA = Skip on Zero Accumulator
CLL = Clear Link SNL = Skip on Nonzero Link
CMA = CoMplement Accumulator RSS = Reverse Skip Sense
CML = CoMplement Link OSR = Or with Switch Register
RAR = Rotate Accumultator Right HLT = HaLT
RAL = Rotate Accumulator Left MQA = Multiplier Quotient into Accumulator
BSW = Byte SWap MQL = Multiplier Quotient Load
PDP-10 Instruction Format

Index
Opcode Register I Memory Address
Register
0 8 9 12 14 17 18 35

I = indirect bit

Figure 14.6 PDP-10 I nstruction Format

Variable-Length Instructions

• Variations can be provided efficiently and compactly

• Increases the complexity of the processor
• Does not remove the desirability of making all of the
instruction lengths integrally related to word length
– Because the processor does not know the length of the next
instruction to be fetched a typical strategy is to fetch a number of
bytes or words equal to at least the longest possible instruction
– Sometimes multiple instructions are fetched
Instruction Formats for the PDP-11
1 Opcode Source Destination 2 Opcode R Source 3 Opcode Offet
4 6 6 7 3 6 8 8

4 Opcode FP Destination 5 Opcode Destination 6 Opcode CC

8 2 6 10 6 12 4

7 Opcode R 8 Opcode
13 3 16

9 Opcode Source Destination M emory Address

4 6 6 16

10 Opcode R Source M emory Address

7 3 6 16

11 Opcode FP Source M emory Address

8 2 6 16

12 Opcode Destination M emory Address

10 6 16

13 Opcode Source Destination M emory Address 1 M emory Address 2

4 6 6 16 16

Numbers below fields indicate bit length

Source and Destination each contain a 3-bit addr essing mode field and a 3-bit r egister number
FP indicates one of four floating-point r egisters
R indicates one of the general-purpose r egisters
CC is the condition code field

Figure 14.7 I nstruction Formats for the PDP-11

Example of VAX Instructions
Hexadecimal Explanation Assembler Notation
Format and Description

8 bits
0 5 Opcode for RSB RSB
Return from subroutine

D 4 Opcode for CLRL CLRL R9

5 9 Register R9 Clear register R9

B 0 Opcode for MOVW MOVW 356(R4), 25(R11)

Word displacement mode,
C 4 Register R4
Move a word from address
that is 356 plus contents
6 4 356 in hexadecimal of R4 to address that is
0 1 25 plus contents of R11
Byte displacement mode,
A B Register R11
1 9 25 in hexadecimal

C 1 Opcode for ADDL3 ADDL3 #5, R0, @A[R2]

0 5 Short literal 5 Add 5 to a 32-bit integer in

R0 and store the result in
5 0 Register mode R0
location whose address is
4 2 Index prefix R2 sum of A and 4 times the
Indirect word relative contents of R2
D F (displacement from PC)

Amount of displacement from

PC relative to location A
x86 Instruction Format
0 or 1 0 or 1 0 or 1 0 or 1
bytes bytes bytes bytes
Operand Address
I nstruction Segment
size size
prefix override
override override

0 or 1 0 or 1
0, 1, 2, 3, or 4 bytes 1, 2, or 3 bytes bytes bytes 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes

I nstruction prefixes Opcode M odR/m SI B Displacement I mmediate

M od Reg/Opcode R/M Scale I ndex Base

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ARM Instruction Formats
Examples of Use of ARM Immediate
Constants
Expanding a Thumb ADD Instruction into
its ARM Equivalent
Thumb-2 Instruction Set
• The only instruction set available on the Cortex-M microcontroller
products
• Is a major enhancement to the Thumb instruction set architecture
(ISA)
– Introduces 32-bit instructions that can be intermixed freely with the older 16-bit
Thumb instructions
– Most 32-bit Thumb instructions are unconditional, whereas almost all ARM
instructions can be conditional
– Introduces a new If-Then (IT) instruction that delivers much of the functionality of
the condition field in ARM instructions

• Delivers overall code density comparable with Thumb, together with

the performance levels associated with the ARM ISA
• Before Thumb-2 developers had to choose between Thumb for size
and ARM for performance
Thumb-2 Encoding