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Reconfigurable Computing Lab Assignment 1 (1)

The assignment requires the implementation of a PL-only reconfigurable system on an FPGA using Verilog/VHDL, focusing on the Programmable Logic side. Students must design a 4-bit ALU that supports various operations including addition, subtraction, and logical shifts. The assignment also involves adding constraints, simulating, synthesizing, implementing, and generating a bit stream using Vivado.

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Adithyan J
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16 views

Reconfigurable Computing Lab Assignment 1 (1)

The assignment requires the implementation of a PL-only reconfigurable system on an FPGA using Verilog/VHDL, focusing on the Programmable Logic side. Students must design a 4-bit ALU that supports various operations including addition, subtraction, and logical shifts. The assignment also involves adding constraints, simulating, synthesizing, implementing, and generating a bit stream using Vivado.

Uploaded by

Adithyan J
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Reconfigurable Computing Lab Assignment -1

Objective: Implement a PL-only reconfigurable system on an FPGA using Verilog/VHDL and


simulate its functionality. This assignment focuses solely on the Programmable Logic (PL)
side of the FPGA, without involving the Processing System (PS).

Design a 4-bit ALU (Arithmetic Logic Unit) in Verilog/VHDL that supports the following
operations:
●​ Addition
●​ Subtraction
●​ AND
●​ OR
●​ XOR
●​ Left Shift
●​ Right Shift

Add detailed constraints to your design, simulate, synthesis, implement and generate bit
stream of the design using Vivado

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