Tutorial Sheet EVEN SEM 2025

Computer Organization and Architecture

(15B11CI313)

4th Sem IT & 6 th Sem CSE

Jaypee Institute of Information Technology, Noida

Instruction for Tutorials

1. Tutorial has to be submitted (Turnin) within three days of tutorial class

conducted.
2. Graded tutorial sheet will be returned within week of conduct of tutorial
class by the concerned teacher.
3. All t u t o r i a l s u b m i s s i o n h a s t o b e ha ndw r i t t e n w i t h y o u r n a m e ,
enrollment and batch compulsory on it.
4. End of the semester COA project will be evaluated in tutorial class
5. Attendances are compulsory for all tutorial classes

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 Tutorial Sheet EVEN SEM 2025

Tutorial -7: 8085 Microprocessor

Tutorial-7 is based on the Module 7

Module 7 Instruction Set Architecture (ISA) of 8085- Architecture, Instruction Set, Instruction
Format, Addressing Modes, instruction execution and Datapath Assembly programming for
simple applications.

Reference:
• Ramesh Gaonkar, Microprocessor Architecture Programming and Applications with the 8085,
Prentice Hall, Eight Edition, 2013
• M. Morris Mano, Computer System Architecture, Prentice Hall of India Pvt Ltd, 3rd Edition
(updated) , 30 June 2017.
• William Stallings, Computer Organization and Architecture–Designing for Performance, Ninth
Edition, Pearson Education, 2013.
• https://www.technicalsymposium.com/microprocessor_lab.pdf
• https://www.javatpoint.com/programming-in-8085
• http://www.darshan.ac.in/Upload/DIET/Documents/CE/2150707-MPI-Study
Material_04112017_033410AM.pdf
• http://www.eazynotes.com/notes/microprocessor/Sort-Array-in-Descending-Order.pdf •
https://webstor.srmist.edu.in/web_assets/srm_mainsite/files/2017/cse-lab-manual
microprocessor.pdf

1. Find the machine codes of following 8085 instructions and in each case identify the opcode part,
and register/ memory reference bits. Also mention the length of opcode, number of bytes in the
instruction.
MOV A, M;
MVI C, data;
PUSH B;
ADC B;
XRA L;
JNZ address
LDAX B
2. Translate the following Assembly program of 8085 into machine code (hex format)
MVI C, 20
LXI H, 1500h
MVI A, 00
Next: MOV B, M
ADC B
INX H
DCR C
JNZ Next
STA 1600h
HLT
Assume that the program is to be stored in memory starting at address 1000h

3. Find out the number of machine cycles and the number of T-states taken by the following 8085
instructions. In each case explain your answer.

a) ADC D
b) ADI 05

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c) JMP 1500h
d) JNZ 1500h
e) LDAX B
f) MOV A, B
g) LDA 1300h

4. Translate the sumArray function (written in C below) to 8085 assembly language:

int sumArray (int * p, int n) {
int sum = 0, x;
int * ptr = p; //ptr points to the starting address of array p int
* pend = &p[n]; //pend points to the last element of array p
while (ptr != pend) {
x = *ptr; //x has the value of an element of array p
if (x> 5) sum = x + sum;
ptr++;
}
return sum;
}
You may make suitable assumptions about the values in processor registers before a call to this
function.

5. The contents of Register (B) and Register (A) of 8085 microprocessors are 49H and 3AH
respectively. The contents of A, the status of carry flag (CF) and sign flag (SF) after executing
‘SUB B’ assembly language instruction, are?

6. Write 8085 ALP to generate an accurate time delay of 100ms, and 1 sec.
7. Write 8085 assembly language program to SORT an array of 10 bytes in Descending order.
8. Write an 8085 ALP to perform 32-bit binary addition.
9. Consider the following program segment for an 8085-processor having three user registers A, B and
D.
Instruction Operation Instruction Size (in bytes)

LXI B,5000H B<-5000H 3

LDAX B A<-MEMORY[B] 1
ADD D A<-A+D 1
STA 6000H M [6000] <-A 3
HLT Machine halts 1

Consider that the memory is byte addressable with size 8- bits, and the program has been loaded
starting from memory location 1000 H. If an interrupt occurs while the CPU has been halted after
executing the HALT instruction, the return address (hex) saved in the stack will be? Assume
word size is 16-bit and calculate the return address for the same.

10. Let the clock cycles required for various operations be as follows:
Register to/ from memory transfer: 3 clock cycles
ADD with both operands in register: 1 clock cycle
Instruction fetch and decode: 2 clock cycles per word

Instruction Operation Instruction Size (in bytes)

LXI B,5000H B<-5000H 3

LDAX B A<-MEMORY[B] 1

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ADD D A<-A+D 1
STA 6000H M [6000] <-A 3
HLT Machine halts 1
The total number of clock cycles required to execute the program is?

11. Draw and show appropriate control signal in timing diagram of following:

i. DAD
ii. INX Reg pair
iii. PUSH Reg Pair
iv. PCHL
12. Assume that this program stored at 20AEH location. Write the addressing mode of each
instruction in the following program. Also write the hex code of JNC AHEAD Instruction and
content of PC and A registers after execution of INR C.

LXI H, C050
MVI C,00
MOV A, M
INX H
ADD M
DAA
JNC AHEAD
INR C
AHEAD: STA C053
MOV A, C
STA C052
HLT

13. What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing the
following 8085 programs?

MVI L, 5DH
MVI L, 6BH
MOV A, H
ADD L

14. What is the status of the ZERO flag and the contents of the accumulator after the execution of the
following 8085 assembly code? Assume that contents of all other registers and memory locations are
unknown.

MOV A, 85H
MOV B, 32H
CMP B

15. If the number starts with a letter of the alphabet, you need to add a zero before it. For example,
AB is entered as 0ABh. WHY?

16. A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The
system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices
(memory mapped I/O) and 1 K byte of EERAM (electrically erasable RAM).

(a) Design a memory map (to reduce decoding logic) and show the decoding logic if the components
available are:

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(b) The microprocessor is operating at 12.5 mHz and provides time equivalent to two clock cycles for
memory read and write. Assuming control signals similar to 8085, design the extra logic required for
interfacing EERAM.

17. A microprocessor is capable of addressing 2 megabytes of memory with a 21-bit address bus.
The system to be designed requires 512 K bytes of RAM, 512 K bytes of EPROM, 32 I/O devices
(memory-mapped I/O), and 2 K bytes of EERAM (Electrically Erasable RAM).

(a) Design a memory map to minimize decoding logic for the components available.

(b) The microprocessor is operating at 10 MHz and allows 3 clock cycles for memory read and write
operations. Design the required extra logic for interfacing the EERAM, considering the control
signals similar to an 8085 microprocessor.

18. A microprocessor has a 24-bit address bus capable of addressing 16 megabytes of memory. The
system design requires:

• 1 megabyte of DRAM
• 2 megabytes of EPROM
• 64 I/O devices (memory-mapped I/O)
• 512 bytes of NVRAM (Non-Volatile RAM)

(a) Design an optimal memory map that minimizes decoding logic, and indicate the decoding logic
required for each component.

(b) The microprocessor runs at 16 MHz and supports a memory read/write cycle of 4 clock cycles.
Assuming control signals similar to the 8085, design the necessary extra interfacing logic for the
NVRAM to ensure proper operation within the available clock cycle window.

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