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fibonacci_series_report _

This lab report details the design and implementation of an n-bit Fibonacci generator using Verilog, focusing on both synchronous and asynchronous reset functionalities. The report includes the necessary components such as D flip-flops, full adders, and testbench for verification. Experimental results confirm the correct operation of the Fibonacci sequence generation.

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Aditya Kumar Dhanraj
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26 views8 pages

fibonacci_series_report _

This lab report details the design and implementation of an n-bit Fibonacci generator using Verilog, focusing on both synchronous and asynchronous reset functionalities. The report includes the necessary components such as D flip-flops, full adders, and testbench for verification. Experimental results confirm the correct operation of the Fibonacci sequence generation.

Uploaded by

Aditya Kumar Dhanraj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 1 :- Fibonacci Generator

Lab report
Aditya Kumar
System On Chip Design
IIT PALAKKAD
152402001@smail.iitpkd.ac.in
September 2024

Abstract
This paper presents the design and implementation of a Fi-
bonacci generator using Verilog, a hardware description lan-
guage widely used for digital circuit design

1 Introduction
The Fibonacci series is a famous sequence of numbers in which each number
is the sum of the two preceding ones. It typically starts with 0 and 1. The
sequence can be defined mathematically as follows:
• F(0) = 0
• F(1) = 1
• F(n) = F(n-1) + F(n-2) for n ≥ 2
A Fibonacci generator can be implemented in various programming languages,
allowing users to generate the sequence either as a list or as a series of numbers
on demand.Generators, in particular, are useful in programming because they
allow for memory-efficient computation. Instead of storing the entire sequence
in memory, a generator can yield one number at a time, making it suitable for
scenarios where only a portion of the sequence is needed or when working with
large values of n.By utilizing Fibonacci generators, programmers can efficiently
explore mathematical properties, create algorithms, or even model real-world
phenomena that follow the Fibonacci pattern.It also has applications in com-
puter science, economics, and art.

In this lab we are going to implement the n-bit fibonacci generator with both
synchronous reset and asynchronous reset and also we are going to get the
related waveforms.

1
Figure 1: Block Diagram of fibonacci generator

2 Implementation details
For implementing n-bit fibonacci generator,first we have to implement two n-bit
registers and a n-bit adder.To implement a n-bit register we have to first imple-
ment a D flip-flop and also we have to implement a full adder for implementing
a n-bit adder.Let us see the different components which we are using here to
implement fibonacci generator.

2.1 D Flip-Flop
D flip-flop operates based on the timing of clock signals and the value of the
data input.The characteristic equation of a D flip-flop describes the relationship
between the inputs and the output. It can be expressed as:

Q(t + 1) = D(t)

Block diagram of D flip-flop :

2
Figure 2: D flip-flop

Figure 3: verilog code of D flip-flop

3
2.2 Full Adder
A full adder is a digital circuit that performs addition of binary numbers. It
is capable of adding three inputs: two significant bits and a carry bit from a
previous less significant addition. The output consists of a sum bit and a carry-
out bit.
Characteristic equation :

Sum (s) = A ⊕ B ⊕ C

Cout = (A · B) + (Cin · (A ⊕ B))

Figure 4: Block diagram of full adder

verilog code for full adder :

Figure 5: verilog code of full adder

2.3 N-bit register


The N-bit register is built using multiple D flip-flops. It stores N bits of data and
updates the stored value on the rising edge of the clock signal.To implement N-
bit register we have to instantiate D flip-flop in the verilog code of n-bit register
Verilog code for n-bit register :

4
Figure 6: verilog code of n-bit register

2.4 N-bit adder


An N-bit adder is a digital circuit designed to add two binary numbers that are
each N bits long, along with a carry-in bit. It produces a sum that can be up to
N+1 bits long due to the potential carry-out from the most significant bit.The
implementation of n-bit register in verilog needs the instantiation of full adder.
Verilog code for n-bit adder :

Figure 7: verilog code of n-bit adder

2.5 Fibonacci generator


Fibonacci generator connects two N-bit registers and a N-bit adder to produce
the Fibonacci series. The design includes both synchronous and asynchronous
reset. To implement the fibonacci generator in verilog we have to instantiate
two n-bit register and one n-bit adder.
verilog code for Fibonacci generator :

5
Figure 8: verilog code of fibonacci generator

2.6 Testbench
To verify that the Fibonacci generator correctly computes the Fibonacci se-
quence for a range of input values, we need a testbench.
The testbench will typically include :
• A clock pulse of width 10 nanosecond.
• A width parameter ’n’ which is 8 here.
• A reset pulse and an end time for simulation to end here it is 1000 ns.

verilog code for testbench :

6
Figure 9: Testbench verilog code

7
3 Experiment results
This report presents the experimental results of a Fibonacci generator designed
with both asynchronous and synchronous reset functionalities. The primary
objectives were to validate the correct operation of the Fibonacci sequence gen-
eration and to assess the behavior of the reset mechanisms.

3.1 Asynchronous Reset Result


The graph below shows the output of the Fibonacci generator after an asyn-
chronous reset. The Fibonacci sequence starts after the clock signal is asserted.

Figure 10: Simulation Result with Asynchronous Reset

3.2 synchronous Reset Result


The graph below shows the output of the Fibonacci generator after a 103 syn-
chronous reset. The Fibonacci sequence resumes after either the clock or the
reset is asserted.

Figure 11: Simulation Result with Synchronous Reset

4 Conclusion
In this lab experiment, we successfully designed and implemented a parameter-
ized N-bit Fibonacci generator using Verilog.This lab highlights the capability
of Verilog to model and simulate combinational or sequential logic, allowing us
to generate Fibonacci numbers in real-time.

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